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JP3400525B2 - Method for manufacturing semiconductor device - Google Patents
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JP3400525B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3400525B2
JP3400525B2 JP04352594A JP4352594A JP3400525B2 JP 3400525 B2 JP3400525 B2 JP 3400525B2 JP 04352594 A JP04352594 A JP 04352594A JP 4352594 A JP4352594 A JP 4352594A JP 3400525 B2 JP3400525 B2 JP 3400525B2
Authority
JP
Japan
Prior art keywords
pattern
resist
opening
transparent
photomask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP04352594A
Other languages
Japanese (ja)
Other versions
JPH07253656A (en
Inventor
勝也 早野
昇雄 長谷川
宏 ▲高▼木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Priority to JP04352594A priority Critical patent/JP3400525B2/en
Publication of JPH07253656A publication Critical patent/JPH07253656A/en
Application granted granted Critical
Publication of JP3400525B2 publication Critical patent/JP3400525B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、微細なパタンを選択的
に形成することが可能な半導体装置の製造方法に関す
る。
BACKGROUND OF THE INVENTION The present invention selectively selects fine patterns.
The present invention relates to a method of manufacturing a semiconductor device that can be formed
It

【0002】[0002]

【従来の技術】近年、素子の微細化が進み、よりいっそ
うの微細リソグラフィ技術が要求されている。特に穴パ
タンはステッパの解像特性から配線パタンに比べ微細化
が困難であり、微細化技術の開発が進められている。穴
及び溝パタンの微細化法としては、特開平1−307228 号
公報に記載されているように、レジストパタンを形成
後、レジストの軟化点以上の温度で熱処理し、レジスト
の熱流動によりパタンを縮小化する方法がある。しかし
この方法では、ウエハ全体のレジストパタン全てが熱流
動するため、必要のないパタンまで縮小化してしまい、
パタンによってはつぶれるなどの問題点があった。
2. Description of the Related Art In recent years, elements are becoming finer, and further finer lithography techniques are required. In particular, the hole pattern is more difficult to be miniaturized than the wiring pattern due to the resolution characteristics of the stepper, and the miniaturization technology is being developed. As a method of miniaturizing the hole and groove pattern, as described in JP-A-1-307228, after forming a resist pattern, heat treatment is performed at a temperature equal to or higher than the softening point of the resist, and the pattern is formed by thermal flow of the resist. There is a way to reduce it. However, in this method, the entire resist pattern of the entire wafer is heat-fluidized, so that the unnecessary pattern is reduced,
There were problems such as being crushed depending on the pattern.

【0003】[0003]

【発明が解決しようとする課題】本発明の目的は、パタ
ン転写用ホトマスクの設計を変更することなく、レジス
トの熱流動によるパタン変形によって、選択的に微細な
穴及び溝パタンを形成する方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for selectively forming fine hole and groove patterns by pattern deformation due to thermal flow of a resist without changing the design of a pattern transfer photomask. To provide.

【0004】[0004]

【課題を解決するための手段】上記目的を達成するた
め、本発明は縮小したいパタンに対応するパタン転写用
ホトマスク上の透明パタン周辺を半透明膜としたホトマ
スクを使用して露光,現像し、その後未露光レジストは
軟化せず、露光レジストが軟化する温度で熱処理し、所
望のパタンを選択的にレジストを軟化流動させる。
In order to achieve the above object, the present invention uses a photomask having a semi-transparent film around a transparent pattern on a photomask for pattern transfer corresponding to a pattern to be reduced, and exposure and development are performed. After that, the unexposed resist is not softened, and is heat-treated at a temperature at which the exposed resist is softened to selectively soften and flow a desired pattern.

【0005】[0005]

【作用】縮小したいパタンに対応するパタン転写用ホト
マスク上の透明パタン周辺を半透明にすることにより、
半透明膜を透過した光によって、パタン周辺のレジスト
中の溶解抑止剤の一部を分解する。その結果、未露光レ
ジストに比べ軟化点温度が低くなり、且つ、レジストの
粘度が小さくなるため熱流動しやすくなる。これに熱処
理を加えることより、所望パタンの選択的な縮小化が実
現できる。
[Operation] By making the transparent pattern periphery on the photomask for pattern transfer corresponding to the pattern to be reduced semi-transparent,
The light transmitted through the semitransparent film decomposes part of the dissolution inhibitor in the resist around the pattern. As a result, the softening point temperature becomes lower than that of the unexposed resist, and the viscosity of the resist becomes smaller, so that heat flow easily occurs. By subjecting this to heat treatment, selective reduction of the desired pattern can be realized.

【0006】[0006]

【実施例】図1は、本発明のホトマスクである。同図
(a)はホトマスクの平面図であり、同図(b)はホト
マスクの断面図である。1はガラス基板、2は遮光膜、
3は半透明膜である。ここで遮光膜2及び半透明膜3は
Cr膜を用い、半透明膜3の透過率Tは50%とした。
また、半透明膜3は実験より透明パタン6の周辺に、透
明パタンのエッジから幅Wを0.2μm以上で形成すれ
ば良く、ここでは1.0μmとした。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a photomask of the present invention. The figure (a) is a top view of a photomask, and the figure (b) is a sectional view of a photomask. 1 is a glass substrate, 2 is a light-shielding film,
3 is a semitransparent film. Here, the light shielding film 2 and the semitransparent film 3 are Cr films, and the transmissivity T of the semitransparent film 3 is 50%.
Further, the semi-transparent film 3 may be formed around the transparent pattern 6 by an experiment so that the width W is 0.2 μm or more from the edge of the transparent pattern, and here it is set to 1.0 μm.

【0007】上記マスクの作成は、2回のリソグラフィ
を用い、1回目で透明部6,7のパタンを加工し、2回
目で半透明部を加工した。ここで半透明の制御は遮光膜
2のエッチング深さをコントロールして行った。作成方
法はこのかぎりでなく、例えば、遮光膜を1回目のリソ
グラフィで3,6,7の部分をエッチングし、半透明膜
を全面に被着した後、2回目のリソグラフィで3の部分
に半透明膜が残るように加工しても良い。また半透明膜
にCrを用いたが、CrO,CrON,MoSiO,MoS
iONなど、半透明膜であればよい。また半透明部と透
明部を通過する光の位相差が180°となるような条件
にすれば、パタンの解像特性も向上する。
The above mask was prepared by using lithography twice and processing the patterns of the transparent portions 6 and 7 the first time and the semi-transparent portion the second time. Here, the semitransparent control was performed by controlling the etching depth of the light shielding film 2. This method is not limited to this. For example, the light-shielding film is etched in the third, sixth, and seventh portions by the first lithography, the semi-transparent film is deposited on the entire surface, and then the third portion is half-etched by the second lithography. You may process so that a transparent film may remain. Although Cr was used for the semitransparent film, CrO, CrON, MoSiO, MoS
A translucent film such as iON may be used. Further, if the condition is such that the phase difference between the light passing through the semitransparent portion and the transparent portion is 180 °, the resolution characteristic of the pattern is also improved.

【0008】図2は本発明によるパターン形成方法の原
理を示したものである。同図(a)は図1のホトマスク
を示す。このホトマスクを用いて通常のリソグラフィに
より、同図(b)に示すような被加工基板4の上にレジ
スト5を塗布したものに、通常の露光量以上で露光し、
通常の現像時間以下又は通常濃度以下の現像液で現像
し、同図(c)に示すようにレジストパタンを形成し
た。ここで、パタン転写用ホトマスク内の、周辺が半透
明膜である透明パタン6と周辺が遮光膜である透明パタ
ン7の転写パタン8及び9の寸法Dはほぼ同じであっ
た。
FIG. 2 shows the principle of the pattern forming method according to the present invention. FIG. 3A shows the photomask shown in FIG. By using this photomask by ordinary lithography, a substrate 5 to be processed as shown in FIG. 1B, which is coated with a resist 5, is exposed at a normal exposure amount or more,
Development was carried out with a developing solution having a normal development time or shorter or a normal concentration or lower to form a resist pattern as shown in FIG. Here, in the photomask for pattern transfer, the transfer patterns 8 and 9 of the transparent pattern 6 having a semi-transparent film in the periphery and the transparent pattern 7 having a light-shielding film in the periphery had substantially the same dimension D.

【0009】次に同図(d)に示すように、レジストを
被加工基板ごとベーク炉を用いて、未露光部レジストの
軟化点以下の温度で熱処理を行った。
Next, as shown in FIG. 3D, the resist was heat-treated together with the substrate to be processed in a baking oven at a temperature not higher than the softening point of the unexposed portion resist.

【0010】この熱処理を行うことにより、パタン転写
用ホトマスク内の、周辺が遮光膜である透明パタン7の
転写パタン9の寸法D2は、転写パタン9周辺のレジス
トが未露光であることから、熱処理温度が未露光部レジ
ストの軟化点以下の温度ではレジストの熱流動がなく、
熱処理前の寸法Dから変化しない。これに対し、パタン
転写用ホトマスク内の周辺が半透明膜である透明パタン
6の転写パタン8は、透明パタン周辺の半透明膜を透過
した光によって、転写パタン8周辺のレジストに露光部
10が形成される。露光部10のレジスト中の溶解抑止
剤の一部が分解し、その結果軟化点温度が低くなり、且
つレジストの粘度が小さくなる。これにより露光部10
のレジストが未露光部レジストの軟化点以下の温度で熱
流動が可能となり、転写パタン8は露光部10のレジス
トの流動によって断面形状が変形し、その結果、転写パ
タン8の寸法D1は熱処理前の転写パタン寸法D以下と
なる。したがって、パタン転写用ホトマスクの透明パタ
ンの周辺に、半透明膜を配置するか遮光膜を配置するか
の選択によって、所望のパタンのみ熱流動によるパタン
縮小が可能である。
By performing this heat treatment, the dimension D2 of the transfer pattern 9 of the transparent pattern 7 having a light shielding film in the periphery in the photomask for pattern transfer is determined because the resist around the transfer pattern 9 is not exposed. At temperatures below the softening point of the unexposed area resist, there is no thermal flow of the resist,
It does not change from the dimension D before heat treatment. On the other hand, in the transfer pattern 8 of the transparent pattern 6 in which the periphery of the pattern transfer photomask is a semitransparent film, the exposure portion 10 is exposed to the resist around the transfer pattern 8 by the light transmitted through the semitransparent film around the transparent pattern. It is formed. Part of the dissolution inhibitor in the resist of the exposed area 10 is decomposed, resulting in a lower softening point temperature and a lower viscosity of the resist. As a result, the exposure unit 10
Of the transfer pattern 8 is deformed by the flow of the resist in the exposed portion 10, and as a result, the dimension D1 of the transfer pattern 8 is the same as that before the heat treatment. The transfer pattern size D is less than or equal to D. Therefore, only a desired pattern can be reduced by heat flow by selecting a translucent film or a light-shielding film around the transparent pattern of the pattern transfer photomask.

【0011】図3にパタン転写用ホトマスク内の半透明
膜3を透過した光による露光部10の露光量と、熱処理
後の転写パタン8及び9の寸法D1及びD2の関係を示
す。ここでレジスト5にノボラック系レジストをレジス
ト膜厚1.0μm で塗布し、半透明膜3の透過率Tが5
0%であるパタン転写用ホトマスクを用いて露光,現像
した後、レジストの軟化流動によってパタンを縮小させ
ることを目的とする熱処理をベーク炉を用いて、熱処理
温度120℃で、180秒間熱処理した。熱処理前の転
写パタン寸法Dは、0.45μm である。
FIG. 3 shows the relationship between the exposure amount of the exposed portion 10 by the light transmitted through the semitransparent film 3 in the pattern transfer photomask and the dimensions D1 and D2 of the transfer patterns 8 and 9 after the heat treatment. Here, a novolac-based resist is applied to the resist 5 with a resist film thickness of 1.0 μm, and the transmissivity T of the semitransparent film 3 is 5 μm.
After exposing and developing using a 0% pattern transfer photomask, a heat treatment for the purpose of reducing the pattern by softening flow of the resist was performed in a baking furnace at a heat treatment temperature of 120 ° C. for 180 seconds. The transfer pattern dimension D before heat treatment is 0.45 μm.

【0012】半透明膜3を透過した光による露光部10
の露光量が50mJ/平方cm2 以上でレジストパタン寸
法が変化しはじめ、300mJ/cm2 以上で寸法はほと
んど変化しなくなった。上記パタン転写用ホトマスクを
用いて露光量620mJ/cm2 で露光したところ、パタ
ン転写用ホトマスク内の周辺が半透明膜である透明パタ
ン6の転写パタン8の寸法D1は0.38μm となっ
た。従って半透明膜3を透過した光による露光部10の
露光量は50mJ/cm2 以上になるよう、半透明膜3の
透過率T及び全体の露光量を設定すれば目的は達成され
る。
Exposure unit 10 by light transmitted through the semitransparent film 3
The amount of exposure is 50 mJ / sq cm 2 or more resist pattern dimension is changed initially in the dimensions at 300 mJ / cm 2 or more was hardly changed. When exposure was performed with an exposure amount of 620 mJ / cm 2 using the pattern transfer photomask, the dimension D1 of the transfer pattern 8 of the transparent pattern 6 having a semitransparent film in the periphery of the pattern transfer photomask was 0.38 μm. Therefore, the object can be achieved by setting the transmittance T of the semitransparent film 3 and the total exposure amount so that the exposure amount of the exposed portion 10 by the light transmitted through the semitransparent film 3 becomes 50 mJ / cm 2 or more.

【0013】以上の熱処理条件において、パタン転写用
ホトマスクの透明パタン周辺が遮光膜であるパタン7の
転写パタン9の寸法D2は熱処理前と変化がなく、従っ
て、パタン転写用ホトマスク上に半透明膜を配置するこ
とにより、所望パタンのみの選択的なレジスト熱流動が
可能となり、パタンの選択的な縮小化が実現できた。
Under the above heat treatment conditions, the dimension D2 of the transfer pattern 9 of the pattern 7 having the light-shielding film around the transparent pattern of the pattern transfer photomask does not change from that before the heat treatment. Therefore, the semitransparent film is formed on the pattern transfer photomask. By arranging, it becomes possible to selectively heat-flow the resist only in the desired pattern, and the pattern can be selectively reduced.

【0014】なお、ここでは、レジストの軟化流動によ
ってパタンを縮小させることを目的とする熱処理温度及
び熱処理時間,パタン転写用ホトマスクの半透明膜の透
過率及びパタン寸法,形状を上記のように限定したがこ
れに限らない。また、レジストの軟化流動によってパタ
ンを縮小させることを目的とする熱処理温度を、未露光
部レジストの軟化点以下の温度としたが、軟化点以上の
温度でもパタンの縮小化はできる。この場合は、両者で
流動の度合いが異なることを利用する。
Here, the heat treatment temperature and heat treatment time for reducing the pattern by softening flow of the resist, the transmissivity and the pattern size and shape of the semitransparent film of the pattern transfer photomask are limited as described above. However, it is not limited to this. Further, the heat treatment temperature for the purpose of reducing the pattern by the softening flow of the resist is set to a temperature equal to or lower than the softening point of the unexposed portion resist, but the pattern can be reduced at a temperature equal to or higher than the softening point. In this case, the fact that the degree of flow differs between the two is used.

【0015】ここで、レジスト5にはポジ型ノボラック
系の樹脂を主成分とするレジストを用いたが、これに限
らない。熱流動を起こす材料であり、且つ光照射によっ
て軟化点が低下する材料であれば用いることができる。
ここで使用したノボラック系レジストの、未露光部が熱
流動を起こす温度は130℃以上であった。
Although a resist containing a positive novolac resin as a main component is used as the resist 5, the present invention is not limited to this. Any material can be used as long as it is a material which causes heat flow and whose softening point is lowered by light irradiation.
The temperature at which the unexposed portion of the novolac-based resist used here causes thermal flow was 130 ° C. or higher.

【0016】また、パタン転写用ホトマスクの半透明膜
をホトマスク上に配置したものを用いて一度の露光で上
記効果を得られるよう半透明膜の透過率等各条件を設定
したが、半透明パタンと同じ配置で透明パタンを持つホ
トマスクを用いて、通常のパタン転写用ホトマスクを用
いてパタンを形成した後に再度露光し、その後上記条件
と同様の熱処理を施しても同様に所望のパタンのみを選
択的に縮小できることは言うまでもない。なお、縮小化
したパタンの平面形状は、穴パタン,溝パタンであるが
これに限らない。また穴パタンをここでは正方形を用い
たが、これに限らず円,楕円はもちろん、三角形又は五
角形等の多角形等でも良い。
Further, the conditions such as the transmissivity of the semitransparent film were set so that the above effect can be obtained by one exposure using the translucent film of the pattern transfer photomask arranged on the photomask. Select a desired pattern in the same manner even if you perform a heat treatment similar to the above conditions after forming a pattern using a normal pattern transfer photomask using a photomask with a transparent pattern in the same arrangement as above It goes without saying that it can be reduced. The planar shape of the reduced pattern is a hole pattern or a groove pattern, but is not limited to this. Although the hole pattern is a square here, the hole pattern is not limited to this, and may be a circle, an ellipse, a polygon such as a triangle or a pentagon.

【0017】パタン転写用ホトマスクを用い、この方法
で超LSIの電極取り出し用穴パタンを形成したとこ
ろ、所望のパタンのみを選択的に縮小することが実現で
き、より高密度な配線が実現できた。
When a pattern transfer photomask was used to form the electrode extraction hole pattern of the VLSI by this method, only a desired pattern could be selectively reduced, and higher density wiring could be realized. .

【0018】[0018]

【発明の効果】本発明の適用により、解像限界を超えた
微細なパタンを選択的に簡単な処理により形成できる。
特に微細化の困難な超LSIの電極取り出し用穴パタン
の選択的な微細化が実現でき、超LSIの製造を光リソ
グラフィを用いて実現することが可能となり、工業的に
極めて有利である。
By applying the present invention, a fine pattern exceeding the resolution limit can be selectively formed by a simple process.
In particular, it is possible to realize selective miniaturization of the electrode extraction hole pattern of the VLSI, which is difficult to miniaturize, and to realize the VLSI production using optical lithography, which is extremely advantageous industrially.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の説明図。FIG. 1 is an explanatory diagram of an embodiment of the present invention.

【図2】本発明の一実施例の製造工程の説明図。FIG. 2 is an explanatory diagram of a manufacturing process according to an embodiment of the present invention.

【図3】本発明の種々の実施例の説明図。FIG. 3 is an explanatory view of various embodiments of the present invention.

【符号の説明】[Explanation of symbols]

1…ガラス基板、2…遮光膜、3…半透明膜、4…被加
工基板、5…レジスト、6…周辺が半透明膜である透明
パタン、7…周辺が遮光膜である透明パタン、8…周辺
が半透明膜である透明パタンの転写パタン、9…周辺が
遮光膜である透明パタンの転写パタン、10…半透明膜
を透過した光による露光部。
DESCRIPTION OF SYMBOLS 1 ... Glass substrate, 2 ... Light-shielding film, 3 ... Semi-transparent film, 4 ... Processed substrate, 5 ... Resist, 6 ... Transparent pattern whose periphery is a semi-transparent film, 7 ... Transparent pattern whose periphery is a light-shielding film, 8 ... Transfer pattern of transparent pattern having a semi-transparent film in the periphery, 9 ... Transfer pattern of transparent pattern having a light-shielding film in the periphery, 10 ... Exposure part by light transmitted through the semi-transparent film.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 ▲高▼木 宏 東京都小平市上水本町5丁目20番1号 日立超エル・エス・アイ・エンジニアリ ング株式会社内 (56)参考文献 特開 平4−143765(JP,A) 特開 平1−258419(JP,A) 特開 昭59−232418(JP,A) (58)調査した分野(Int.Cl.7,DB名) G03F 1/00 - 1/16 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor ▲ Hiroshi Takagi 5-20-1 Kamisuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Ultra LSI Engineering Co., Ltd. (56) References Special Kaihei 4-143765 (JP, A) JP-A 1-258419 (JP, A) JP-A 59-232418 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) G03F 1 / 00-1/16

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板上にレジスト層を形成する工程
と、半透明領域と前記半透明領域内に設けられた第1開口部
と、遮光領域と前記遮光領域内に設けられた第2開口部
とを有するホトマスクを介して前記レジスト層を露光す
る工程と、 露光された前記レジスト層を現像し、前記第1開口部及
び第2開口部にそれぞれ対応する第1開口パタン及び第
2開口パタンを有するレジストパタンを形成する工程
と、 その後、前記第1開口パタン周辺のレジスト層を軟化流
動させ、前記第2開口パタン周辺のレジスト層は流動さ
せないように前記半導体基板を熱処理する工程とを有す
ることを特徴とする半導体装置の製造方法。
1. A step of forming a resist layer on a semiconductor substrate, a semitransparent region, and a first opening provided in the semitransparent region.
And a light shielding area and a second opening provided in the light shielding area
Exposing the resist layer through a photomask having
And a step of developing the exposed resist layer to expose the first opening and
And the first opening pattern and the first opening pattern respectively corresponding to the second opening and the second opening.
Process of forming a resist pattern having a two-opening pattern
And then softening the resist layer around the first opening pattern.
And the resist layer around the second opening pattern is fluidized.
Heat treating the semiconductor substrate to prevent
A method of manufacturing a semiconductor device, comprising:
【請求項2】前記第1開口部は穴パタンであることを特
徴とする請求項1記載の半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the first opening is a hole pattern.
【請求項3】前記第2開口部は穴パタンであることを特
徴とする請求項1又は2記載の半導体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the second opening is a hole pattern.
JP04352594A 1994-03-15 1994-03-15 Method for manufacturing semiconductor device Expired - Fee Related JP3400525B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04352594A JP3400525B2 (en) 1994-03-15 1994-03-15 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04352594A JP3400525B2 (en) 1994-03-15 1994-03-15 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH07253656A JPH07253656A (en) 1995-10-03
JP3400525B2 true JP3400525B2 (en) 2003-04-28

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Country Link
JP (1) JP3400525B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010025764A (en) * 1998-12-30 2001-04-06 박종섭 Light transmittance control reticle and developing method for photosensitive material using same
KR100555463B1 (en) * 1999-01-18 2006-03-03 삼성전자주식회사 Photoresist Flow Method
JP2006133785A (en) * 2004-11-08 2006-05-25 Lg Micron Ltd Halftone mask, method of manufacturing the same, and flat display manufactured thereby
KR100848815B1 (en) * 2004-11-08 2008-07-28 엘지마이크론 주식회사 Half tone mask and fabricating method and flat panel displayq
CN111856888B (en) * 2020-07-03 2023-06-23 儒芯微电子材料(上海)有限公司 Method for enhancing photoetching resolution of dense graph

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