JP3401994B2 - Semiconductor resistance element and method of manufacturing the same - Google Patents
Semiconductor resistance element and method of manufacturing the sameInfo
- Publication number
- JP3401994B2 JP3401994B2 JP12990195A JP12990195A JP3401994B2 JP 3401994 B2 JP3401994 B2 JP 3401994B2 JP 12990195 A JP12990195 A JP 12990195A JP 12990195 A JP12990195 A JP 12990195A JP 3401994 B2 JP3401994 B2 JP 3401994B2
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- polycrystalline silicon
- resistance region
- single crystal
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title description 7
- 238000009792 diffusion process Methods 0.000 claims description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 24
- 239000013078 crystal Substances 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】Detailed Description of the Invention
【０００１】[0001]
【産業上の利用分野】本発明は、温度依存性の低減が図
れる半導体抵抗素子及びその製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor resistance element capable of reducing temperature dependence and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、半導体集積回路において、半導体
抵抗素子としては、シリコン基板に形成された単結晶拡
散抵抗または多結晶シリコン抵抗が用いられていた。こ
れらの抵抗素子は、単独で、または、直列あるいは並列
に接続されて用いられていた。単結晶拡散抵抗の場合、
温度の上昇につれてその抵抗率は増加する性質があり、
その温度係数は正の値となっていた。逆に、多結晶シリ
コン抵抗の場合は、温度の上昇につれてその抵抗率は減
少し、その温度係数は負の値となっていた。2. Description of the Related Art Conventionally, in a semiconductor integrated circuit, a single crystal diffusion resistance or a polycrystalline silicon resistance formed on a silicon substrate has been used as a semiconductor resistance element. These resistance elements have been used alone or connected in series or in parallel. For single crystal diffusion resistors,
Its resistivity has the property of increasing with increasing temperature,
The temperature coefficient was a positive value. On the contrary, in the case of a polycrystalline silicon resistor, its resistivity decreased with increasing temperature, and its temperature coefficient had a negative value.
【０００３】[0003]
【発明が解決しようとする課題】ところで、半導体集積
回路は、自動車搭載用あるいは宇宙開発用などのように
これまで以上に広い温度範囲における環境での使用が求
められているが、以上に説明したように、従来の半導体
抵抗素子は温度依存性を有しているため、周囲温度の変
化に従ってその抵抗値が変化し、回路設計値とのズレが
発生するという点が問題となっていた。By the way, the semiconductor integrated circuit is required to be used in an environment in a wider temperature range than ever, such as for mounting on an automobile or for space development. As described above, since the conventional semiconductor resistance element has temperature dependency, its resistance value changes according to the change of the ambient temperature, which causes a problem that the deviation from the circuit design value occurs.
【０００４】本発明は、上記問題点に鑑みなされたもの
で、その目的とするところは、広い温度範囲にわたっ
て、周囲温度変化による抵抗値の変化を低減することが
できる半導体抵抗素子の構造及びその製造方法を提供す
ることにある。The present invention has been made in view of the above problems, and an object thereof is to provide a structure of a semiconductor resistance element capable of reducing a change in resistance value due to a change in ambient temperature and a structure thereof. It is to provide a manufacturing method.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するた
め、請求項１記載の半導体抵抗素子は、シリコン基板の
表面に形成された単結晶拡散抵抗領域で構成される、正
の温度係数を有する単結晶拡散抵抗と、前記単結晶拡散
抵抗領域に接するように前記シリコン基板に埋め込まれ
た多結晶シリコン抵抗領域で構成され前記単結晶拡散抵
抗と直列に接続される、負の温度係数を有する多結晶シ
リコン抵抗とを備えたことを特徴とするものである。In order to achieve the above object, the semiconductor resistance element according to claim 1 has a positive temperature coefficient constituted by a single crystal diffusion resistance region formed on the surface of a silicon substrate. A single crystal diffusion resistor and a polycrystalline silicon resistance region embedded in the silicon substrate so as to be in contact with the single crystal diffusion resistance region and connected in series with the single crystal diffusion resistor have a negative temperature coefficient. It is characterized by having a crystalline silicon resistor.
【０００６】請求項２記載の半導体抵抗素子の製造方法
は、シリコン基板の表面に単結晶拡散抵抗領域を形成す
る工程と、前記単結晶拡散抵抗領域に接する、前記シリ
コン基板の所定領域のシリコンを除去して凹部を形成す
る工程と、その凹部の内部に多結晶シリコンを堆積させ
る工程とを備えたことを特徴とするものである。According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor resistance element, wherein a step of forming a single crystal diffusion resistance region on a surface of a silicon substrate, and a step of forming silicon in a predetermined region of the silicon substrate in contact with the single crystal diffusion resistance region. The method is characterized by including a step of removing and forming a concave portion, and a step of depositing polycrystalline silicon inside the concave portion.
【０００７】[0007]
【作用】請求項１記載の半導体抵抗素子は、シリコン基
板上で、正の温度係数を有する単結晶拡散抵抗と、負の
温度係数を有する多結晶シリコン抵抗とを直列に接続し
たものであり、周囲温度の上昇による、単結晶拡散抵抗
の抵抗増加量と多結晶シリコン抵抗の抵抗減少量とが略
等しくなるように、例えば、２つの抵抗領域の長さの比
を設定して、所定の温度範囲で、周囲温度変化による半
導体抵抗素子の抵抗値の変化が小さくなるように構成し
たものである。According to a first aspect of the present invention, there is provided a semiconductor resistance element in which a single crystal diffusion resistance having a positive temperature coefficient and a polycrystalline silicon resistance having a negative temperature coefficient are connected in series on a silicon substrate. For example, the ratio of the lengths of the two resistance regions is set so that the resistance increase amount of the single crystal diffusion resistance and the resistance decrease amount of the polycrystalline silicon resistance due to the increase of the ambient temperature are substantially equal to each other, and the predetermined temperature is set. Within the range, the change in the resistance value of the semiconductor resistance element due to the change in ambient temperature is configured to be small.
【０００８】また、請求項１記載の半導体抵抗素子で
は、多結晶シリコン抵抗となる多結晶シリコン抵抗領域
が、シリコン基板に埋め込まれているので、シリコン基
板の平坦性を損ねることがない。Further, in the semiconductor resistance element according to the first aspect, since the polycrystalline silicon resistance region serving as the polycrystalline silicon resistance is embedded in the silicon substrate, the flatness of the silicon substrate is not impaired.
【０００９】[0009]
【実施例】図１（ｅ）の断面図に基づいて本発明の半導
体抵抗素子の一実施例について説明する。図１（ｅ）
で、１はＮ型のシリコン基板、２はシリコン基板１の表
面に形成された、単結晶拡散抵抗領域であるＰ型拡散抵
抗領域、３はシリコン基板１の表面に形成された層間絶
縁酸化膜、４はＰ型拡散抵抗領域２に接するようにシリ
コン基板１に埋め込まれ、その上面がシリコン基板１の
表面と略面一となるように形成された多結晶シリコン抵
抗領域、５は層間絶縁酸化膜３に形成されたコンタクト
窓を介して、それぞれ、Ｐ型拡散抵抗領域２及び多結晶
シリコン抵抗領域４に接続されたAl電極配線である。ま
た、Ａは多結晶シリコン抵抗領域４で構成される多結晶
シリコン抵抗、ＢはＰ型拡散抵抗領域２で構成されるＰ
型拡散抵抗である。図１に示す半導体抵抗素子は、この
ように、多結晶シリコン抵抗ＡとＰ型拡散抵抗Ｂとを直
列に接続して、それぞれの抵抗領域に接続したAl電極配
線５からその合成抵抗値を取り出すように構成したもの
である。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor resistance element of the present invention will be described with reference to the sectional view of FIG. Figure 1 (e)
1 is an N-type silicon substrate, 2 is a P-type diffusion resistance region which is a single crystal diffusion resistance region formed on the surface of the silicon substrate 1, and 3 is an interlayer insulating oxide film formed on the surface of the silicon substrate 1. 4 is a polycrystalline silicon resistance region which is embedded in the silicon substrate 1 so as to be in contact with the P type diffusion resistance region 2 and whose upper surface is substantially flush with the surface of the silicon substrate 1. Al electrode wirings connected to the P-type diffusion resistance region 2 and the polycrystalline silicon resistance region 4, respectively, through the contact windows formed in the film 3. A is a polycrystalline silicon resistor composed of the polycrystalline silicon resistance region 4, and B is P composed of the P-type diffusion resistance region 2.
Type diffusion resistance. In the semiconductor resistance element shown in FIG. 1, the polycrystalline silicon resistance A and the P-type diffusion resistance B are thus connected in series, and the combined resistance value is taken out from the Al electrode wiring 5 connected to each resistance region. It is configured as follows.
【００１０】ここで、多結晶シリコン抵抗領域４とＰ型
拡散抵抗領域２の形状については、その長さのみが異な
るように形成されており、多結晶シリコン抵抗領域４の
長さａと、Ｐ型拡散抵抗領域２の長さｂの比が、ａ：ｂ
＝tb：ta（ta；多結晶シリコン抵抗領域４で構成される
多結晶シリコン抵抗Ａの温度係数、tb；Ｐ型拡散抵抗領
域２で構成されるＰ型拡散抵抗Ｂの温度係数）となるよ
うに形成されている。このように構成することによっ
て、周囲温度の変化による、Ｐ型拡散抵抗Ｂの抵抗値の
変化量と多結晶シリコン抵抗Ａの抵抗値の変化量が略打
ち消しあうので、所定の周囲温度範囲で、半導体抵抗素
子の温度係数を小さくすることができ、その抵抗値の変
化を小さくすることができる。Here, the shapes of the polycrystalline silicon resistance region 4 and the P-type diffusion resistance region 2 are formed so that only the lengths thereof are different, and the length a of the polycrystalline silicon resistance region 4 and P The ratio of the length b of the type diffusion resistance region 2 is a: b
= Tb: ta (ta; temperature coefficient of polycrystalline silicon resistance A composed of polycrystalline silicon resistance region 4, tb; temperature coefficient of P type diffusion resistance B composed of P type diffusion resistance region 2) Is formed in. With this configuration, the amount of change in the resistance value of the P-type diffusion resistance B and the amount of change in the resistance value of the polycrystalline silicon resistor A due to the change in the ambient temperature substantially cancel each other. The temperature coefficient of the semiconductor resistance element can be reduced, and the change in its resistance value can be reduced.
【００１１】次に、図１（ａ）〜図１（ｅ）に基づいて
本発明の半導体抵抗素子の製造方法の一実施例について
説明する。まず、（ａ）に示すように、Ｎ型のシリコン
基板１の表面の所定領域に、ボロンイオンを注入して熱
処理を行い、単結晶拡散抵抗領域であるＰ型拡散抵抗領
域２を形成する。次に、（ｂ）に示すように、シリコン
基板１上に酸化膜６を形成し、多結晶シリコン抵抗領域
となる部分の長さａと、Ｐ型拡散抵抗領域２の長さｂの
比が、ａ：ｂ＝tb：ta（ta；多結晶シリコン抵抗Ａの温
度係数、tb；Ｐ型拡散抵抗Ｂの温度係数）となるよう
に、多結晶シリコン抵抗領域となる領域上の酸化膜６を
エッチングにより除去する。Next, an embodiment of the method for manufacturing a semiconductor resistance element of the present invention will be described with reference to FIGS. 1 (a) to 1 (e). First, as shown in (a), boron ions are implanted into a predetermined region of the surface of the N-type silicon substrate 1 and heat treatment is performed to form a P-type diffusion resistance region 2 which is a single crystal diffusion resistance region. Next, as shown in (b), an oxide film 6 is formed on the silicon substrate 1, and the ratio of the length a of the polycrystalline silicon resistance region to the length b of the P-type diffusion resistance region 2 is set. , A: b = tb: ta (ta; temperature coefficient of polycrystalline silicon resistance A, tb; temperature coefficient of P-type diffusion resistance B), the oxide film 6 on the polycrystalline silicon resistance region is formed. Remove by etching.
【００１２】次に、シリコン基板１の露出した部分のシ
リコンをエッチングにより除去して、（ｃ）に示すよう
に、Ｐ型拡散抵抗領域２に接する凹部７を形成し、酸化
膜６を除去する。この場合、凹部７の深さがＰ型拡散抵
抗領域２の深さと同じになるように構成する。その後、
LP-CVDにより、シリコン基板１の表面に多結晶シリコン
を堆積させ、（ｄ）に示すように、凹部７の内部のみに
多結晶シリコンが残るように、その他の領域に堆積した
多結晶シリコンをエッチングにより除去して、Ｐ型拡散
抵抗領域２に接する多結晶シリコン抵抗領域４を形成す
る。Next, the silicon in the exposed portion of the silicon substrate 1 is removed by etching to form a recess 7 in contact with the P type diffusion resistance region 2 and the oxide film 6 is removed, as shown in FIG. . In this case, the depth of the recess 7 is the same as the depth of the P-type diffusion resistance region 2. afterwards,
Polycrystalline silicon is deposited on the surface of the silicon substrate 1 by LP-CVD, and as shown in (d), the polycrystalline silicon deposited in other regions is left so that the polycrystalline silicon remains only inside the recess 7. By removing by etching, a polycrystalline silicon resistance region 4 in contact with the P type diffusion resistance region 2 is formed.
【００１３】最後に、（ｅ）に示すように、シリコン基
板１上に、層間絶縁酸化膜３を形成し、この層間絶縁酸
化膜３の一部分をエッチングにより除去して、半導体抵
抗素子の電極をとるためのコンタクトを形成し、Ｐ型拡
散抵抗領域２と多結晶シリコン抵抗領域４のそれぞれの
領域に接するAl電極配線５を形成する。Finally, as shown in (e), an interlayer insulating oxide film 3 is formed on the silicon substrate 1, a part of the interlayer insulating oxide film 3 is removed by etching, and an electrode of the semiconductor resistance element is formed. A contact for taking is formed, and an Al electrode wiring 5 is formed in contact with each of the P type diffusion resistance region 2 and the polycrystalline silicon resistance region 4.
【００１４】なお、実施例では、単結晶拡散抵抗領域と
多結晶シリコン抵抗領域の形状は、長さのみが異なると
して説明したが、実施例に示した形状に限定されるもの
ではない。In the embodiment, the shapes of the single crystal diffusion resistance region and the polycrystalline silicon resistance region are different only in length, but the shapes are not limited to those shown in the embodiment.
【００１５】[0015]
【発明の効果】請求項１記載の半導体抵抗素子または請
求項２記載の半導体抵抗素子の製造方法によれば、所定
の温度範囲で、周囲温度変化による抵抗値の変化が小さ
い、シリコン基板の平坦性を損ねることがない半導体抵
抗素子を実現することができる。According to the semiconductor resistance element of the first aspect or the method of manufacturing the semiconductor resistance element of the second aspect, the flatness of the silicon substrate in which the change in the resistance value due to the ambient temperature change is small in a predetermined temperature range. It is possible to realize a semiconductor resistance element that does not impair the property.
【図１】本発明の半導体抵抗素子の製造方法の一実施例
を示す断面図である。FIG. 1 is a cross-sectional view showing one embodiment of a method for manufacturing a semiconductor resistance element of the present invention.
１ シリコン基板
２ Ｐ型拡散抵抗領域（単結晶拡散抵抗
領域）
４ 多結晶シリコン抵抗領域
７ 凹部
Ａ 多結晶シリコン抵抗
Ｂ 単結晶拡散抵抗DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 P-type diffusion resistance region (single crystal diffusion resistance region) 4 Polycrystalline silicon resistance region 7 Recess A Polycrystalline silicon resistance B Single crystal diffusion resistance
Claims (2)
拡散抵抗領域で構成される、正の温度係数を有する単結
晶拡散抵抗と、前記単結晶拡散抵抗領域に接するように
前記シリコン基板に埋め込まれた多結晶シリコン抵抗領
域で構成され前記単結晶拡散抵抗と直列に接続される、
負の温度係数を有する多結晶シリコン抵抗とを備えたこ
とを特徴とする半導体抵抗素子。1. A single crystal diffusion resistance having a positive temperature coefficient, which is composed of a single crystal diffusion resistance region formed on a surface of a silicon substrate, and embedded in the silicon substrate so as to be in contact with the single crystal diffusion resistance region. Formed of a polycrystalline silicon resistance region and connected in series with the single crystal diffusion resistor,
A semiconductor resistance element, comprising: a polycrystalline silicon resistance having a negative temperature coefficient.
域を形成する工程と、前記単結晶拡散抵抗領域に接す
る、前記シリコン基板の所定領域のシリコンを除去して
凹部を形成する工程と、その凹部の内部に多結晶シリコ
ンを堆積させる工程とを備えたことを特徴とする半導体
抵抗素子の製造方法。2. A step of forming a single crystal diffusion resistance region on a surface of a silicon substrate, a step of removing silicon in a predetermined region of the silicon substrate which is in contact with the single crystal diffusion resistance region to form a recess, and And a step of depositing polycrystalline silicon inside the recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12990195A JP3401994B2 (en) | 1995-05-29 | 1995-05-29 | Semiconductor resistance element and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12990195A JP3401994B2 (en) | 1995-05-29 | 1995-05-29 | Semiconductor resistance element and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08330514A JPH08330514A (en) | 1996-12-13 |
| JP3401994B2 true JP3401994B2 (en) | 2003-04-28 |
Family
ID=15021191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12990195A Expired - Lifetime JP3401994B2 (en) | 1995-05-29 | 1995-05-29 | Semiconductor resistance element and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3401994B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10317466A1 (en) * | 2003-04-16 | 2004-12-09 | Robert Bosch Gmbh | electric motor |
| KR100699833B1 (en) * | 2005-01-22 | 2007-03-27 | 삼성전자주식회사 | Resistance element having uniform resistance value and semiconductor device using same |
-
1995
- 1995-05-29 JP JP12990195A patent/JP3401994B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08330514A (en) | 1996-12-13 |
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