JP3402844B2 - Image input device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image input device for illuminating a document or the like and inputting an image thereof in a copying machine, an image scanner or the like, and more particularly to controlling the light output of a light source thereof.

[0002]

2. Description of the Related Art Conventionally, a fluorescent lamp, which is advantageous in power consumption and heat generation, is used as a light source for illuminating a document. However, since the fluorescent lamp has a large variation in the light quantity, in order to control the light quantity to a constant value, feedback control is performed to detect the light quantity of the fluorescent lamp and change the lamp current of the fluorescent lamp so that the output becomes constant. The control system uses a timer IC such as an operational amplifier or 555, and control for switching the loop gain is not performed.
Note that the control target here is the intensity of the light illuminating the original, which is called "light amount" according to the convention in this field.

[0003]

However, in the above-mentioned conventional example, it was difficult to achieve both the stability of the light quantity control and the quick rise of the light quantity.

In recent years, there has been a demand for further shortening of the first copy time in a copying machine, and a higher quality image is also demanded.

The present invention has been made in order to solve such a problem, and achieves both stability of light quantity control and quick start-up of the light quantity at the same time to shorten the first copy time and realize high image quality. It is an object of the present invention to provide an image input device that can be used.

[0006]

In order to achieve the above-mentioned object, in the present invention, an image input device is constructed as in the following (1) to (5).

(1) A light source for irradiating an original or the like, a light amount detecting means for detecting the light amount of the light source, a comparing means for comparing the output of the light amount detecting means with a reference value, and a variable dividing means for variably dividing the clock. According to the output of the circumference means and the comparison means,
In synchronization with the clock divided by the variable divider
Counting means for increasing or decreasing the count value by 1, power supply means for supplying power to the light source according to the count value of the counting means, state detecting means for detecting the state of the device, and state detecting means The image input device comprising: a control unit that changes the frequency division ratio of the variable frequency division unit according to the output of

[0008] (2) said state detecting means is for detecting the time from the start of lighting of the light source, the control means
The frequency division ratio of the variable frequency dividing means is set low at the initial lighting of the light source.
The image input device according to (1) above, which is increased after a predetermined time .

[0009] (3) the state detecting means is adapted to detect the light quantity of the light source, the control means the variable frequency divider hand
If the light amount of the light source is low, lower the step division ratio
The image input device according to (1) above, which is increased when the amount of light becomes close to the light amount .

[0010] (4) The state detection device is for detecting the temperature near the light source, the control means the variable frequency
If the temperature near the light source is low, lower the frequency division ratio
The image input device according to (1) above, which is increased when the temperature of the characteristics of the light source becomes stable .

[0011] (5) The light source is a fluorescent lamp, before
The lighting time of the fluorescent lamp can be changed by the power supply means.
The image input device according to any one of (1) to (4), wherein the light amount of the fluorescent lamp is adjusted by .

[0012]

With the configurations (1) to (5), the count speed of the counting means changes according to the state of the device, and the loop gain of the dimming control changes.

[0013]

EXAMPLES The present invention will be described in detail below with reference to examples.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a main part (a light control unit of a document illumination lamp) of a "copying machine" according to a first embodiment. In the figure, 51 is a CPU that controls the entire control. The address / data bus 80 of the CPU 51 is connected to the PWM circuit 50. PWM circuit 50
Output 96 is connected to ballast 70. In the ballast 70, the signal 96 is "1" for the fluorescent lamp 71 which is the original illumination lamp.
Light only during the period. Therefore, the light quantity of the fluorescent lamp 71 can be adjusted by changing the pulse width (duty ratio) of the signal 96. Part of the light emitted from the fluorescent lamp 71 is applied to the light amount sensor 72, where it is converted into a voltage signal 97 and input to the comparator 68. The reference voltage 69 is connected to the other input of the comparator 68, and the comparator 68 outputs "1" when the voltage of the signal 97 is lower than the reference voltage 69, that is, when the light amount is lower than the target value, and vice versa. In the case, "0" is output. The output 90 of the comparator 68 is input to the PWM circuit 50. Further, the signal 97 is connected to the CPU 51 and the CPU 5
1 can know the light amount of the fluorescent lamp 71.

Reference numeral 53 is an 8 MHz oscillator. Again 67
Is an oscillator that determines the PWM cycle (lighting cycle of the fluorescent lamp 71), and is 1 to 2 KHz. In the case of a digital copying machine, a signal synchronized with the image reading for each line may be used. Reference numeral 52 is a temperature sensor arranged in the vicinity of the fluorescent lamp 71, the output of which is connected to the CPU 51.
U51 can know the temperature near the fluorescent lamp 71.

Next, the PWM circuit 50 will be described in detail. A programmable frequency divider 54 divides the output 81 of the oscillator 53 by a frequency division ratio set by the CPU 51 to obtain an output 82. The frequency division ratio can be set from 2 to 2048 in increments of one. Reference numeral 62 is a 13-bit up / down counter, which increases the counter value by 1 in synchronization with the clock input 82 when the level of the signal 90 is "1". Conversely, when the level of the signal 90 is "0", the counter value is decremented by 1 in synchronization with the clock input 82. 5
5, 56, 57 and 58 are registers that can be set by the CPU 51. 55 is a 13-bit register for setting the initial value of the up / down counter 62. The output 83 is connected to the data input terminal D of the up / down counter 62. The Q1 output 87 of the register 58 is connected to the load terminal of the up / down counter 62, and when this signal is "0", the set value of the register 55 is loaded into the up / down counter 62. Reference numeral 56 is a 13-bit register that sets the upper limit value of the up / down counter 62. Its output is connected to the B input of the comparator 59 and the other A input is the output 91 of the up / down counter 62. The comparator 59 outputs "1" when the A input is smaller than the B input. 57 is a 13-bit register for setting the lower limit value of the up / down counter 62. Its output 85 is connected to the B input of the comparator 60 and the other A input is the output 91 of the up / down counter 62. The comparator 60 outputs "1" when the A input is larger than the B input. The Q0 output of the register 58 is input to the AND circuit 61. The outputs of the comparators 59 and 60 are also input to the AND circuit 61, and when all the inputs are "1", the AND circuit 61 outputs "1". The output 89 of the AND circuit 61 is the enable terminal E of the up / down counter 62.
Connected to. The up / down counter 62 performs the above counting operation only when the enable terminal E is "1".

The output of the oscillator 67 is the D flip-flop 7
4 to produce an output 98 synchronized with the oscillator 53. The output 91 of the up / down counter 62 is connected to the 13-bit register 63, and the register 63 latches the data in synchronization with the signal 98. The output 92 is connected to the B input of the comparator 64 and the buffer 73. The output of the buffer 73 is connected to the address / data bus 80, and the CPU 51 can read the data in the register 73 as appropriate. 66 is an addition counter,
The output of the oscillator 53 is counted up. Also signal 98
Cleared in sync with. The output 93 of the counter 66 is connected to the A input of the comparator 64. Comparator 6
4 makes its output 95 "1" when the A input and the B input become equal. Reference numeral 65 is an RS flip-flop, whose output 96 becomes "1" in synchronization with the signal 98, and when the output of the output 95 of the comparator 64 becomes "1", its output 96 becomes "0".

Next, the operation will be described with reference to the timing charts of FIGS. The signal names in FIGS. 2 and 3 are represented by the symbols used in FIG.

FIG. 2 is a timing chart for explaining the operation during the lighting of the fluorescent lamp 71. Here, the frequency division ratio of the programmable frequency divider 54 is set to 4, and 82 is an output obtained by dividing the output 81 of the oscillator 53 by 4. When the signal 98 falls at time t1, the RS flip-flop 65 is set, the signal 96 becomes "1", and the fluorescent lamp 71 is turned on. When the signal 98 rises at time t2, the counter 66 is cleared and its output 93 becomes "0". Further, the register 63 latches the data of the signal 91 (here, 100H) and outputs the value to the signal 92. The signal 93 is thereafter synchronized with the signal 81, 1, 2,
It is counted up as 3. At time t3, the up / down counter 62 is subtracted when the signal 90 is "0" (the light amount of the fluorescent lamp 61 is higher than the target value), and the signal 91 becomes 0FFH. Similarly, the signals 91 are 0FEH and 0FDH after being subtracted at times t4 and t5. Time t5 '
When the signal 90 becomes "1" at (the light amount of the fluorescent lamp 71 is lower than the target value), the up / down counter 62 is added at the time t6 when the next signal 82 rises and the signal 91
Becomes 0FEH. After this, the signal 91 is synchronized with the signal 82.
Will be added. When the signal 93 becomes 100H at time t8, A = B in the comparator 64 and the output 95 is "1".
Then, the RS flip-flop 65 is reset, its output 96 becomes "0", and the fluorescent lamp 71 is turned off.
When the signal 98 falls at time t11, the RS flip-flop 65 is set and the signal 96 is set in the same manner as described above.
Becomes "1" and the fluorescent lamp 71 is turned on. Time t1
When the signal 98 rises at 2, the counter 66 is cleared and its output 93 becomes "0". Also register 63
Latches the data of the signal 91 (here, 112H) and outputs the value to the signal 92. That is, in the next cycle, the time during which the signal 96 is "1" is 112H minutes.

By the operation described above, the time of "1" of the signal 96 is adjusted so that the light quantity of the fluorescent lamp 71 becomes a target value, and the light quantity is controlled to a constant light quantity. Further, the changing speed of the up / down counter 62, that is, the changing speed of the signal 96 can be changed by changing the dividing ratio of the programmable frequency divider 54. Therefore, the loop gain of dimming control can be changed.

Next, the lower limit operation will be described with reference to the timing chart of FIG. 10H is set in the register 57 as the lower limit value from the CPU 51, and the data 85 is 10H. When the up / down counter 62 is decremented to 10H while the signal 90 is "0" (t20), the output of the comparator 60 is "0",
The signal 89 also becomes "0". Therefore, at time t21, the up / down counter 62 is not decremented and the signal 91 becomes 10
It remains H. Therefore, the up / down counter 62 is 1
It does not become 0H or less, and the time of "1" of the signal 96, that is, the lighting time of the fluorescent lamp 71 does not become 10H or less. Further, the CPU 51 can know that the limiter is operating by reading the value of the register 92 and determining that it is 10H (lower limit value).

Since the upper limit operation is almost the same, the description is omitted.

Next, referring to the flow chart of FIG. 4, the CPU 5
The operation of No. 1 will be described.

First, in step 101, 1F50H is set in the register 56 for setting the upper limit. Here, the oscillator 6
The period of 7 is 1 msec. The value of this 1F50H is 1
It is a value slightly larger than msec. Therefore, the signal 96 is output up to a duty ratio of 100%. Next step 10
320H is set in the register 57 for setting the lower limit in 2. This value is equivalent to 0.1 msec, so that the lower limit of the duty ratio of the signal 96 is 10%. This value may be a lower limit value with which the fluorescent lamp 71 is stably turned on. Next, at step 103, the frequency division ratio of the programmable frequency divider 54 is set to 20, which is a relatively low value. Next, in step 104, 1F50H is set in the register 55 for setting the initial value.
Set. This value is the same as the upper limit value, and the fluorescent lamp 71 is initially turned on with a duty ratio of 100%. Next, in steps 105 and 106, the Q1 output 87 of the register 58 is changed from "0" to "1" and the register 55 is changed.
Is loaded into the up / down counter 62. Next, in step 107, Q0 of the register 58 is set to "1" to permit the operation of the up / down counter 62. Next, at step 108, Q2 of the register 58 is set to "1" to permit the operation of the RS flip-flop. Fluorescent lamp 71 from here
Starts to light up. Next, in step 109, the timer in the CPU 51 is set to 0.1 second, and in step 110 it is determined whether or not the timer has expired. Step 110 is executed until the timer expires, and then, in step 111, the frequency division ratio of the programmable frequency divider 54 is set to a relatively large value of 200, and the loop gain of the dimming control is lowered. Next, at step 112, it is judged if the register 63 is at 320H or not, that is, if it becomes the lower limit value and the control is impossible. Yes
Then, in step 113, appropriate error processing is performed and the process ends. If NO in step 112, step 112 is repeated.

As described above, in the present embodiment, when the fluorescent lamp is turned on, the loop gain of the dimming control is increased to improve the responsiveness, and after a predetermined time, the control of the fluorescent lamp becomes close to the target value. The loop gain of can be reduced to improve stability.

(Second Embodiment) Next, a second embodiment will be described. In the present embodiment, the block diagram of the dimming control unit of the document illumination lamp is the same as that of the first embodiment, but the operation of the CPU 51 is different. The operation of the CPU 51 will be described with reference to the flowchart of FIG.

In the figure, step 101 to step 10
8 and steps 111, 112, and 113 are the same as those in the first embodiment, and a description thereof will be omitted. At step 120, it is judged if the voltage of the signal 97 is larger than a predetermined value, that is, if the light quantity of the fluorescent lamp 71 is larger than a predetermined value. This predetermined value is set to about 90% of the target value.
If NO, repeat step 120 and if YES, proceed to step 111 to reduce the loop gain of dimming control.

As described above, in this embodiment, the loop gain of the dimming control is increased at the initial stage of lighting of the fluorescent lamp to improve the responsiveness, and the light quantity of the fluorescent lamp 71 is monitored, and it is close to the target value. In this case, the loop gain can be reduced to improve the stability. Since the amount of light of the fluorescent lamp is observed, optimum control can be performed without being affected by changes in ambient temperature and characteristics of the fluorescent lamp.

(Third Embodiment) Next, a third embodiment will be described. In this embodiment, the block diagram of the dimming control unit of the document illumination lamp is the same as that of the first embodiment, but the operation of the CPU 51 is different.
The operation of the CPU 51 will be described with reference to the flowchart of FIG.

In the figure, step 101 to step 10
8 and steps 111, 112, and 113 are the same as those in the first embodiment, and a description thereof will be omitted. In step 130, it is determined whether or not the register 63 is smaller than 1F40H. This means whether or not the light quantity of the fluorescent lamp 71 once reaches the target value. If NO in step 130, repeat step 130 and if YES, step 111.
Go to and decrease the loop gain.

As described above, in this embodiment, the loop gain of the dimming control is increased to improve the responsiveness in the initial stage of lighting of the fluorescent lamp, and the loop gain is decreased when the light quantity of the fluorescent lamp once exceeds the target value. And stability can be improved.

(Fourth Embodiment) Next, a fourth embodiment will be described. In this embodiment, the block diagram of the dimming control unit of the document illumination lamp is the same as that of the first embodiment, but the operation of the CPU 51 is different.
The operation of the CPU 51 will be described with reference to the flowchart of FIG.

In the figure, step 101 to step 10
8 and steps 130, 111, 112, and 113 are the same as those in the third embodiment, and a description thereof will be omitted. Step 140
Then, it is determined whether or not the temperature detected by the temperature sensor 52 is 40 ° C. or higher. If YES, the process proceeds to step 141, and since the characteristic of the fluorescent lamp 71 is stable, 500 is set to the frequency division ratio of the programmable frequency divider 54 to further reduce the loop gain of the dimming control, and the process returns to step 112. On the other hand, if NO in step 140, the process returns to step 112.

As described above, in this embodiment, when the temperature in the vicinity of the fluorescent lamp 71 rises and the characteristics become stable, the loop gain of the dimming control can be further reduced to improve the stability. This makes it possible to obtain good results especially when inputting a delicate image such as halftone.

(Modification) In each of the embodiments described above, the reference voltage 69 for determining the target value has a fixed value.
You may make it variable from U51. Further, although the lower limit limiter is set to a fixed value, it may be changed depending on the temperature.

In each embodiment, it is assumed that the original is illuminated by the lamp and the image is input by the reflected light, but the present invention is not limited to this, and the photographic film or the like is illuminated by the lamp. It is also possible to carry out an image input by the transmitted light.

[0037]

As described above, according to the present invention, the device
The loop gain for light intensity control can be changed according to the lighting condition.
As a result, both the stability of the control of the light amount of the light source for irradiating the original and the like and the quick rise of the light amount can both be achieved, and the first copy time can be shortened and high image quality can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a first embodiment.

FIG. 2 is a timing chart showing the operation of the first embodiment.

FIG. 3 is a timing chart showing a lower limit operation.

FIG. 4 is a flowchart showing the operation of the CPU 51 in the first embodiment.

FIG. 5 is a flowchart showing the operation of the CPU 51 in the second embodiment.

FIG. 6 is a flowchart showing the operation of the CPU 51 in the third embodiment.

FIG. 7 is a flowchart showing the operation of the CPU 51 in the fourth embodiment.

[Explanation of symbols]

50 PWM circuit 51 CPU 52 Temperature sensor 62 up-down counter 68 Comparator 71 fluorescent lamp 72 Light intensity sensor

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Satoru Sugano 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Hidehiko Kinoshita 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. Co., Ltd. (72) Inventor Nomasasa Iseki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Tetsuya Morita 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (56) References JP-A-60-10872 (JP, A) JP-A-3-85012 (JP, A) JP-A-4-282629 (JP, A) JP-A-61-151639 (JP, A) ( 58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 1/04-1/207

Claims (5)

(57) [Claims] 1. A light source for irradiating an original or the like, a light amount detecting means for detecting the light amount of the light source, a comparing means for comparing the output of the light amount detecting means with a reference value, and a variable frequency dividing for variably dividing a clock. Means and a counter that synchronizes with the clock divided by the variable dividing means according to the outputs of the comparing means and the comparing means.
Counting means for increasing or decreasing the counter value by 1, power supplying means for supplying power to the light source according to the count value of the counting means, state detecting means for detecting the state of the device, and this state detecting means. The image input device comprising: a control unit that changes the frequency division ratio of the variable frequency division unit according to the output of Wherein said state detecting means is for detecting the time from the start of lighting of the light source, said control means said Allowed
The frequency division ratio of the variable frequency dividing means is set low at the beginning of lighting the light source.
The image input device according to claim 1, wherein the image input device is increased after a fixed time . Wherein said state detecting means is for detecting the light quantity of the light source, the control means min of the variable frequency division means
If the light intensity of the light source is small, set the period ratio to a low value to obtain the target light intensity.
2. The value is increased when it comes close to
The image input device described. 4. The state detecting device detects a temperature in the vicinity of a light source, and the control means is the variable frequency dividing means.
If the temperature near the light source is low, the division ratio of
The image input device according to claim 1, wherein the temperature is raised when the temperature of the source characteristic becomes stable . 5. The light source is a fluorescent lamp, and the power
By changing the lighting time of the fluorescent lamp by the supply means
The image input device according to any one of claims 1 to 4, wherein the light amount of the fluorescent lamp is adjusted .