JP3402874B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having an alignment mark for aligning a metal layer with a contact layer. . 2. Description of the Related Art Conventionally, an alignment mark is
An alignment mark is formed on a substrate by arranging a plurality of rectangular frames each having a predetermined size, for example, a concave portion having a square of 4 μm, in one direction. This is performed by detecting light and detecting a position in a direction perpendicular to the direction in which the alignment mark extends. [0003] Since alignment is required in two directions (X direction and Y direction) perpendicular to each other, the scribe line is formed on the scribe line so that such alignment marks extend in the direction perpendicular to each other. One set in the direction and the Y direction (as shown in FIG.
a) a plurality of rectangular frame alignment marks 12a are arranged in one direction). The alignment marks 12 are provided for each chip to be aligned at one time. Each recess 12a of the alignment mark 12
Has a width of about 0.8 μm and a depth of 0.1 μm, as shown in FIG.
5 μm to 0.8 μm, 4 μm in height and width in the area surrounded by the recess
m, and the arrangement pitch is 8 μm. Each region surrounded by the rectangular frame-shaped recess has a region necessary for mask alignment. The shape of the alignment mark 12 is disclosed in JP-A-1-272117. In the formation of the contact hole 14, the alignment mark 12 for aligning the metal layer with the contact layer in a later step is formed.
Through the following steps, the contact hole 14 is formed at the same time. First, an interlayer insulating film 15 is formed on a semiconductor substrate 11.
(For example, an NSG film or a BPSG film by a CVD method) is deposited in a thickness of 0.5 to 0.8 μm. Next, dry etching (for example, using a gas of C ₂ F ₆ or the like and a pressure of several mTorr)
And ) To form the contact holes 14 and the alignment marks 12. In a process using the step of burying the inside of the contact hole 14 with a buried plug material 13 (for example, tungsten), the diameter of the contact hole 14 is about 0.4 μm and the depth is 0.5 which is the same as the thickness of the interlayer insulating film 15. ~ 0.8
As compared with μm, the alignment mark 12 has a width of about 0.8 μm and a depth of 0.5 to 0.8 μm, which is equivalent to that of the contact hole 14 as described above (FIG. 8A). Further, an embedded plug material 13 for embedding the contact hole 14 is deposited to a thickness of, for example, 0.5 μm for a contact diameter of about 0.4 μm (FIG. 8).
(B)), to buried plug material 13, for example, when using tungsten, gas SF _6, Ar, the He, etc., the pressure to form a contact carried down, the dry etching conditions 200～300MTorr. At this time, if the amount of deposition increases, the dry etching of the buried plug material 13 causes the plug material to be left unetched at the step. When over-etching is performed until the etching residue is removed, the buried plug material 13 inside the contact hole 14 is etched. During the dry etching of the buried plug material 13, the buried plug material 13 inside the contact hole 14 is hardly etched. On the other hand, in the above-described alignment mark 12, the embedded plug material 13 inside the alignment mark 12 is etched, and a sidewall 18 of the embedded plug material 13 is formed on the inner wall of the alignment mark 12.
(C)). The sidewalls 18 formed in the above steps are easily peeled off in a later cleaning step or during sputtering of the wiring metal, and there is a problem of dust generation due to the peeling. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having an alignment mark for preventing generation of dust due to peeling of a sidewall of an embedded plug material formed inside an alignment mark. According to a first aspect of the present invention, there is provided a semiconductor device according to the first aspect of the present invention, wherein the semiconductor device has a scribe region and a semiconductor element formation region. In a semiconductor device having an alignment mark embedded with the same plug material as that of a contact hole formed in a semiconductor element formation region, the minimum width of the concave portion of the alignment mark may be smaller than that of the contact hole formed in the semiconductor element formation region. Below the same value as the diameter,
In addition, the alignment mark is equal to or greater than a value that can be sensed. According to the above configuration, an alignment mark which can prevent generation of dust due to peeling of the sidewall of the buried plug material formed on the inner wall of the alignment mark is formed. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments of the present invention. In the following description, tungsten is used as the buried plug material, but the present invention is not limited to this. FIG. 1 is a plan view of a rectangular alignment mark included in a semiconductor device according to an embodiment of the present invention, FIG. 2 is a partially enlarged view of the alignment mark shown in FIG. 1, and FIG. FIG. 4 is a plan view of a row of alignment marks included in the semiconductor device according to the embodiment of the present invention, and FIG. 5 is a part of the alignment mark shown in FIG. It is an enlarged view. 1 to 5, 1 is a semiconductor substrate, 2 is an alignment mark, 2a is a recess of an alignment mark, 3 is a buried plug material, 4 is a contact hole, 5 is an interlayer insulating film, and 6 is a gate electrode. , 7 are source / drain regions. Next, an embodiment of the present invention will be described with reference to FIG. First, an NSG film having a thickness of about 0.8 μm is formed on the semiconductor substrate 1 on which the gate electrode 6 and the source / drain region 7 of the transistor are formed in the semiconductor element formation region, for example, by the CVD method. A BPSG film is formed as the interlayer insulating film 5. Thereafter, dry etching (for example, gas is C ₂ F ₆ or the like and pressure is several mTorr) is performed to form the contact holes 4 and the alignment marks 2 (FIG. 3A). This alignment mark 2 has a rectangular window pattern as shown in FIGS.
A plurality of parallel linear patterns as shown in FIG. 5 are arranged in one direction. Each of the recesses 2a has the same width as the contact hole 4 in the element region, and the length and width of the portion surrounded by the recess 2a are 4 μm and the wiring pitch is 8 μm (FIG. 2). In the present invention, if the width of the concave portion 2a is equal to or smaller than the same width as the contact hole 4 and is equal to or larger than a value at which the alignment mark can be sensed, the effects of the present invention are exhibited. Since the alignment mark 2 is formed at the same time as the dry etching for forming the contact hole 4, the depth is formed to be equal to the depth of the contact hole.
Such an alignment mark 2 is perpendicular to the moving direction of the belt-shaped spot of the laser beam applied to the alignment mark, and in the X direction and the Y direction of the scribe line for each semiconductor chip unit aligned at a time. One set is provided (FIGS. 1 and 4). Next, the concave portion 2a of the alignment mark is buried with the buried plug material 3 (for example, tungsten) in the contact hole 4 (FIG. 3B. In the process using the buried plug forming step, the diameter of the contact is 0.4 μm).
0.5 to 0.8 of the same degree and depth as the thickness of the interlayer insulating film 5
As described above, the alignment mark 2 has a width of about 0.4 μm and a depth of about 0.1 μm,
5 to 0.8 μm. Further, an embedded plug material 3 for embedding the contact hole 4 is deposited to a thickness of 0.5 μm (FIG. 3).
(B)) When, for example, tungsten is used as the buried plug material 3, the contact is formed by dry etching using a gas of SF ₆ , Ar, He or the like at a pressure of 200 to 300 mTorr. Thus, by forming the minimum width of the concave portion 2a of the alignment mark to be equal to or less than the diameter of the contact hole 4, the embedded plug material 3 inside the concave portion 2a of the alignment mark becomes similar to the embedded plug material 3 inside the contact hole 4. Without being etched, the concave portion 2 a of the alignment mark is completely buried with the buried plug material 3. As described in detail above, the concave portion formed in the interlayer insulating film of the scribe region on the semiconductor substrate having the scribe region and the semiconductor element formation region,
A semiconductor device having an alignment mark embedded with the same material as a plug material embedded in a contact hole formed in the semiconductor element formation region, wherein a minimum width of a concave portion of the alignment mark is smaller than that of a contact formed in the semiconductor element formation region. By using the present invention in which the diameter of the hole is equal to or smaller than the diameter and the alignment mark is equal to or larger than the perceived value, the side wall of the buried plug material generated at the time of dry etching of the buried plug material as compared with the conventional method is reduced. A semiconductor device having an alignment mark capable of preventing generation of dust due to peeling can be manufactured.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a rectangular alignment mark included in a semiconductor device according to an embodiment of the present invention. FIG. 2 is a partially enlarged view of the alignment mark shown in FIG. FIG. 3 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention; FIG. 4 is a plan view of a plurality of linear alignment marks included in the semiconductor device according to the embodiment of the present invention. 5 is a partially enlarged view of the alignment mark shown in FIG. FIG. 6 is a plan view of an alignment mark included in a conventional semiconductor device. FIG. 7 is a partially enlarged view of the alignment mark shown in FIG. 6; FIG. 8 is a manufacturing process diagram of a conventional semiconductor device. [Description of Reference Numerals] 1 semiconductor substrate 2 alignment mark 2a recess of alignment mark 3 buried plug material 4 contact hole 5 interlayer insulating film 6 gate electrode 7 source / drain region

Claims (1)

(57) [Claim 1] A semiconductor substrate having a scribe region and a semiconductor element formation region is formed in a recess formed in an interlayer insulating film of a scribe region in the semiconductor element formation region. A semiconductor device having an alignment mark in which the same material as the plug material of the contact hole is embedded, wherein the minimum width of the concave portion of the alignment mark is equal to or smaller than the diameter of the contact hole formed in the semiconductor element formation region. And a semiconductor device characterized in that the alignment mark is equal to or greater than a sensed value.