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JP3404099B2 - Method for manufacturing capacitor - Google Patents
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JP3404099B2 - Method for manufacturing capacitor - Google Patents

Method for manufacturing capacitor

Info

Publication number
JP3404099B2
JP3404099B2 JP31626493A JP31626493A JP3404099B2 JP 3404099 B2 JP3404099 B2 JP 3404099B2 JP 31626493 A JP31626493 A JP 31626493A JP 31626493 A JP31626493 A JP 31626493A JP 3404099 B2 JP3404099 B2 JP 3404099B2
Authority
JP
Japan
Prior art keywords
tantalum oxide
heat treatment
capacitor
oxygen
oxide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP31626493A
Other languages
Japanese (ja)
Other versions
JPH07169917A (en
Inventor
美鈴 平山
昌之 中田
晋平 飯島
夏樹 横山
譲 大路
輝明 木須
裕一 松井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Priority to JP31626493A priority Critical patent/JP3404099B2/en
Publication of JPH07169917A publication Critical patent/JPH07169917A/en
Application granted granted Critical
Publication of JP3404099B2 publication Critical patent/JP3404099B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)
  • Recrystallisation Techniques (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はキャパシタの製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor.

【0002】[0002]

【従来の技術】LSIの高集積化にはメモリセル面積の
縮小が必須であるが、例えば、ダイナミックRAMのキ
ャパシタに関しては、読み出し信号のS/N,ソフトエ
ラーなどの問題から単位面積あたりの蓄積電荷量をセル
面積に比例して縮小することはできない。そこで、キャ
パシタ絶縁膜の薄膜化,高誘電率化およびキャパシタ構
造の立体化による大容量化が検討されているが、従来キ
ャパシタ絶縁膜として用いられてきた熱酸化膜(誘電率
ε=3.9)あるいは窒化膜(ε=7)の薄膜化は信頼
性,制御性の面から既に限界に達しており、更に、高集
積化を行うにはより高い誘電率を持つ材料を用いる必要
がある。
2. Description of the Related Art A reduction in memory cell area is indispensable for high integration of LSIs. For example, in the case of a dynamic RAM capacitor, storage per unit area is caused by problems such as S / N of read signal and soft error. The amount of charge cannot be reduced in proportion to the cell area. Therefore, thinning of the capacitor insulating film, increasing the dielectric constant, and increasing the capacity by increasing the three-dimensional structure of the capacitor are being studied. However, the thermal oxide film (dielectric constant ε = 3.9) that has been used as a conventional capacitor insulating film has been studied. ) Or the thinning of the nitride film (ε = 7) has already reached the limit in terms of reliability and controllability, and it is necessary to use a material having a higher dielectric constant for higher integration.

【0003】このような材料として最も注目されている
のが誘電率,絶縁耐圧ともに高く、コンデンサとして実
績のある酸化タンタル(Ta25,ε=22)であり、キ
ャパシタの構造は、特開昭61−36963号公報にW/Ta2
5/Si(Metal-Insulator-Semiconductor=MI
S),特開昭62−84544 号公報にW/Ta25/Si3
4/Si(Metal-Insulator-Nitride-Semiconductor=
MINS),特開昭60−152049号公報にW/Ta25
W(Metal-Insulator-Metal=MIM)が記載されてい
る。
The most noticeable material for such a material is tantalum oxide (Ta 2 O 5 , ε = 22), which has a high permittivity and a high withstand voltage and has a proven track record as a capacitor. W / Ta 2 in Sho 61-36963
O 5 / Si (Metal-Insulator-Semiconductor = MI
S), Japanese Patent Application Laid-Open No. 62-84544, W / Ta 2 O 5 / Si 3
N 4 / Si (Metal-Insulator-Nitride-Semiconductor =
MINS), JP 60-152049 A, W / Ta 2 O 5 /
W (Metal-Insulator-Metal = MIM) is described.

【0004】しかし、いずれの場合も酸化タンタル膜を
形成後そのまま上部電極を形成してキャパシタとすると
リーク電流が大きく、デバイスには適用できない。この
リーク電流の原因は酸化タンタル膜を有機金属原料を用
いた化学気相成長法により形成した場合は原料から、ま
たスパッタリング法により形成した場合は排気系からそ
れぞれ膜中に炭素が混入すること、酸化タンタル膜中に
酸素欠陥が存在すること等が考えられている。これに対
して形成した酸化タンタル膜を酸素雰囲気中で、あるい
は水銀ランプ照射したオゾン中でアニールした後乾燥酸
素雰囲気中でアニールすることによって耐圧を向上させ
る方法が既に知られており、特に700℃以上の高温に
おける乾燥酸素雰囲気中のアニールにより酸化タンタル
キャパシタの耐圧は著しく向上することが特開昭61−36
963号公報に記載されている。
However, in any case, if the tantalum oxide film is formed and then the upper electrode is formed as it is to form a capacitor, a large leak current will not be applied to the device. The cause of this leakage current is that carbon is mixed into the film from the raw material when the tantalum oxide film is formed by the chemical vapor deposition method using an organic metal raw material, and from the exhaust system when the film is formed by the sputtering method, It is considered that oxygen defects are present in the tantalum oxide film. On the other hand, there is already known a method of improving the breakdown voltage by annealing the formed tantalum oxide film in an oxygen atmosphere or in ozone irradiated with a mercury lamp and then in a dry oxygen atmosphere. It is noted that the withstand voltage of the tantalum oxide capacitor is remarkably improved by annealing in a dry oxygen atmosphere at the above high temperature.
It is described in Japanese Patent No. 963.

【0005】[0005]

【発明が解決しようとする課題】上記のような活性酸素
雰囲気あるいは高温酸素雰囲気中のアニールにより酸化
タンタルキャパシタの耐圧は大きく向上するが、MIS
型キャパシタの場合にはTa25/Si界面に生成する
二酸化シリコン層の成長を促し、MINS形,MIM形
キャパシタにおいては、それぞれ、酸窒化膜,下部電極
が酸化されて蓄積電荷量の低下を引き起こす。
The withstand voltage of the tantalum oxide capacitor is greatly improved by annealing in the active oxygen atmosphere or the high temperature oxygen atmosphere as described above.
-Type capacitors promote the growth of the silicon dioxide layer generated at the Ta 2 O 5 / Si interface, and in MINS-type and MIM-type capacitors, the oxynitride film and the lower electrode are oxidized to reduce the accumulated charge amount. cause.

【0006】図1はMISキャパシタに関し酸素アニー
ル温度に対してリーク電流が、10-8A/cm2 に達する印
加電圧で定義した耐圧とキャパシタの容量を示したもの
である。アニール温度が高くなるにつれて耐圧は向上す
るが、容量は低下していく。従って容量の大きいキャパ
シタを得るためには界面酸化膜,界面窒化膜あるいは下
部電極を酸化することなく、酸化タンタル膜中に混入す
る炭素を取り除き、酸素欠陥を補うアニール方法が必要
である。
FIG. 1 shows the withstand voltage and the capacitance of the MIS capacitor, which are defined by the applied voltage at which the leakage current reaches 10 -8 A / cm 2 with respect to the oxygen annealing temperature. The breakdown voltage improves as the annealing temperature increases, but the capacity decreases. Therefore, in order to obtain a capacitor having a large capacitance, it is necessary to remove the carbon mixed in the tantalum oxide film without oxidizing the interfacial oxide film, the interfacial nitride film or the lower electrode, and perform an annealing method for compensating for oxygen defects.

【0007】[0007]

【課題を解決するための手段】上記の問題点は形成した
酸化タンタル膜を初め酸素あるいは二窒化酸素を0.1%
以上含む雰囲気中で、600℃以上750℃以下の温度
でアニールして膜中に混入した炭素を取り除き、次いで
非酸化性雰囲気中700℃以上1000℃以下の範囲に
て第一の熱処理より高温でアニールして膜を結晶化する
ことにより達成できる。
[Problems to be Solved by the Invention] The above problems are caused by the formed tantalum oxide film containing 0.1% of oxygen or oxygen dinitride.
Annealing is performed at a temperature of 600 ° C. or more and 750 ° C. or less in the atmosphere containing the above to remove carbon mixed in the film, and then at a temperature higher than that of the first heat treatment in the range of 700 ° C. or more and 1000 ° C. or less in a non-oxidizing atmosphere. This can be achieved by annealing and crystallizing the film.

【0008】[0008]

【作用】発明者らの検討によれば、酸化タンタル膜中に
混入した炭素は酸素雰囲気中では200℃から600℃
の間で脱離する。
According to the studies made by the inventors, the carbon mixed in the tantalum oxide film is 200 ° C. to 600 ° C. in the oxygen atmosphere.
Desorb between.

【0009】図2は酸素アニール温度に対してX線回折
ピークの積分値の和を取ったもので、結晶化の程度を示
している。この図から分かるように酸化タンタル層は7
00℃付近で結晶化し始め、酸素アニール温度が高くな
るほど結晶化は進む。また、アルゴン雰囲気中850℃
でアニールを行った場合にも800℃の酸素アニールと
同程度の結晶化が確認できた。しかし,アルゴンアニー
ルのみ行った酸化タンタルキャパシタの耐圧は低く、結
晶化が耐圧向上の直接の原因ではないことが明らかとな
った。
FIG. 2 shows the sum of integrated values of X-ray diffraction peaks with respect to the oxygen annealing temperature, and shows the degree of crystallization. As can be seen from this figure, the tantalum oxide layer is 7
Crystallization starts at around 00 ° C., and crystallization progresses as the oxygen annealing temperature increases. Also, in an argon atmosphere at 850 ° C
Even when the annealing was performed at 1, the crystallization was confirmed to be about the same as the oxygen annealing at 800 ° C. However, the withstand voltage of the tantalum oxide capacitor only subjected to argon annealing was low, and it was clarified that crystallization was not the direct cause of the withstand voltage improvement.

【0010】図3に弾性反跳粒子検出法により測定した
各種アニールを行った酸化タンタル層に含まれる不純物
炭素の量を示した。酸素アニール温度が高いほど膜中に
混入した炭素量は減少しており、膜中に混入した炭素が
酸化タンタルキャパシタのリーク電流の大きな原因の一
つであることが確認できた。また、酸素アニール後に高
温のアルゴンアニールを行うと膜中の炭素量が減少し、
結晶化により膜中の不純物炭素の脱離が助長されて耐圧
が向上することを確認した。
FIG. 3 shows the amount of impurity carbon contained in the tantalum oxide layer subjected to various annealings, which was measured by the elastic recoil particle detection method. The higher the oxygen annealing temperature, the smaller the amount of carbon mixed in the film, and it was confirmed that carbon mixed in the film was one of the major causes of the leakage current of the tantalum oxide capacitor. Also, when high-temperature argon annealing is performed after oxygen annealing, the amount of carbon in the film decreases,
It was confirmed that crystallization promotes desorption of impurity carbon in the film and improves the breakdown voltage.

【0011】従って、まず酸素もしくは二窒化酸素を
0.1% 以上含む雰囲気中で、膜中の炭素を取り除くこ
とができ、かつ界面酸化膜,窒化膜あるいは下部電極を
酸化することのない温度、すなわち600℃以上750
℃以下の温度でアニールを行い、次いで、不活性ガス雰
囲気中あるいは酸素濃度が0.1% 以下になるように不
活性ガスで希釈した酸素あるいは二窒化酸素雰囲気中
で、第一の熱処理よりも高温、且つ、酸化タンタル膜を
結晶化する温度、すなわち700℃以上の温度でアニー
ル(以後結晶化アニールと呼ぶ)を行えば、界面の酸化
膜を成長させることなく、また界面に形成した窒化膜あ
るいは下部電極金属層を酸化することなく酸化タンタル
膜中に混入する炭素を取り除き、結晶化して、大容量で
耐圧良好なキャパシタ絶縁膜を得ることができる。
Therefore, first, in an atmosphere containing oxygen or oxygen dinitride in an amount of 0.1% or more, a temperature at which carbon in the film can be removed and which does not oxidize the interfacial oxide film, the nitride film or the lower electrode, That is 600 ° C or higher 750
Annealing is performed at a temperature of ℃ or less, then in an inert gas atmosphere or in an oxygen or dinitride oxygen atmosphere diluted with an inert gas so that the oxygen concentration is 0.1% or less, than in the first heat treatment. If annealing is performed at a high temperature and at a temperature for crystallizing the tantalum oxide film, that is, at a temperature of 700 ° C. or higher (hereinafter referred to as crystallization annealing), a nitride film formed on the interface without growing an oxide film on the interface Alternatively, without mixing the lower electrode metal layer, carbon mixed in the tantalum oxide film can be removed and crystallized to obtain a capacitor insulating film having a large capacity and a good withstand voltage.

【0012】[0012]

【実施例】(実施例1)図4は本発明の概念を用いて形
成したキャパシタの形成プロセスの断面図である。
(Embodiment 1) FIG. 4 is a sectional view of a process of forming a capacitor formed using the concept of the present invention.

【0013】図4(a)に示すように、シリコン基板1
上に熱酸化膜2を形成し、その一領域の絶縁膜を除去し
た。次に絶縁膜を除去した部分に多結晶シリコン膜を形
成,加工しキャパシタの下部電極3を形成した。図4
(b)に示すように、この多結晶シリコン膜3を酸化タ
ンタル膜形成直前にフッ酸洗浄後水洗を行うと表面に1
nm以下の自然酸化膜4が生成した。ついで図4(c)
に示すように自然酸化膜上にペンタエトキシタンタル
(Ta(OC25)5)を原料とし窒素をキャリアガスとし
て用い、酸素雰囲気中で420℃で化学気相成長法によ
り、酸化タンタル膜5を10nm堆積させた。形成した
酸化タンタル膜は、初めに抵抗加熱炉を用い乾燥酸素雰
囲気中700℃で30分間アニールを行った後、続いて
アルゴン雰囲気中850℃で10分間結晶化アニールを
行った。図4(d)は酸化タンタル5上に窒化チタン電
極6を形成した状態を示している。
As shown in FIG. 4A, the silicon substrate 1
A thermal oxide film 2 was formed on top and the insulating film in that region was removed. Next, a polycrystalline silicon film was formed and processed in the portion where the insulating film was removed to form the lower electrode 3 of the capacitor. Figure 4
As shown in (b), when the polycrystalline silicon film 3 is washed with hydrofluoric acid and then washed with water immediately before the formation of the tantalum oxide film, the surface of the polycrystalline silicon film 3 becomes 1
A native oxide film 4 having a thickness of nm or less was formed. Then, Fig. 4 (c)
Pentaethoxy tantalum on the native oxide film as shown in
Using (Ta (OC 2 O 5 ) 5 ) as a raw material and nitrogen as a carrier gas, a tantalum oxide film 5 was deposited to 10 nm by a chemical vapor deposition method at 420 ° C. in an oxygen atmosphere. The formed tantalum oxide film was first annealed at 700 ° C. for 30 minutes in a dry oxygen atmosphere using a resistance heating furnace, and subsequently, crystallized annealing was performed at 850 ° C. for 10 minutes in an argon atmosphere. FIG. 4D shows a state in which the titanium nitride electrode 6 is formed on the tantalum oxide 5.

【0014】図5の曲線(g)はこの方法で形成したキ
ャパシタの電流−電圧特性を示している。また、同図の
曲線(e)は熱処理を行わないキャパシタ、(f)は7
00℃の酸素アニールのみを行ったキャパシタの耐圧を
示している。比較として乾燥酸素雰囲気における800
℃,30分のアニールのみを行ってタングステン電極を
形成したキャパシタの耐圧を(h)に示した。二酸化シ
リコンの比誘電率を用いて換算した換算膜厚は(e)
3.1nm(f)3.7nm(g)3.7nm(h)4.2
nm であり、二段階のアニールを行うことにより界面
酸化膜の成長を抑制しながら耐圧が向上した。
The curve (g) in FIG. 5 shows the current-voltage characteristic of the capacitor formed by this method. Further, the curve (e) in the figure is a capacitor not subjected to heat treatment, and the curve (e) is 7
It shows the breakdown voltage of the capacitor which was only oxygen-annealed at 00 ° C. 800 for comparison in a dry oxygen atmosphere
The withstand voltage of a capacitor having a tungsten electrode formed only by annealing at 30 ° C. for 30 minutes is shown in (h). The converted film thickness converted using the relative permittivity of silicon dioxide is (e)
3.1 nm (f) 3.7 nm (g) 3.7 nm (h) 4.2
and the withstand voltage was improved while suppressing the growth of the interfacial oxide film by performing the two-step annealing.

【0015】なお、第一の熱処理は成膜温度600℃以
上750℃以下で10分から3時間アニールを行った場
合にも同様の効果を得ることができ、二窒化酸素雰囲
気、あるいは酸素又は二窒化酸素を窒素又はアルゴンで
0.1% 以上に希釈した雰囲気中でアニールを行っても
同様の効果が得られる。続く第二の熱処理に関しては窒
素又はアルゴン雰囲気中あるいは0.1% 未満の濃度の
酸素あるいは二窒化酸素を含む窒素又はアルゴン雰囲気
中700℃以上1000℃以下で10分以上30分以下
のアニールを行った場合にも同様の効果が得られた。
[0015] Incidentally, the first heat treatment can also obtain the same effect when performing 10 minutes to 3 hours annealing at below 750 ° C. deposition temperature 600 ° C. or higher, oxygen dinitride Kiri囲<br/> gas Alternatively, the same effect can be obtained by annealing in an atmosphere in which oxygen or oxygen dinitride is diluted to 0.1% or more with nitrogen or argon. For the subsequent second heat treatment, annealing is performed at 700 ° C to 1000 ° C for 10 minutes to 30 minutes in a nitrogen or argon atmosphere or in a nitrogen or argon atmosphere containing oxygen or oxygen dinitride at a concentration of less than 0.1%. The same effect was obtained in the case of

【0016】(実施例2)図6は多結晶シリコン膜3を
形成した後抵抗加熱炉を用い、アンモニア雰囲気中にお
いて800℃で5分間処理して表面の酸化シリコン層を
窒化した後酸化タンタル膜5を形成し、窒化チタン電極
6を形成したキャパシタの断面図である。このような構
造のキャパシタに関しても界面の酸窒化膜7が高温の酸
素アニールで酸化することがSSDM,1992,p5
21に報告されており、この界面酸窒化シリコン層の酸
化による容量の低下を抑えるのに実施例1に記載の結晶
化アニールは効果的である。
(Example 2) FIG. 6 shows a tantalum oxide film after nitriding the silicon oxide layer on the surface by forming a polycrystalline silicon film 3 and using a resistance heating furnace to treat the silicon oxide layer at 800 ° C. for 5 minutes in an ammonia atmosphere. 5 is a cross-sectional view of a capacitor in which a titanium nitride electrode 6 is formed after forming No. 5 in FIG. Also in the capacitor having such a structure, the oxynitride film 7 at the interface may be oxidized by high-temperature oxygen annealing in SSDM, 1992, p5.
21 reported that the crystallization annealing described in Example 1 is effective in suppressing the decrease in capacity due to the oxidation of the interfacial silicon oxynitride layer.

【0017】このキャパシタの耐圧を図7に示した。曲
線(i)は熱処理なし、(j)は700℃の酸素アニー
ル、(k)は700℃の酸素アニール後850℃のアル
ゴンアニール、(h)は800℃の酸素アニールを行っ
たキャパシタの耐圧を示しており、換算膜厚はそれぞれ
(i)3.0nm(j)3.5nm(k)3.5nm
(h)4.2nmであった。窒化処理は600℃以上1
000℃以下で5分以上30分以下行った場合にも同様
の効果が得られる。また、例えばSSDM,1992,p
521に記載されているようにランプ加熱等を用いて昇
降温時間を短くすると酸窒化シリコン層を薄膜化できる
ため容量の大きいキャパシタを得ることができるがこの
場合にも実施例1に記載の結晶化アニールは同様の効果
があった。
The breakdown voltage of this capacitor is shown in FIG. The curve (i) shows the breakdown voltage of the capacitor which was not heat-treated, (j) was oxygen-annealed at 700 ° C., (k) was oxygen-annealed at 700 ° C. and then argon-annealed at 850 ° C., and (h) was oxygen-annealed at 800 ° C. The converted film thickness is (i) 3.0 nm (j) 3.5 nm (k) 3.5 nm, respectively.
(H) It was 4.2 nm. Nitriding process is over 600 ℃ 1
The same effect can be obtained when the heating is performed at 000 ° C. or lower for 5 minutes or more and 30 minutes or less. Also, for example, SSDM, 1992, p
As described in No. 521, when the temperature rising / falling time is shortened by using lamp heating or the like, a silicon oxynitride layer can be thinned to obtain a capacitor having a large capacity. In this case as well, the crystal described in Example 1 is used. Chemical annealing had a similar effect.

【0018】(実施例3)図8はシリコン基板1上に下
部電極としてタングステン層8を形成した後、酸化タン
タル層5を形成し、窒化チタン電極6を形成したキャパ
シタの模式的断面図である。この構造のキャパシタは高
温の酸素アニールにより下部電極タングステン層8と酸
化タンタル層5の界面に酸化タングステン層9が成長し
容量の低下を引き起こすためこの場合にも実施例1に記
載の結晶化アニールは同様の効果をもたらした。特に、
下部電極がタングステンの場合に第一の熱処理を水と水
素を含む雰囲気中で行うと下部電極と酸化タンタル層の
界面に存在する酸化タングステン9が還元されるため良
好な特性を持つ大容量のキャパシタが得られた。
(Embodiment 3) FIG. 8 is a schematic sectional view of a capacitor in which a tungsten layer 8 is formed as a lower electrode on a silicon substrate 1, a tantalum oxide layer 5 is then formed, and a titanium nitride electrode 6 is formed. . In the capacitor having this structure, the tungsten oxide layer 9 grows at the interface between the lower electrode tungsten layer 8 and the tantalum oxide layer 5 due to the high temperature oxygen annealing, which causes a decrease in the capacitance. It had a similar effect. In particular,
When the lower electrode is tungsten and the first heat treatment is performed in an atmosphere containing water and hydrogen, the tungsten oxide 9 existing at the interface between the lower electrode and the tantalum oxide layer is reduced, so that a large-capacity capacitor having good characteristics. was gotten.

【0019】また、第一の熱処理を行った後、水と水素
を含む雰囲気中で熱処理を行い第二の熱処理を行って
も、第一,第二の熱処理を行った後に水と水素を含む雰
囲気中で熱処理を行っても同様の効果が得られた。また
下部電極をモリブデン,タングステンあるいはモリブデ
ンの窒化物もしくはケイ化物のうち一種からなる単層膜
もしくはタングステンも含めたうちの二種以上を複数層
積層した積層膜としても何ら問題はない。
Further, even if the second heat treatment is performed after the first heat treatment in an atmosphere containing water and hydrogen, the first heat treatment is performed after the first and second heat treatments. The same effect was obtained even when the heat treatment was performed in the atmosphere. There is no problem even if the lower electrode is a single-layer film made of molybdenum, tungsten, or a nitride or silicide of molybdenum, or a laminated film in which two or more layers including tungsten are laminated.

【0020】(実施例4)実施例1と同様の構造の酸化
タンタルキャパシタにおいて、第一の熱処理と第二の熱
処理を逆の順番で行った場合にも実施例1と同様の効果
が得られた。
(Embodiment 4) In the tantalum oxide capacitor having the same structure as that of Embodiment 1, even when the first heat treatment and the second heat treatment are performed in the reverse order, the same effect as that of the first embodiment can be obtained. It was

【0021】図9のキャパシタはフッ酸洗浄を行ったシ
リコン基板1上に酸化タンタル層5を形成し、その後、
窒化チタン上部電極6を形成後、加工して形成したもの
である。
In the capacitor shown in FIG. 9, a tantalum oxide layer 5 is formed on a silicon substrate 1 which has been washed with hydrofluoric acid, and thereafter,
The titanium nitride upper electrode 6 is formed and then processed.

【0022】図10の各曲線は、図9に示した構造のキ
ャパシタに関して、酸化タンタル層5形成後に(o)6
00℃の酸素アニールに続いて800℃のアルゴンアニ
ールを行ったもの、(n)800℃のアルゴンアニール
を行った後600℃の酸素アニールを行ったもの、比較
として(l)熱処理を行わないもの、(m)800℃の
アルゴンアニールのみを行ったキャパシタの耐圧を示し
ている。
The curves in FIG. 10 show (o) 6 after forming the tantalum oxide layer 5 for the capacitor having the structure shown in FIG.
Oxygen anneal at 00 ° C. followed by argon anneal at 800 ° C., (n) Argon anneal at 800 ° C. and then oxygen anneal at 600 ° C., (l) No heat treatment for comparison , (M) shows the withstand voltage of a capacitor that was only annealed at 800 ° C. with argon.

【0023】第一の熱処理と第二の熱処理を逆の順番で
行った場合にも実施例1に記載したアニール方法の場合
と同程度の容量の低下を抑える効果および耐圧向上の効
果があった。しかし酸素アニールを行った後、結晶化ア
ニールを行った方が耐圧の向上には効果的であった。ま
た、800℃のアルゴンアニールのみでは耐圧不十分で
あった。
Even when the first heat treatment and the second heat treatment were carried out in the reverse order, there was the effect of suppressing the decrease in capacitance and the effect of improving the breakdown voltage to the same extent as in the case of the annealing method described in the first embodiment. . However, it was more effective to improve the breakdown voltage by performing crystallization annealing after performing oxygen annealing. Further, the pressure resistance was insufficient only by argon annealing at 800 ° C.

【0024】(実施例5)酸化タンタル膜形成後第一の
熱処理を行って不純物炭素を除去し、酸素欠陥を修復し
た後、再び酸化タンタル膜を形成して第一の熱処理を行
う行程を一回以上繰返し行い最後に第二の熱処理を行っ
た場合、更に高耐圧のキャパシタを得ることができた。
(Embodiment 5) After the tantalum oxide film is formed, a first heat treatment is performed to remove impurity carbon and repair oxygen defects, and then a tantalum oxide film is formed again to perform the first heat treatment. When the second heat treatment was performed at the end by repeating the above operation more than once, it was possible to obtain a capacitor having a higher withstand voltage.

【0025】図11に10nmの酸化タンタル層を1〜
4回に分けて形成し、その都度700℃の酸素アニールを
行い、最後に850℃のアルゴンアニールを行って形成
したキャパシタの耐圧を示した。膜形成を細かく分けて
行うほど不純物炭素や酸素欠陥の少ない酸化タンタル層
が得られ耐圧が向上した。
In FIG. 11, 1 to 10 nm tantalum oxide layers are formed.
The breakdown voltage of the formed capacitor was shown by performing oxygen anneal at 700 ° C. each time, and performing argon anneal at 850 ° C. finally. The finer the film formation, the more the tantalum oxide layer with less impurity carbon and oxygen defects was obtained, and the breakdown voltage was improved.

【0026】また酸化タンタル層を形成した後第一の熱
処理に続いて第二の熱処理を行って膜を結晶化した後、
再び酸化タンタル層を形成し第一の熱処理に続いて第二
の熱処理を行う工程を一回以上繰返して形成した酸化タ
ンタルキャパシタの耐圧を図12に示した。図11に示
したキャパシタと同様に膜形成を細かく分けて行うほど
耐圧は向上し、図11の場合よりさらに緻密で高耐圧の
キャパシタを得ることができた。
After forming the tantalum oxide layer, the first heat treatment is followed by the second heat treatment to crystallize the film.
FIG. 12 shows the breakdown voltage of the tantalum oxide capacitor formed by repeating the step of forming the tantalum oxide layer again and performing the first heat treatment and then the second heat treatment one or more times. Similar to the capacitor shown in FIG. 11, the breakdown voltage was improved as the film formation was finely divided, and a more dense and high breakdown voltage capacitor could be obtained as compared with the case of FIG.

【0027】(実施例6)図13は結晶化アニールを行
った酸化タンタルキャパシタを実際に適用したDRAM
の断面図である。同図(a)は王冠型、(b)はフィン
型と呼ばれる構造で、64Mbit以降のDRAMのキ
ャパシタに必要とされる容量を確保するために立体化し
実効面積を大きくする工夫がなされている。このような
複雑な立体構造の場合には被覆性の良いCVD法が効果
的である。また、酸化タンタル膜をトランジスタのゲー
ト絶縁膜として用いた場合も結晶化アニールは効果があ
る。
(Embodiment 6) FIG. 13 shows a DRAM in which a tantalum oxide capacitor subjected to crystallization annealing is actually applied.
FIG. In the figure, (a) is a crown type structure, and (b) is a fin type structure, which has been devised so as to have a three-dimensional structure and a large effective area in order to secure the capacitance required for a DRAM capacitor of 64 Mbit or later. In the case of such a complicated three-dimensional structure, the CVD method with good coverage is effective. Crystallization annealing is also effective when a tantalum oxide film is used as a gate insulating film of a transistor.

【0028】以上の実施例は上部電極として窒化チタン
を用いた例を示したが、タングステン,チタン,タンタ
ル,モリブデンのうち一種以上の元素を含む金属あるい
はこれらの金属の積層膜の場合にも同様の効果が得られ
る。また、酸化タンタルの膜厚は2nm以上20nm以
下の範囲で同様の効果が得られた。さらに、酸化タンタ
ル膜を形成する原料はペンタエトキシタンタルを用いた
例について示したが、ペンタメトキシタンタル,ペンタ
ブトキシタンタル,ペンタクロロタンタル,ペンタフル
オロタンタル,ペンタブロモタンタルなど他の原料を用
いても、スパッタ法により形成しても同様の効果が得ら
れる。
In the above embodiments, titanium nitride was used as the upper electrode, but the same applies to a metal containing at least one element of tungsten, titanium, tantalum and molybdenum or a laminated film of these metals. The effect of is obtained. Similar effects were obtained when the film thickness of tantalum oxide was in the range of 2 nm to 20 nm. Furthermore, although an example using pentaethoxy tantalum as the raw material for forming the tantalum oxide film is shown, other raw materials such as pentamethoxy tantalum, pentabtox tantalum, pentachloro tantalum, pentafluoro tantalum, pentabromo tantalum may be used. The same effect can be obtained by forming by a sputtering method.

【0029】[0029]

【発明の効果】本発明を用いれば、高集積LSIに必要
とされる大容量,高耐圧,高信頼のキャパシタを製造す
ることができる。
According to the present invention, a large-capacity, high breakdown voltage, highly reliable capacitor required for a highly integrated LSI can be manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】酸化タンタルキャパシタの容量と耐圧の酸素ア
ニール温度依存性の説明図。
FIG. 1 is an explanatory diagram of oxygen annealing temperature dependence of capacitance and withstand voltage of a tantalum oxide capacitor.

【図2】酸化タンタル層結晶化の酸素アニール温度依存
性の説明図。
FIG. 2 is an explanatory diagram of oxygen annealing temperature dependence of crystallization of a tantalum oxide layer.

【図3】各種熱処理による不純物炭素量の低減効果の説
明図。
FIG. 3 is an explanatory diagram of the effect of reducing the amount of impurity carbon by various heat treatments.

【図4】酸化タンタルキャパシタの形成の工程を示す断
面図。
FIG. 4 is a cross-sectional view showing a step of forming a tantalum oxide capacitor.

【図5】結晶化アニールを行った酸化タンタルキャパシ
タのリーク電流密度の特性図。
FIG. 5 is a characteristic diagram of a leakage current density of a tantalum oxide capacitor that has been subjected to crystallization annealing.

【図6】第一の電極シリコン上の表面酸化膜を窒化した
後酸化タンタル層を形成したキャパシタの断面図。
FIG. 6 is a cross-sectional view of a capacitor in which a tantalum oxide layer is formed after nitriding a surface oxide film on a first electrode silicon.

【図7】第一の電極シリコン上の表面酸化膜を窒化した
後酸化タンタル層を形成したキャパシタのアニール条件
とリーク電流密度特性図。
FIG. 7 is an annealing condition and leakage current density characteristic diagram of a capacitor in which a tantalum oxide layer is formed after nitriding a surface oxide film on a first electrode silicon.

【図8】第一の電極層がタングステンである酸化タンタ
ルキャパシタの断面図。
FIG. 8 is a cross-sectional view of a tantalum oxide capacitor in which the first electrode layer is tungsten.

【図9】図10に示した評価を行ったキャパシタの断面
図。
9 is a sectional view of the evaluated capacitor shown in FIG.

【図10】逆の順番でアニールを行った酸化タンタルキ
ャパシタのリーク電流密度特性図。
FIG. 10 is a leakage current density characteristic diagram of a tantalum oxide capacitor annealed in the reverse order.

【図11】キャパシタのリーク電流密度特性図。FIG. 11 is a leakage current density characteristic diagram of a capacitor.

【図12】酸化タンタルキャパシタのリーク電流密度特
性図。
FIG. 12 is a leakage current density characteristic diagram of a tantalum oxide capacitor.

【図13】酸化タンタル膜を適用したDRAMキャパシ
タ部の断面図。
FIG. 13 is a cross-sectional view of a DRAM capacitor part to which a tantalum oxide film is applied.

【符号の説明】[Explanation of symbols]

1…シリコン基板、2…素子分離膜、3…高濃度リンド
ープ多結晶シリコン、4…界面酸化シリコン層、5…酸
化タンタル層、6…窒化チタン電極7…酸窒化膜、8
…タングステン層、9…酸化タングステン層、10…半
導体領域、11…ワード線、12…ビット線、13…下
部電極、14…酸化タンタル層、15…上部電極。
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation film, 3 ... High concentration phosphorus dope polycrystalline silicon, 4 ... Interface silicon oxide layer, 5 ... Tantalum oxide layer, 6 ... Titanium nitride electrode , 7 ... Oxynitride film, 8
... tungsten layer, 9 ... tungsten oxide layer, 10 ... half
Conductor area, 11 ... Word line, 12 ... Bit line, 13 ... Bottom
Partial electrode, 14 ... Tantalum oxide layer, 15 ... Upper electrode.

フロントページの続き (72)発明者 飯島 晋平 東京都国分寺市東恋ケ窪1丁目280番地 株式会社 日立製作所 中央研究所内 (72)発明者 横山 夏樹 東京都国分寺市東恋ケ窪1丁目280番地 株式会社 日立製作所 中央研究所内 (72)発明者 大路 譲 東京都国分寺市東恋ケ窪1丁目280番地 株式会社 日立製作所 中央研究所内 (72)発明者 木須 輝明 東京都小平市上水本町5丁目20番1号 日立超エル・エス・アイ・エンジニアリ ング株式会社内 (72)発明者 松井 裕一 東京都国分寺市東恋ケ窪1丁目280番地 株式会社 日立製作所 中央研究所内 (56)参考文献 特開 昭63−312664(JP,A) 特開 平5−114698(JP,A) 特開 平5−243524(JP,A) 特開 昭57−167669(JP,A) 特開 平4−328862(JP,A) 特開 平2−283022(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 27/04 H01L 21/822 H01L 27/108 H01L 21/8242 H01L 21/316 Front page continuation (72) Inventor Shinpei Iijima 1-280, Higashi Koikekubo, Kokubunji, Tokyo, Hitachi Central Research Laboratory (72) Inventor Natsuki Yokoyama 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory (72) Inventor, Yo Oji 1-280, Higashi Koigokubo, Kokubunji, Tokyo, Central Research Laboratory, Hitachi, Ltd. (72) Teruaki Kisu, 5-20 Kamisuihonmachi, Kodaira-shi, Tokyo Hitachi Ultra L.S.I.・ Engineering Co., Ltd. (72) Inventor Yuichi Matsui 1-280, Higashi Koigokubo, Kokubunji, Tokyo Metropolitan Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-63-312664 (JP, A) JP-A-5 -114698 (JP, A) JP 5-243524 (JP, A) JP 57-167669 (JP, A) JP 4-328862 (JP, A) JP 2-283022 (JP, A) ) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 27/04 H 01L 21/822 H01L 27/108 H01L 21/8242 H01L 21/316

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】シリコン基板上に形成された第一の絶縁膜
上に延在する第一の電極上に酸化タンタル層を形成した
後、前記酸化タンタル層中に含まれる炭素を脱離させる
ために第一の熱処理を酸素もしくは二窒化酸素雰囲気、
あるいはアルゴンや窒素で希釈された、酸素もしくは二
窒化酸素濃度0.1% 以上の雰囲気中600℃以上75
0℃以下の温度で行い、前記第一の熱処理より高温で前
記酸化タンタル層を結晶化できる温度においてかつアル
ゴンもしくは窒素の不活性雰囲気中もしくはアルゴン
たは窒素で0.1 %以下に希釈された酸素雰囲気で第二
の熱処理を行って前記酸化タンタル層を結晶化した後、
前記酸化タンタル層上に第二の電極を形成することを特
徴とするキャパシタの製造方法。
1. A tantalum oxide layer is formed on a first electrode extending on a first insulating film formed on a silicon substrate, and then carbon contained in the tantalum oxide layer is desorbed.
For the first heat treatment in an oxygen or oxygen dinitride atmosphere,
Or, in an atmosphere diluted with argon or nitrogen with oxygen or oxygen dinitride concentration of 0.1% or more, 600 ° C or more 75
It is performed at a temperature of 0 ° C. or lower and before the first heat treatment at a higher temperature .
Serial and in an inert atmosphere of argon or nitrogen at a temperature tantalum oxide layer can be crystallized or argon or
Or after performing a second heat treatment in an oxygen atmosphere diluted with nitrogen to 0.1% or less to crystallize the tantalum oxide layer,
A method of manufacturing a capacitor, comprising forming a second electrode on the tantalum oxide layer.
【請求項2】請求項1において、前記第一,第二の熱処
理のうち少なくとも一方はランプ加熱を用いて昇降温時
間、もしくは昇降温時間及びアニール時間を短縮するキ
ャパシタの製造方法。
2. The method for manufacturing a capacitor according to claim 1, wherein at least one of the first and second heat treatments uses lamp heating to shorten the temperature raising / lowering time or the temperature raising / lowering time and the annealing time.
【請求項3】請求項1において、前記第一の電極はシリ
コン層であるキャパシタの製造方法。
3. The method for manufacturing a capacitor according to claim 1, wherein the first electrode is a silicon layer.
【請求項4】請求項3において、前記シリコン層の表面
を窒化した後、前記酸化タンタル層を形成するキャパシ
タの製造方法。
4. The method of manufacturing a capacitor according to claim 3 , wherein the tantalum oxide layer is formed after nitriding the surface of the silicon layer.
【請求項5】請求項1において、前記第一の電極はタン
グステン,モリブデン、それらの窒化物、もしくはケイ
化物のうち一種からなる単層膜あるいは二種以上を複数
層積層した積層膜よりなるキャパシタの製造方法。
5. The capacitor according to claim 1, wherein the first electrode is a single-layer film made of one of tungsten, molybdenum, nitrides thereof, or a silicide thereof or a laminated film in which two or more layers are laminated. Manufacturing method.
【請求項6】請求項において、前記第一の熱処理は水
と水素を含む雰囲気中で行う、あるいは第一の熱処理後
もしくは第一の熱処理に続いて第二の熱処理を行った後
に水と水素を含む雰囲気中で熱処理を行うキャパシタの
製造方法。
6. The method according to claim 1 , wherein the first heat treatment is performed in an atmosphere containing water and hydrogen, or after the first heat treatment or after performing the second heat treatment after the first heat treatment. A method for manufacturing a capacitor, wherein heat treatment is performed in an atmosphere containing hydrogen.
【請求項7】請求項1において、前記酸化タンタル層
形成した後第一の熱処理を行う一連の工程を複数回繰り
返し、あるいは前記酸化タンタル層を形成した後第一の
熱処理を行い、続いて第二の熱処理を行う一連の工程
複数回繰り返すキャパシタの製造方法。
7. The method according to claim 1, wherein a series of steps of performing the first heat treatment after forming the tantalum oxide layer is repeated a plurality of times, or after performing the first heat treatment after forming the tantalum oxide layer , A method for manufacturing a capacitor, wherein a series of steps of performing a second heat treatment is repeated a plurality of times.
JP31626493A 1993-12-16 1993-12-16 Method for manufacturing capacitor Expired - Fee Related JP3404099B2 (en)

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JP3878724B2 (en) * 1997-10-14 2007-02-07 株式会社ルネサステクノロジ Semiconductor integrated circuit device and manufacturing method thereof
US6204203B1 (en) 1998-10-14 2001-03-20 Applied Materials, Inc. Post deposition treatment of dielectric films for interface control
JP3199114B2 (en) 1998-11-06 2001-08-13 日本電気株式会社 Method for manufacturing semiconductor device
KR20000053632A (en) * 1999-01-28 2000-08-25 카네코 히사시 Fabrication method of semiconductor device having electrode including tantalum oxide film
KR100497142B1 (en) * 1999-11-09 2005-06-29 주식회사 하이닉스반도체 Method of manufacturing a capacitor in a semiconductor device
JP2001217403A (en) * 2000-02-04 2001-08-10 Hitachi Ltd Semiconductor integrated circuit device and method of manufacturing the same
KR20020039838A (en) * 2000-11-22 2002-05-30 박종섭 Method for Fabricating Capacitor of Semiconductor Device
KR100379526B1 (en) * 2000-12-21 2003-04-10 주식회사 하이닉스반도체 Method for fabricating capacitor in semiconductor device
KR100761406B1 (en) * 2001-06-30 2007-09-27 주식회사 하이닉스반도체 Method for manufacturing a capacitor having a tantalum oxide film as a dielectric film
JP3839281B2 (en) 2001-07-05 2006-11-01 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
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