JP3404451B2 - Signal input device for burst signal input - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal input device for deleting an invalid data portion of an input signal by register setting when a burst signal having a burst length of N bytes is input.

[0002]

2. Description of the Related Art When transferring a transferred signal stored in a storage means on the transmitting side, CP is transferred before transferring the transferred signal.
It is necessary for U (central processing unit) to issue a transfer instruction to the storage device on the transmission side to the reception device side, and due to this work, the efficiency of transfer of the transferred signal to the reception device side becomes low.
Further, during the work, the CPU has to concentrate on the work, and there is a problem that other work cannot be performed.

Therefore, in general, the transferred signal is set as a burst signal of 2 ^n- byte structure such as 8 bytes, 16 bytes, 32 bytes, and the CPU only before transferring one burst signal to the receiving device side. The (central processing unit) issues a transfer instruction to the receiving device side to the storing means on the transmitting side, so that the transfer efficiency of the transferred signal to the receiving device side is improved and the burst transfer in which the work load of the CPU is reduced. Method is used.

As a means for efficiently performing this burst transfer, a DMA (Direct Memory Access) is used.
ss) controller is widely used,
It is general to transfer a burst signal having a burst length of 2 ⁿ bytes. The DMA controller refers to the transferred burst signal stored in the storage means on the transmission device side as CP
This is a device that automatically transfers to the receiving device side without going through U, and an example thereof is disclosed in Japanese Patent Laid-Open No. 7-135518.

[0005]

However, for example, as shown in FIG.
As shown in 1, when the end of the transferred signal is not at the end of one burst signal or when the end of the transferred signal is an odd byte of one burst signal, a fraction is included in one burst signal. Comes out. This fraction becomes an invalid signal in one burst signal and is transferred to the receiving device side.

In order to prevent this, even if burst transfer is performed, 1 is applied to a burst signal in which one of the burst signals includes the above invalid signal.
It is necessary for the CPU to issue a transfer command to the receiving side for the storage means on the transmitting side for each byte. But during this time,
Burst transfer cannot be performed, and the transfer efficiency of the transferred signal deteriorates in that part. Also, in the meantime,
The CPU needs to concentrate on the transfer work, and there is a problem that it cannot perform other work.

An object of the present invention is to solve such a problem and to improve the burst transfer efficiency and to improve the CPU work efficiency even for the transferred signal including the burst signal including the invalid signal as described above. Another object of the present invention is to provide a signal input device for burst signal input that can be enhanced.

[0008]

In order to achieve the above object, the present invention is provided with a burst signal input counter circuit, a valid burst termination setting register circuit, and a valid burst enable signal generating circuit. The effective burst termination setting value indicating the termination of the effective portion of one burst signal is stored in the effective burst termination setting register circuit, and the effective burst termination position value as the output signal and the output value of the burst signal input counter circuit. And a burst signal input byte count value, which is a valid burst enable signal generating circuit, and a valid burst enable signal that activates only a valid signal portion together with the input burst signal to an external device. .

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a signal input device for burst signal input according to the present invention, in which 100 is a transmitting device, 200 is an external device, and 300.
Is a signal input device, 1 is a burst enable signal generating circuit, 2 is a burst signal input counter circuit, and 3 is a valid burst termination setting register circuit. FIG. 2 is a timing chart showing the operation of the first embodiment.
Signals corresponding to are given the same reference numerals.

In FIG. 1 and FIG. 2, the input burst signal 11 has a burst length N from the transmitter 100 side to the signal input device 300 (where N is 2 ⁿ and n is a positive integer. When a burst signal 11 of bytes (n = 3 and thus N = 8) is supplied, an active burst enable signal 12 indicating that the supplied signal 11 is valid is also supplied. Further, when only the D2 (where D2 is an integer and D2 <N) bytes portion of the N-byte input burst signal 11 is valid, the end position of the valid portion of the input burst signal 11 is input. (In this case, D2, and in FIG. 2, D2 = 5), the effective burst termination setting value 14 is supplied from the transmitting apparatus 100 immediately before the input burst signal 11 and, together with this, the effective burst Termination setting value 14
Is also provided, which indicates that the valid burst setting enable signal 15 is valid.

In the signal input device 300, when the burst enable signal 12 is active, the burst signal input counter circuit 2 counts the number of bytes from the beginning to the end of the input burst signal 11 from 0 to (N-1). , When a count of burst signals is input and its count value becomes (N-1), it is reset to 0. Burst signal input byte count value 1 which is this count value
8 is supplied to the burst enable signal generation circuit 1.

The effective burst termination setting register circuit 3 is
When the effective burst setting enable signal 15 is active, the effective burst termination setting value 14 is fetched and held,
Until then, it retains the valid burst termination setting value that was fetched before. The held effective burst termination setting value 1
4 is supplied to the burst enable signal generating circuit 1 as the effective burst end position value 17.

The burst enable signal generating circuit 1 inputs a burst enable signal 12, a burst signal input byte count value 18 and an effective burst end position value 17, generates an effective burst enable signal 19 from these and outputs it.

Here, the effective burst end position value 1
Assuming that the value of 7 is D2 as described above, the burst enable signal generation circuit 1 will generate the burst enable signal 12
Is activated, the effective burst end position value 17 and the burst signal input byte count value 18 are fetched. Since the effective burst end position value 17 is D2, the burst signal input byte count value 18 is from 0 to D2. Is determined to be a valid burst signal, and during the active period of the input burst enable signal 12, the burst signal input byte count value 18 is made active from 0 to D2, which is the start end of the burst signal, and the burst signal is input. The byte count value 18 is (D2
Effective burst enable signal 19 which is inactive from +1) to (N-1) which is the end of the burst signal
Is generated and output. Therefore, the effective burst enable signal 19 becomes active from the first byte to the (D2 + 1) th byte of the input burst signal 11. This effective burst enable signal 19 is the input burst signal 1
Together with 1 are supplied to the external device 200 side.

On the external device 200 side, when the effective burst enable signal 19 is active, the input burst signal 11 is taken in, and when the effective burst enable signal 19 is inactive, the input burst signal 11 is not taken in. To do.

In this way, even if an invalid signal is included in one burst signal, in the external device 200, which is the receiving device, the valid burst enable signal 19 is inactive, so that the invalid signal is invalid. Since it is possible to determine that the burst signal including the invalid signal is read from the storage unit (not shown), the transmitting apparatus 100 can read the burst signal including the invalid signal from the storage unit (not shown). Therefore, the burst transfer efficiency is improved, and the work efficiency of the CPU (not shown) in the transmitter 100 is also improved.

FIG. 3 is a block diagram showing a second embodiment of the signal input device for burst signal input according to the present invention. Reference numeral 4 is an effective burst start setting register circuit, and the portions corresponding to those in FIG. 1 are the same. A reference numeral is given and a duplicate description is omitted. FIG. 4 is a timing chart showing the operation of the second embodiment shown in FIG.

In the first embodiment, the input burst signal 11 includes an invalid signal of an arbitrary number of bytes at the tail end thereof, but in the second embodiment, the input burst signal 11 is included.
This is a case where an invalid signal of an arbitrary number of bytes is included at the beginning of the.

3 and 4, the first byte A0 of the N-byte input burst signal 11 is an invalid signal. In this case, immediately before the input burst signal 11 is supplied from the transmission device 11 to the signal input device 300 (thus immediately before the burst enable signal 12 becomes active), the valid signal of the input burst signal 11 is changed. A valid burst start set value 13 indicating the first byte position (valid burst signal start position) and an active valid burst setting enable signal 15 indicating that the valid burst start set value 13 is valid are supplied.

In the signal input device 300, when the effective burst setting enable signal 15 becomes active, the effective burst start setting register circuit 4 fetches and holds the effective burst start setting value 13 supplied at the same time. Until then, it retains the effective burst start setting value that was fetched before. The held effective burst start edge set value 13 is supplied to the burst enable signal generation circuit 1 as the effective burst start edge position value 16.

The burst signal input counter circuit 2
When the burst enable signal 12 becomes active, the burst enable signal generation circuit 1 is supplied with a burst signal input byte count value 18 which changes from 0 to (N-1) with the input of the input burst signal.

Here, the effective burst start position value 1
When the value of 6 is D1 (D1 = 1 in FIG. 4), the burst enable signal generation circuit 1 determines from the effective burst start position setting register circuit 4 to the effective burst start position value 16 of D1 when the burst enable signal 12 becomes active. Of the input signal 11 is determined to be the effective burst signal from the D1 byte to the end (N-1) byte, and the burst signal input byte count value 18 is fetched from the burst signal input counter circuit 2 Generates a valid burst enable signal 19 which is inactive when the signal input byte count value 18 is between 0 and (D1-1) and is active between this burst signal input byte count value 18 is between D1 and (N-1) To do. The effective burst enable signal 19 is supplied to the external device 200 together with the input burst signal 11.

In the external device 200, when the valid burst enable signal 19 is active, the input burst signal 1
1 is taken in so that the input burst signal 11 is not taken in when the effective burst enable signal 19 is inactive.

As described above, also in the second embodiment, the invalid signal of the input burst signal 11 is the external device 20.
When 0 is eliminated, the same effect as that of the first embodiment can be obtained.

FIG. 5 is a diagram showing a third embodiment of the signal input device for a burst signal according to the present invention. The parts corresponding to those in FIGS. 1 and 3 are designated by the same reference numerals and their duplicate description will be omitted. . FIG. 6 is a timing chart showing the operation of the third embodiment shown in FIG.

The third embodiment is a combination of the first and second embodiments described above, and is adapted to extract an effective burst signal at an arbitrary position of an input burst signal. Is.

5 and 6, in the input burst signal 11, from the D1 byte to (D2 + 1).
The effective burst signal extends to the byte. However, in FIG. 6, D1 = 1 and D2 = 5.

As in the first and second embodiments, the effective burst start setting value 13 of D1 is set in the effective burst start setting register circuit 4 immediately before the input burst signal is supplied.
D5 is captured and held, and is supplied at the same time
The effective burst end setting value 14 of is acquired and held in the effective burst end setting register 3.

When the burst enable signal 12 is active, the burst signal input counter circuit 2 counts the number of bytes from the beginning to the end of the input burst signal 11 from 0 to (N-1), and a burst signal Is a counter circuit that resets to 0 after is input. The burst signal input byte count value 18 is an output signal from the burst signal input counter circuit 2.

When the burst enable signal 12 becomes active, the burst enable signal generation circuit 1 outputs the effective burst start position value 16 from the effective burst start setting register circuit 4 and the effective burst end position from the effective burst end setting register circuit 3. Take each value 17
Of the input burst signal 11, it is determined that the D1th byte to the (D2 + 1) th byte are valid burst signals, and the burst signal input byte count value 18 from the burst signal input counter circuit 2 is 0 to (D1- 1)
Is generated, the active burst enable signal 19 is generated and output from D1 to D2, and from (D2 + 1) to (N-1). This effective burst enable signal 19 is
It is supplied to the external device 200 together with the input burst signal 11.

In the external device 200, when the valid burst enable signal 19 is active, the input burst signal 1
1 is taken in so that the input burst signal 11 is not taken in when the effective burst enable signal 19 is inactive.

In this way, in the third embodiment, the external device 200 takes in only the effective burst signal at an arbitrary position of the input burst signal, which is different from the first and second embodiments. The same effect can be obtained.

By the way, in the above-described embodiment, when the valid burst termination setting value 14 is loaded into the valid burst termination setting register circuit 3, the same valid burst termination setting value is supplied until the next valid burst termination setting value is supplied. 1
4 is held as it is, and when the valid burst start set value 13 is taken into the valid burst start set register circuit 4, the same valid burst start set value 13 is kept until the next valid burst start set value is supplied. To be done. Therefore, if the position of the invalid burst signal in the next input burst signal 11 is different, or if there is only the valid burst signal without the invalid burst signal, the transmitting device 100
Must create a valid burst end set value 14 and a valid burst start set value 13 corresponding thereto and send them to the signal input device 300.

However, the state in which the input burst signal 11 includes the invalid burst signal frequently occurs, and the input burst signal 11 including the invalid burst signal rarely continues, it rarely continues, and the transmitter. Even when 100 is set, when the burst signal 11 including the invalid burst signal is transmitted and then the burst signal 11 including no invalid signal is transmitted, the valid burst end set value 14 and the valid burst start set value 13 are set to the burst signal 11. Creating a creation causes the CPU to do extra work.

FIG. 7 shows a fourth example of a signal input device for a burst signal according to the present invention, which solves such a problem.
FIG. 5 is a diagram showing an embodiment of the present invention, in which reference numeral 5 is a burst length / count value comparator, and the same reference numerals are given to the portions corresponding to those in the above drawings. FIG. 8 is a timing chart showing the operation of the fourth embodiment shown in FIG.

In the fourth embodiment, when the effective burst enable signal 19 for one input burst signal 11 is completed, the count value of the effective burst termination setting register circuit 3 is automatically reset to 0, and the effective burst enable signal 19 is effective. Set the count value of the burst start setting register circuit 4 to (N-
It is designed so that 1) can be automatically reset. Therefore, in the fourth embodiment, as shown in FIG. 7, a burst length / count value comparator 5 is provided.

7 and 8, for the first input burst signal 11a shown in the figure, the effective burst start position register circuit 4 sets the effective burst start position value 1 of D1.
6 is held and the effective burst end position value 17 of D5 is held in the effective burst end setting register circuit 3, the burst enable signal generation circuit 1 outputs the effective burst end position value 17 as described in the third embodiment. A valid burst enable signal 19 is output which is active during the period in which the burst signal input byte counter value 18 from the burst signal input counter circuit 2 is between D1 and D5.

This burst signal input byte count value 1
8 is also supplied to the burst length / count value comparator 5.
The burst length / count value comparator 5 compares the burst signal input byte count value 18 with (N-1) and sets the burst signal input byte count value 18 to the end of the input burst signal 11a. When it is detected that the position has reached (N-1), the burst end pulse 21 to be output is activated. The activation of the burst end pulse 21 resets the effective burst start setting register circuit 4 to 0 and the effective burst end setting register circuit 3 to (N-1). When the burst signal input counter circuit 2 is reset after the 1-byte period in which the burst signal input byte count value 18 is (N-1) has elapsed and the burst signal input byte count value 18 becomes 0, the burst length / The count value comparator 5 deactivates the burst end pulse 21.

In this way, the next input burst signal 1
When 1b is transferred, the effective burst start position value 16 from the effective burst start setting register circuit 4 is 0, the effective burst end position value 17 from the effective burst end setting register circuit 3 is (N-1), Even when the input burst signal 11b does not include the invalid burst signal, the burst enable signal generation circuit 1 can generate the valid burst enable signal 19 corresponding to the input burst signal 11b.

Of course, the effective burst start setting register circuit 4 and the effective burst end setting register circuit 3 are
It is reset before the transfer period of the effective burst setting enable signal 15 for the next input burst signal 11b. Therefore, when the next input burst signal 11b includes an invalid burst signal, these effective burst start setting register circuits are set. The corresponding effective burst start setting value 13 and the corresponding effective burst end setting value 14 are fetched and held in the 4 and the effective burst end setting register circuit 3.

As described above, the fifth embodiment can obtain the same effects as those of the previous embodiments, and
The CPU of the transmitter 100 saves the trouble of creating the effective burst start setting value 13 and the effective burst end setting value 14.
It is possible to improve the work efficiency of the and the burst transfer efficiency.

FIG. 9 is a block diagram showing a fifth embodiment of the signal input device for a burst signal according to the present invention. The parts corresponding to those in FIG. 7 are designated by the same reference numerals and their duplicate description will be omitted. Further, FIG. 10 is a timing chart showing the operation of the fifth embodiment shown in FIG.

The fifth embodiment is for the case where the burst length N of the input burst signal 11 is variable.
However, the burst length N is also configured to be 2 ⁿ bytes.

9 and 10, assuming that the burst length of the input burst signal 11 is Nmax (this Nmax differs depending on the input burst signal 11), this burst length Nmax (Nmax = 8 in FIG. 10 is set. The burst length setting value 20 indicating that the burst length setting value 20 is supplied from the transmitting device 100, and the burst length / count value comparator 5 outputs the burst signal input byte count value 18 from the burst signal input counter circuit 2 to the burst length setting value. When the burst signal input byte count value 18 reaches Nmax of the burst length setting value 20 in comparison with 20, the burst end pulse 21 is immediately activated, the effective burst start setting register circuit 4 is set to 0, and the effective burst end setting register is set to 0. Circuit 3
To (N-1) respectively.

As a result, the burst signal input byte count value 18 is from 0 to (N-1)
1 is made valid, and after the input burst signal 11 including an invalid signal is transferred, the next burst signal 1 to be inputted
It becomes unnecessary to send information for reset setting of the effective burst start setting register circuit 4 and the effective burst end setting register circuit 3 for making all 1s valid from the transmitting device 100.

Therefore, in this fifth embodiment,
For the input burst signal 11 having a variable burst length, FIG.
The same effect as that of the fourth embodiment shown in FIG.

Although the embodiment of the present invention has been described above, the present invention is not limited to the embodiment of the box. For example, the burst length / count value 5 in the embodiment shown in FIGS. 7 and 9 is provided in the embodiment shown in FIGS. 1 and 3, and these effective burst end setting register circuit 3 and effective burst start setting register circuit are provided. 4 may be automatically reset.

[0049]

As described above, according to the present invention,
On the receiving device side, the valid signal and the invalid signal of the input burst signal as the transferred signal can be judged, and the invalid signal can be deleted without receiving. Therefore, on the transmitting device side, the burst signal including the invalid signal can also be deleted. It can be read from the storage means and transferred in the same manner as the burst signal which does not include the invalid signal. Therefore, the burst transfer efficiency is improved and the work efficiency of the CPU in the transmitter is also improved.

Further, according to the present invention, it is possible to further reduce the time and effort required for the transmitter to create the effective burst start end setting value and the effective burst end end setting value. Therefore, the work efficiency of the CPU is improved and the burst transfer efficiency is improved. Can be increased.

Furthermore, according to the present invention, the same applies to a burst signal having a variable burst length.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a signal input device in burst signal input according to the present invention.

FIG. 2 is a timing chart showing an operation of the first embodiment shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of a signal input device in burst signal input according to the present invention.

FIG. 4 is a timing diagram showing an operation of the second exemplary embodiment shown in FIG.

FIG. 5 is a block diagram showing a third embodiment of a signal input device in burst signal input according to the present invention.

FIG. 6 is a timing diagram showing an operation of the third exemplary embodiment shown in FIG.

FIG. 7 is a block diagram showing a fourth embodiment of a signal input device in burst signal input according to the present invention.

8 is a timing chart showing an operation of the fourth exemplary embodiment shown in FIG. 7. FIG.

FIG. 9 is a block diagram showing a fifth embodiment of a signal input device in burst signal input according to the present invention.

FIG. 10 is a timing chart showing the operation of the fifth embodiment shown in FIG.

FIG. 11 is a diagram showing an example of an invalid burst signal.

[Explanation of symbols]

1 Effective burst enable signal generator 2 Burst signal input counter circuit 3 Effective burst termination setting register circuit 4 Effective burst start setting register circuit 5 Burst length / count value comparator 100 transmitter 200 receiver 300 Signal input device for burst signal input

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroki Mizozoe 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Multimedia system development headquarters (56) Reference JP-A-7-121471 (JP, A) JP-A-7-21117 (JP, A) JP-A-6-266612 (JP, A) JP-A-6-44180 (JP, A) JP-A-3-135647 (JP, A) JP-A 1-144148 (JP, A) JP 62-263560 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 13/28 310 G06F 13/38 320

Claims (5)

(57) [Claims] 1. A signal input device for burst signal input, when a burst enable signal indicating an input burst signal is active when a burst signal having a burst length of N bytes is input from the transmitter side. Burst signal input counter that counts the number of bytes for each input burst signal consisting of N bytes by counting the burst signal from 0 to (N-1) in byte units and then repeating the operation of setting the count value to 0 A circuit, a valid burst termination setting register circuit that stores a valid burst termination setting value indicating the termination of a valid portion of the input burst signal, and a burst signal input byte count value output from the burst signal input counter circuit Is valid output from the valid burst termination setting register circuit A valid burst enable signal that activates the valid burst enable signal when it is less than or equal to the burst end position value, and deactivates the valid burst enable signal when the burst signal input byte count value is greater than the valid burst end position value. A signal input device for burst signal input, comprising: a generation circuit. 2. A signal input device for burst signal input, when a burst signal having a burst length of N bytes is input from a transmitter side when a burst enable signal indicating an input burst signal is active. Burst signal input counter that counts the number of bytes for each input burst signal consisting of N bytes by counting the burst signal from 0 to (N-1) in byte units and then repeating the operation of setting the count value to 0 A circuit, a valid burst start setting register circuit that stores a valid burst start setting value indicating the beginning of a valid portion in the input burst signal, and a burst signal input byte count value output from the burst signal input counter circuit Is valid output from the valid burst start setting register circuit A valid burst enable signal that is active when the burst start position value is greater than or equal to the burst start position value, and inactive when the burst signal input byte count value is smaller than the valid burst start position value. A signal input device for burst signal input, comprising: a generation circuit. 3. A signal input device for burst signal input, when a burst enable signal indicating an input burst signal is active when a burst signal having a burst length of N bytes is input from the transmitter side. Burst signal input counter that counts the number of bytes for each input burst signal consisting of N bytes by counting the burst signal from 0 to (N-1) in byte units and then repeating the operation of setting the count value to 0 A circuit, a valid burst start setting register circuit that stores a valid burst start setting value that indicates the beginning of a valid portion of the input burst signal, and a valid that indicates the end of the valid portion of the input burst signal An effective burst termination setting register circuit for storing a burst termination setting value; The burst signal input byte count value output from the signal input counter circuit is greater than or equal to the effective burst start position value output from the effective burst start setting register circuit, and the effective burst termination output from the effective burst termination setting register circuit When it is less than the position value, the valid burst enable signal is activated, and when the burst signal input byte count value is smaller than the valid burst start position value or larger than the valid burst end position value, the valid burst And a valid burst enable signal generating circuit for deactivating an enable signal. 4. The burst signal input byte count value from the burst signal input counter circuit as set forth in claim 3, wherein:
A burst length / count value comparator for generating a burst end pulse indicating that the input of the input burst signal has ended, and when the burst end pulse becomes active,
The effective burst signal start setting register circuit is set to 0, and the effective burst signal end setting register circuit is set to (N-1).
By initializing the input burst signal, the effective burst signal start end set value and the effective burst signal end set value set before input of the input burst signal are set to one input after the start end and end set register values are set. A signal input device for burst signal input, which is effective only for burst signals. 5. The burst length according to claim 4, wherein the burst length is N (where N is 2 ⁿ and n
A burst length count value comparator for comparing the burst length set value Nmax with the burst signal input byte count value output from the burst signal input counter circuit. , The burst signal input byte count value is (Nmax−
When 1) is reached, the input burst signal bursts by initializing the effective burst signal start setting register circuit to 0 and the effective burst signal end setting register circuit to (Nmax−1). A signal input device for burst signal input, wherein an invalid signal in the input burst signal can be deleted when the length is variable.