JP3404733B2 - Digital comparator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital comparator used in an IC test apparatus, and more particularly to a digital comparator capable of mode switching for each test rate.

[0002]

2. Description of the Related Art A conventional digital comparator is used in an IC tester, and an IC under test (hereinafter referred to as DUT (Device
der test). The output signal from (1) is taken in through the test pin of the IC tester, converted into a digital signal, and then compared with an expected value.

FIG. 3 is a block diagram showing an example of such a conventional digital comparator. In FIG. 3, 1 and 2 are analog comparators, 3 is a digital comparator, 4 is a digital function controller, 5 is an expected value memory circuit, 6 is a timing generation circuit, 7 is a mode setting register circuit, 8 is a fail memory circuit, and 100. Is an input signal, and 101 and 102 are threshold voltages.

Further, 1 and 2 are digital conversion means 50.
3 to 6 constitute the digital comparison means 51, respectively.

The input signal 100 is the analog comparators 1 and 2
One of the input terminals is input to one of the input terminals, and the other input terminals of the analog comparators 1 and 2 are input to the threshold voltages 101 and 102, respectively. Also, analog comparator 1
The outputs of and 2 are connected to the digital comparator 3.

Address signals and control signals from the digital function controller 4 are respectively connected to the expected value memory circuit 5 and the timing generation circuit 6, and the outputs of the expected value memory circuit 5, the timing generation circuit 6 and the mode setting register circuit 7 are digital. Each is connected to the comparator 3.

The output of the digital comparator 3 is connected to the fail memory circuit 8, and the control signal from the digital function controller 4 is also connected to the fail memory circuit 8.

The operation of the conventional example shown in FIG. 3 will be described. In a general IC test apparatus, components other than the digital function controller 4 are provided for each test pin of the IC test apparatus, and D is input via each test pin.
The signal from the UT corresponds to the input signal 100, respectively.

The input signal 100 is the analog comparators 1 and 2.
Is compared with the threshold voltages 101 and 102 at.
The threshold voltage 101 is a threshold voltage on the high level side, and for example, the voltage value of the input signal 100 is the threshold voltage 1
If it is higher than 01, the output of the analog comparator 1 becomes high level.

Similarly, the threshold voltage 102 is a low-level threshold voltage. For example, if the voltage value of the input signal 100 is higher than the threshold voltage 102, the output of the analog comparator 2 is high level. become.

Therefore, if the voltage value of the input signal 100 is smaller than the threshold voltage 102, the outputs of the analog comparators 1 and 2 both become low level, and the voltage value of the input signal 100 becomes the threshold voltage 101. If it is larger, the outputs of the analog comparators 1 and 2 both become high level.

If the voltage value of the input signal 100 is between the threshold voltage 101 and the threshold voltage 102, the output of the analog comparator 1 becomes low level and the output of the analog comparator 2 becomes high level. .

That is, two analog comparators 1 and 2
Thus, the input signal 100 is converted into a 2-bit digital signal, and this digital signal is input to the digital comparator 3.

On the other hand, the digital function controller 4 inputs the address signal to the expected value memory circuit 5 to output the expected value data to the digital comparator 3 and controls the timing generation circuit 6 with the control signal to generate the strobe signal. Output to the digital comparator 3.

The digital comparator 3 compares the input digital signal with the expected value data at the timing of the strobe signal and outputs a match / mismatch comparison result. Further, the digital function controller 4 controls the fail memory circuit 8 by the control signal to write the comparison result in the fail memory circuit 8.

As a result, the DUT is converted by converting the input signal 100 into a digital signal and comparing it with expected value data.
It is possible to obtain the normal or abnormal output from.

Further, the digital comparator 3 performs the comparison in synchronization with the strobe signal, but in general, the "edge strobe mode" for comparing when the edge of the strobe signal occurs and the period formed from two strobe signals There are two types of modes: "window strobe mode" for comparison within (window).

In the mode setting register circuit 7, which of the two types of modes is selected is preset.
The mode setting register circuit 7 selects the "edge strobe mode" or the "window strobe mode" of the digital comparator 3 according to its output.

That is, the mode of the mode setting register circuit 7 can be set for each test pin of the IC test apparatus, so that the mode for each test pin of the IC test apparatus can be set according to the test purpose of the DUT. Become.

[0020]

However, the conventional example shown in FIG. 3 has a problem that mode switching cannot be performed during the test.

Therefore, for example, when the mode is switched for each test rate, the IC is connected to one pin of the DUT.
Using two test pins of the test equipment, one test pin is "edge strobe" and the other test pin is "
There is a problem that it is necessary to perform the test by setting each to the "window strobe", and the use efficiency of the test pin of the IC test device is lowered. Therefore, the problem to be solved by the present invention is to solve the test rate. It is to realize a digital comparator capable of switching modes for each.

[0022]

In order to achieve such a object, according to the first aspect of the present invention, in a digital comparator used in an IC test apparatus, a digital converting means for converting an analog signal into a digital signal, and The expected value data is composed of digital comparison means for comparing a digital signal and expected value data in synchronization with the strobe signal, a fail memory circuit for storing the output of the digital comparison means, and an edge / window strobe selection memory circuit. Mode selection means for selecting the mode of the digital comparison means in response to a mode selection signal output from the edge / window strobe selection memory circuit in synchronism with the output of FIG.

In order to achieve such a subject, in the second aspect of the present invention, in a digital comparator used in an IC test apparatus, a digital converting means for converting an analog signal into a digital signal, the digital signal and expected value data. And a fail comparison circuit for storing the output of the digital comparison means, an edge / window strobe selection memory circuit, an edge strobe mode, and a window comparison circuit.
The strobe mode or the edge / window strobe rate switching mode is set and the edge / window
And a mode setting register circuit having a designation register for designating a specific bit of the window strobe selection memory circuit, and selects the mode of the digital comparison means based on the data of the specific bit when the edge / window strobe rate switching mode is selected. And a mode selecting means for performing the operation.

In order to achieve such a subject, in a third aspect of the present invention, in a digital comparator used in an IC test apparatus, a digital converting means for converting an analog signal into a digital signal, the digital signal and expected value data. And a pattern memory circuit and a formatter for storing the output of the digital comparison means, and the pattern is synchronized with the output of the expected value data. The formatter further comprises a mode selection means for generating a strobe signal suitable for the mode of the digital comparison means based on pattern data output from the memory circuit.

[0025]

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the drawings. FIG. 1 is a configuration block diagram showing an embodiment of a digital comparator according to the present invention.

1 to 8, 50, 51 and 10 in FIG.
Reference numerals 0 to 102 are the same as those in FIG. 3, and 9 is an edge / window strobe selection memory circuit. Also,
Reference numerals 7 and 9 constitute the mode selection means 52.

The input signal 100 is the analog comparators 1 and 2
One of the input terminals is input to one of the input terminals, and the other input terminals of the analog comparators 1 and 2 are input to the threshold voltages 101 and 102, respectively. Also, analog comparator 1
The outputs of and 2 are connected to the digital comparator 3.

The address signal from the digital function controller 4 is connected in parallel to the expected value memory circuit 5 and the edge / window strobe selection memory circuit 9, and the control signal from the digital function controller 4 is connected to the timing generation circuit 6.

The outputs of the expected value memory circuit 5, the timing generation circuit 6, the mode setting register circuit 7 and the edge / window strobe selection memory circuit 9 are the digital comparator 3.
Respectively connected to.

The output of the digital comparator 3 is connected to the fail memory circuit 8, and the control signal from the digital function controller 4 is also connected to the fail memory circuit 8.

The operation of the embodiment shown in FIG. 1 will be described here. Since the basic operation is the same as that of the conventional example shown in FIG. 3, the description of that part is omitted.

As described above, the input signal 100 is converted into a digital signal by the analog comparators 1 and 2 and input to the digital comparator 3.

On the other hand, the digital function controller 4 sends the address signal to the expected value memory circuit 5 and the edge /
Input to the window strobe selection memory circuit 9. With this address signal, expected value data is output from the expected value memory circuit 5, and at the same time, a mode selection signal is output from the edge / window strobe selection memory circuit 9 to the digital comparator 3.

A mode for each test rate is preset in the edge / window strobe selection memory circuit 9, and a mode set in synchronization with an address signal from the digital function controller 4 is output as the mode selection signal.

Further, the digital function controller 4 controls the timing generation circuit 6 with a control signal to generate a strobe signal and output it to the digital comparator 3.

The digital comparator 3 compares the input digital signal with the expected value data at the timing of the strobe signal and outputs a match / mismatch comparison result.

At this time, the "edge strobe mode" or "window strobe mode" of the digital comparator 3 is selected based on the mode selection signal from the edge / window strobe selection memory circuit 9, and the digital comparator 3 The comparison is performed in this mode, and the comparison result is stored in the fail memory circuit 8.

That is, since the mode for each test rate is set in the edge / window strobe selection memory circuit 9, the digital comparator 3 switches the mode for each test rate according to the setting.

As a result, the mode selection signal is output from the edge / window strobe selection memory circuit 9 in synchronization with the address signal from the digital function controller 4 and the mode of the digital comparator 3 is selected. Mode switching becomes possible.

Further, since it is possible to switch the mode for each test mode, it is not necessary to use two test pins of the IC test device for one pin of the DUT as in the conventional example, and the test pin of the IC test device is used. Efficiency is improved.

Although the mode setting register circuit 7 is illustrated in FIG. 1, the mode setting register circuit 7 is necessary if the edge / window strobe selection memory circuit 9 is provided for each test pin of the IC test apparatus. Absent.

Further, the edge / window strobe selection memory circuit 9 is not provided for each test pin of the IC test apparatus,
When the edge / window strobe selection memory circuit 9 of several bits is provided for each device, the mode setting register circuit 7
is necessary.

In this case, the mode setting register circuit 7 is provided with "edge / strobe mode" and "window / strobe mode" as well as "edge / edge strobe mode".
It also has a switching mode for each window strobe rate ", and also has a designation register indicating which bit of the edge / window strobe selection memory circuit 9 of several bits is designated.

For example, the mode setting register circuit 7 has "
Consider the case where the "edge / window strobe rate switching mode" is set and the "second bit" of the edge / window strobe selection memory circuit 9 is designated in the designation register.

The output of the mode setting register circuit 7 is the "edge / window strobe rate switching mode", and at the same time, since the "second bit" is designated in the designation register, the edge / window strobe selection memory circuit 9 is "Edge strobe mode" of the digital comparator 3 for each test rate according to the "2nd bit" data
Alternatively, the "window strobe mode" is selected.

That is, the mode of the digital comparator 3 is switched according to the mode for each test rate set in the edge / window strobe selection memory circuit 9.

As a result, if the "edge / window strobe rate switching mode" is set, the mode switching for each test rate becomes possible based on the designated bit of the edge / window strobe selection memory circuit 9.

Further, depending on the IC test apparatus, it is not necessary to provide the timing generation circuit 6 for each test pin of the IC test apparatus, and it may be sufficient to provide one set for each of the plurality of test pins. FIG. 2 is a configuration block diagram showing an embodiment of a digital comparator in such a case.

In FIG. 2, 1 to 5, 8, 50, 100,
101 and 102 have the same reference numerals as those in FIG.
Is a timing generation circuit, 10 is a formatter, and 11 is a pattern memory circuit.

Further, 3 to 5 are digital comparison means 51a.
, 6a, 10 and 11 respectively constitute the mode selecting means 52a.

The input signal 100 is the analog comparators 1 and 2
One of the input terminals is input to one of the input terminals, and the other input terminals of the analog comparators 1 and 2 are input to the threshold voltages 101 and 102, respectively. Also, analog comparator 1
The outputs of and 2 are connected to the digital comparator 3.

The address signal from the digital function controller 4 is connected in parallel to the expected value memory circuit 5 and the pattern memory circuit 11, and the control signal from the digital function controller 4 is connected to the timing generation circuit 6a.

The output of the timing generation circuit 6a is connected to the formatter 10, and the output of the pattern memory circuit 11 is also connected to the formatter 10.

Expected value memory circuit 5 and formatter 10
The output of each is connected to the digital comparator 3.

The output of the digital comparator 3 is connected to the fail memory circuit 8, and the control signal from the digital function controller 4 is also connected to the fail memory circuit 8.

The operation of the embodiment shown in FIG. 2 will be described here. However, the description of the common part is omitted. The digital function controller 4 inputs the address signal to the expected value memory circuit 5 and the pattern memory circuit 11. Due to this address signal, expected value data is sent from the expected value memory circuit 5 to the digital comparator 3 and at the same time to the pattern memory circuit 11
To output format data to the formatter 10, respectively.

Pattern data for generating a strobe signal corresponding to a mode for each test rate is preset in the pattern memory circuit 11, and the pattern data is output in synchronization with the address signal from the digital function controller 4.

Further, the digital function controller 4 controls the timing generation circuit 6a by the control signal to generate the timing signal and output it to the formatter 10.

The formatter 10 is the pattern memory circuit 1
The timing signal is processed on the basis of the pattern data output from 1 to output "edge strobe edge" or "window strobe start edge" and "window strobe end edge".

The digital comparator 3 compares the digital signal with the expected value data based on the type of strobe signal output from the formatter 10.

For example, if the "strobe edge" is output from the formatter 10, the digital comparator 3 performs the comparison in the "edge strobe mode", while the "strobe start edge" and the "strobe end edge" are output. Is output, the digital comparator 3 performs the comparison in the "window strobe mode".

As a result, the formatter 10 generates a strobe signal suitable for the mode on the basis of the pattern data output from the pattern memory circuit 11 in synchronization with the address signal from the digital function controller 4. It becomes possible to switch.

In this case, the mode setting register circuit 7 and the edge / window strobe selection memory circuit 9 are also included.
Is unnecessary, the configuration is simplified.

[0065]

As is apparent from the above description,
The present invention has the following effects. By outputting the mode selection signal from the edge / window strobe selection memory circuit in synchronization with the address signal from the digital function controller to select the mode of the digital comparator 3, a digital comparator capable of switching the mode for each test rate is provided. realizable.

Further, the formatter generates a strobe signal suitable for the mode based on the pattern data output from the pattern memory circuit in synchronization with the address signal from the digital function controller.
Mode switching for each test rate becomes possible.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of a digital comparator according to the present invention.

FIG. 2 is a configuration block diagram showing an embodiment of a digital comparator.

FIG. 3 is a configuration block diagram showing an example of a conventional digital comparator.

[Explanation of symbols]

1,2 analog comparator 3 Digital comparator 4 Digital function controller 5 Expected value memory circuit 6,6a Timing generation circuit 7 Mode setting register circuit 8 Fail memory circuit 9 Edge / Window strobe selection memory circuit 10 formatter 11 Pattern memory circuit 50 Digital conversion means 51,51a Digital comparison means 52, 52a Mode selection means 100 input signal 101,102 threshold voltage

Claims (3)

(57) [Claims] 1. A digital comparator used in an IC test apparatus, comprising: digital conversion means for converting an analog signal into a digital signal; and digital comparison means for comparing the digital signal and expected value data in synchronization with a strobe signal. It is composed of a fail memory circuit for storing the output of the digital comparison means and an edge / window strobe selection memory circuit. The edge / window strobe selection memory circuit is synchronized with the output of the expected value data.
A digital comparator comprising: a mode selection unit that selects a mode of the digital comparison unit according to a mode selection signal output from a window strobe selection memory circuit. 2. A digital comparator used in an IC test apparatus, comprising: digital conversion means for converting an analog signal into a digital signal; and digital comparison means for comparing the digital signal and expected value data in synchronization with a strobe signal. A fail memory circuit for storing the output of the digital comparing means, an edge / window strobe selection memory circuit, and an edge strobe mode, a window strobe mode or an edge / window strobe rate switching mode are set, and the edge / window strobe is set. And a mode setting register circuit having a designation register for designating a specific bit of a selected memory circuit, wherein the digital signal is based on the data of the specific bit when the switching mode for each edge / window strobe rate is selected. A digital comparator comprising: a mode selection unit that selects a mode of the comparison unit. 3. A digital comparator used in an IC test apparatus, comprising: digital conversion means for converting an analog signal into a digital signal; and digital comparison means for comparing the digital signal and expected value data in synchronization with a strobe signal. A fail memory circuit for storing the output of the digital comparing means, a pattern memory circuit and a formatter are provided, and the formatter outputs the digital data based on the pattern data output from the pattern memory circuit in synchronization with the output of the expected value data. A digital comparator, comprising: a mode selection means for generating a strobe signal suitable for the mode of the comparison means.