JP3406432B2 - Liquid crystal video display device and video signal processing circuit of video display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention makes it possible to display an image in the horizontal direction of the display screen even if the aspect ratio of the image signal is different from that of the display screen. The present invention relates to a liquid crystal image display device and an image signal processing circuit in which a region having a plurality of expansion / contraction rates is provided in the axial direction.

[0002]

2. Description of the Related Art Television receivers which receive terrestrial broadcasting such as UHF / VHF or satellite broadcasting to display an image and display an input video signal from a video device such as a VTR are currently the most popular. It is used as an image display device.

Conventionally, the display screen size of a television receiver has various sizes, but the aspect ratio is unified to 3: 4,
The broadcast video displayed on it and the input video signals from various devices are also configured as video with the same aspect ratio of 3: 4, so that when displayed on the screen, they can be displayed as video without vertical or horizontal expansion. It was

However, in recent years, in order to enable more powerful and immersive image display, beginning with the adoption of a horizontally long display image having an aspect ratio of 9:16 in a high definition image standard such as high definition. Even conventional television receivers of standard video standards such as NTSC, which have a display screen with an aspect ratio of 9:16, have been put on the market, and their occupancy rates are rapidly increasing. Along with that, the number of display video signals having an aspect ratio of 9:16 is also increasing.

However, most of the conventional video signals have an aspect ratio of 3: 4, and the aspect ratio is 9:16.
Even in the case of using a television receiver having the above display screen, in most cases, a video signal having an aspect ratio of 3: 4 is to be displayed. In such a case, a problem occurs because the aspect ratio of the display image signal is different from that of the television receiver.

[0006]

The problem to be solved by the invention is shown in FIG.
(B) shows a display state in the case of displaying all video signals with an aspect ratio of 3: 4 on the display screen with an aspect ratio of 9:16 without omission.

FIG. 14 (a) shows a video signal having an aspect ratio of 3: 4 embedded in a display screen having an aspect ratio of 9:16. The video signal has a vertical and horizontal aspect ratio of 3: 4. Although the image is displayed in a non-stretched state and the entire image can be displayed, the non-image portion where the image is not displayed occurs on the left and right because the display screen is horizontally long with the aspect ratio of 9:16. In this case, there is a problem in that it is not possible to fully utilize the fact that the display area is enlarged as a horizontally long screen having an aspect ratio of 9:16.

FIG. 14B shows a case where a video signal having an aspect ratio of 3: 4 is horizontally stretched and the entire video image is displayed at the full display screen having an aspect ratio of 9:16. Due to the difference in aspect ratio, the display video signal is approximately 1.
It has been stretched three times.

In this case, although the entire image is displayed in the full display screen with the aspect ratio of 9:16, the content of the image is stretched in the horizontal direction, and the displayed image becomes uncomfortable. .

The state at this time will be examined with reference to the relationship between the display video signal, the sampling clock and the liquid crystal panel picture element for one line shown in FIGS. 15 (a) and 15 (b).

In FIG. 15A, the display section T of the video signal is displayed.
Is sampled by using the clock pulse 1 having the frequency f1 and the sampling period of t1.
The image data of 1 is obtained, and the image is displayed on N1 picture elements for one line of the liquid crystal panel. A non-image portion is formed at both ends of the image display portion of the liquid crystal panel, and the non-image portion has a sampling period t1 'in the blanking interval T'where no image signal is present.
Sampling using the clock pulse 1'of the frequency f1 'is to obtain the image data for the non-image of the sample number N1', and give the image data to N1 'picture elements of the liquid crystal panel. It is provided in. As shown in the figure, if there is a non-picture part with a picture element number N1 ′ at both ends of a video display part with a picture element number N1, the sum N1 + 2 × N1 ′ of these is the picture element number N2 for one line of the liquid crystal panel.

In FIG. 15B, sampling is performed by using the clock pulse 2 having the frequency f2 (f1 <f2) with the sampling period t2 (t1> t2) in the display section T of the same video signal. Number N2 (N1 <N
Image data of 2) is obtained, and the picture element N for one line of the liquid crystal panel
Display the video on all two.

FIG. 16 is a block diagram of a circuit configuration for performing the two types of image display shown in FIGS. 14 (a) and 14 (b).
become that way. A clock pulse generation circuit 1 (2-1) that outputs a clock pulse of frequency f1 in the image display area and outputs a clock pulse of frequency f1 ′ in the blanking area.
And a clock pulse generation circuit 2 (2-2) that outputs a clock pulse of frequency f2, and outputs their outputs according to a clock switching signal (2b) from a system controller (not shown) in the liquid crystal image display device. The clock pulse selected by the changeover switch (2-3) is output to the control circuit (2-4). The switching between the frequencies f1 and f1 ′ in the clock pulse generating circuit 1 between the video display area and the blanking area is performed at the frequency f.
It is also possible to input two clock pulses of 1 and f1 ′ to the control circuit (2-4) and switch the control circuit (2-4).

From the control circuit (2-4), the sampling pulse created based on the input clock pulse is sent to the sample hold circuit (2-6) through the shift register (2-5), and the video amplification circuit. A video signal (2a) input from (not shown) is sampled, and the sampled video data is sent to each picture element of the liquid crystal panel (2-8) via the output buffer circuit (2-7). An image is displayed on this liquid crystal panel (2-8). This enables display in two types of modes shown in FIGS. 14 (a) and 14 (b).

Here, in the image display state shown in FIGS. 14 (a) and 14 (b), as described above, the image signal having the aspect ratio of 3: 4 is displayed as it is on the screen having the aspect ratio of 9:16. There is a non-image part, and the entire screen is not fully utilized for displaying.On the other hand, since the entire screen is displayed, the displayed image is stretched horizontally and the display is visually uncomfortable. There was a problem that it had become.

Aspect ratio 9: Wide TV
As a countermeasure for the above state in a display device having a display screen composed of 16 cathode ray tubes, there is disclosed in Japanese Patent Laid-Open No. 6-66.
34, by increasing the capacity of the S-shaped correction capacitor and the power supply voltage of the horizontal deflection output circuit,
The horizontal deflection current is modulated so that the scanning speed of the electron beam increases at the left and right edges of the display screen, and the display size is enlarged toward the left and right edges of the horizontal direction, and a saturable coil is installed in the horizontal deflection output circuit. The display size is increased by increasing the difference in horizontal deflection current between the central portion and the left and right end portions of the display screen, and increasing the display size toward the left and right end portions of the central portion of the display screen.

However, these countermeasures are methods applicable to a drive circuit in an image display device using a cathode ray tube, and cannot be applied to devices such as liquid crystals having different image display drive methods.

Further, Japanese Patent Laid-Open No. 6-6634 discloses a method of using a memory as a method of modulating the time axis of a video signal. This is to perform time-axis modulation by keeping the write clock of the memory constant in frequency, lowering the frequency of the read clock at the beginning and end of one horizontal cycle, and increasing the frequency in the middle part.

The read clock is obtained by FM-modulating a signal having a low voltage change waveform at the beginning and end of one horizontal period and a high voltage change waveform at the intermediate portion as shown in FIG. At this time, the number of writing and reading clocks in one horizontal cycle of the video signal must be constant in each horizontal line so that the display video is not distorted and missing, and the number of clocks of the modulated clock The phase change must also be constant in each horizontal cycle. For that purpose, it is necessary to accurately manage the period and number of each clock within one horizontal period of the video signal. In this case, the frequency of the clock pulse is not directly handled, but the voltage value is converted to the frequency by the FM modulation. Due to the conversion, the effects of component variations and noise are large, making it extremely difficult to accurately manage and control them as a total, and the display size increases as the left and right edges of the display screen are approached. However, there is a problem in that it is difficult to obtain a similar display size change pattern in each horizontal period.

In view of such a problem, the present invention sets the variation form of the enlargement of the display size of the video signal in the horizontal direction to be always constant in each horizontal period, and displays even when the aspect ratio of the video signal and the display screen is different. The video signal has a reduced portion and an extended portion in the time axis direction within the horizontal scanning period so that the image can be fully displayed in the horizontal direction of the display screen, and the aspect ratio of the image signal and the screen display matches near the center of the screen. An object of the present invention is to provide a liquid crystal image display device and an image signal processing circuit that can reduce the visual discomfort by providing the round portion as wide as possible.

[0021]

In order to solve the above-mentioned problems, the present invention has the following constitution. According to a first aspect of the present invention, in a video display device using liquid crystal, a liquid crystal drive circuit including a shift register, a sample hold circuit, and a buffer circuit, and a reference clock pulse generation circuit that outputs a reference clock pulse signal that is the sample pulse. A clock pulse frequency conversion circuit for converting the input reference clock pulse signal into a pulse signal having a plurality of frequencies stepwise without changing the number of samples in one horizontal scanning period of the video signal; A liquid crystal video display device comprising a switch for switching a clock pulse, and a video signal to be displayed on a liquid crystal panel is provided with a region having a plurality of expansion / contraction ratios in a time axis direction within a horizontal scanning period. is there.

According to the first aspect of the invention, in the clock pulse frequency conversion circuit, the delay elements having a constant delay time are connected in series, and the output of each delay element is taken out so that the input reference clock pulse signal is obtained. A multi-phase delay circuit that makes a pulse signal of a plurality of phases delayed by a fixed time, and a phase selection switch that selects a phase signal to be output from the pulse signals of the plurality of phases output from the multi-phase delay circuit. And a phase selection signal generating circuit for instructing which phase of the pulse signal is selected by the phase selection changeover switch.

According to a second aspect of the present invention, in the phase selection signal generating circuit, the selection of a plurality of phase pulse signals output from the multi-phase delay circuit is selected by the phase selection changeover switch with the number of selected phase intervals being an even number. and the pulse signal phase, according to claim 1, characterized in that is performed by using a pulse signal phase corresponding to the number of interphase of a predetermined ratio of said selected phase number of intervals (e.g., 1/2) It is a liquid crystal image display device.

According to a third aspect of the present invention, in the video signal processing circuit, a reference clock pulse generation circuit, an AD converter, a line memory and a clock pulse frequency conversion circuit are provided, and the reference clock pulse generation circuit is a reference clock of a predetermined frequency. The clock pulse frequency conversion circuit outputs a pulse signal, and the clock pulse frequency conversion circuit has a delay
The elements are connected in series and each delay element output is taken.
The input reference clock pulse signal
Signal is a multi-phase pulse signal delayed by a fixed time.
Output from the multi-phase delay circuit
Select the phase signal to be output from the multi-phase pulse signals
The phase selection switch and the phase selection switch
Phase selection to instruct which pulse signal to select with H
A signal generating circuit, and the clock pulse signal output from the reference clock pulse generating circuit is changed into a pulse signal having a plurality of frequencies stepwise without changing the number of samples in one horizontal scanning period of the video signal. To convert the output pulse signal of the clock pulse frequency conversion circuit to AD
By using as the sampling clock signal of the converter and the write clock signal of the line memory, and by using the reference clock pulse signal as the read clock signal of the line memory, the video signal has a plurality of expansion / contraction ratios in the time axis direction within the horizontal scanning period. A video signal processing circuit of a video display device, characterized in that a region is provided.

By the way, according to the knowledge of the inventor, when considering that a person tends to concentrate on the central portion of a video display screen as compared to the peripheral portion, a video signal having an aspect ratio of 3: 4 is displayed in the vertical and horizontal directions. When displaying on a screen with a ratio of 9:16, it is conceivable that the central portion of the screen is a perfect circle area and the left and right edges of the screen are expansion areas, which results in the display as shown in FIG. 14 (c).

The relationship between the display video signal, the sampling clock, and the picture elements for one line of the liquid crystal panel at this time is shown in FIG.
It looks like (c). In the display section T of the video signal, the clock pulse changes to the low frequency side at the central part and to the high frequency side at both ends, and if the frequency at the central part is f1 which is the same as the clock pulse 1 in (a). In the central portion, the display image can be a perfect circular region in which the image having the aspect ratio of 3: 4 is not vertically extended and horizontally extended as in (a). The number of samples in the video display section T is N2, which is the same as in (b).
By setting the frequency change state of the clock pulse so that, the image display can be performed on all the two picture elements N for one line of the liquid crystal panel.

The present invention has been made based on the above findings. With the configuration of the first aspect of the invention, a plurality of frequencies are gradually changed without changing the number of samples in one horizontal scanning period of the video signal. Since the pulse signal is converted into a pulse signal, the video signal to be displayed is provided with a reduced portion or an extended portion in the time axis direction within the horizontal scanning period when the aspect ratio of the video signal and the video display screen are different. It is possible to display an image with a predetermined width, for example, in the horizontal direction, and reduce the visual discomfort by providing a perfect circle portion where the aspect ratio of the image signal matches the aspect ratio of the screen display near the center of the screen. It is a thing.

According to the first aspect of the present invention, a plurality of phase pulse signals for delaying the input pulse signal by a constant time are taken out by a configuration in which delay elements having a constant delay time are simply connected in series. Then, the phase selection signal generation circuit gives an instruction as to which phase of the pulse signal is selected by the phase selection changeover switch.

According to the second aspect of the present invention, when the pulse signal is selected, for example, by using the pulse signal of the phase corresponding to the number of phase intervals of 1/2 of the number of phase selection intervals, the duty ratio of 50% is obtained. A pulse signal can be output.

Further, according to the invention of claim 3, in the video display device of any display screen, the video signal to be displayed includes an area having a plurality of expansion / contraction ratios in the time axis direction within the horizontal scanning period. Can be provided.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration of the entire liquid crystal image display device according to the first embodiment of the present invention.

In FIG. 1, a clock pulse generation circuit 1
(1-1) switches the clock pulse of the frequency f1 in the image display area and the clock pulse of the frequency f1 ′ in the blanking area to switch to the subsequent changeover switch (1-
Output to 4).

Further, the clock pulse generation circuit 2 (1-
2) outputs the clock pulse of frequency f2 to the changeover switch (1-4).

Clock pulse frequency conversion circuit (1-3)
Then, the clock pulse of the frequency f2 output from the clock pulse generation circuit 2 (1-2) is input, and using it as a reference pulse, the number of pulses in one horizontal scanning period of the video signal is not changed and is stepwise. And outputs the clock pulse converted into the pulse signal having a plurality of frequencies to the changeover switch (1-4).

The three clock pulses output from the clock pulse generation circuit 1 (1-1), the clock pulse generation circuit 2 (1-2), and the clock pulse frequency conversion circuit (1-3) are as shown in FIG. 3 of (a), (b), and (c)
In accordance with a clock switching signal 1b from a system controller (not shown) in the liquid crystal image display device, which indicates which of the two image display modes is to be selected, the changeover switch (1-4) is switched to select the selected clock. The pulse is output to the control circuit (1-5).

From the control circuit (1-5), a sampling pulse created based on the input clock pulse is input to the liquid crystal drive circuit. In the video drive circuit, the sampling pulse is sent to the sample hold circuit (1-7) through the shift register (1-6), the video signal 1a input from the video amplifier circuit (not shown) is sampled, and the sampling is performed. The generated video data is sent to each picture element of the liquid crystal panel (1-9) via the output buffer circuit (1-8), and the liquid crystal panel (1-9)
The video is displayed at.

The clock pulse frequency conversion circuit (1-
3) has a configuration as shown in FIG. Frequency f2 output from the clock pulse generation circuit 2 (1-2)
Is input to the multi-phase delay circuit (4-1) as the reference clock pulse 4a. As shown in FIG. 3, the multi-phase delay circuit (4-1) has a structure in which delay elements having the same delay time are connected in cascade for the required number of phases and their respective outputs are taken out. The pulse signal output by multi-phaseing the reference clock pulse in the multi-phase delay circuit (4-1) is input to the phase selection changeover switch (4-2).

In the phase selection changeover switch (4-2), the number of pulses in one horizontal scanning period of the video signal is not changed by the selection signal from the phase selection signal generating circuit (4-3) The clock pulse signal 4b converted so as to have a plurality of frequencies is output.

Next, details of the clock pulse frequency conversion circuit (1-3) will be described with reference to FIG. Here, for the sake of explanation, it is assumed that the input reference clock pulse is used in 10 phases and the number of clocks in one horizontal cycle of the video signal is simplified to 20 clocks.

First, the input reference clock pulse is multiphased by the delay line (6-1). Delay line (6
The configuration of -1) is also as shown in FIG. 3, and here, as an example, a case is shown in which 10 delay elements are provided for 10-phase conversion. The delay time for one delay element is a value obtained by dividing the cycle of the input reference clock pulse into 10 equal parts. The ten output signals of the delay line (6-1) are input to the line selector 1 (6-2) and the line selector 2 (6-3), respectively.

Each line selector 1 (6-2), 2 (6-
As the output of 3), the signal of one line selected by the 4-bit selector signal of S0 to S4 is output.
The output signals 6a and 6b of the two line selectors 1 (6-2) and 2 (6-3) are pulse edge detectors (6-4).
Each of the rising edges is detected to generate a narrow pulse, and the added signal 6c is output. The flip-flop (6-5) divides the signal to obtain an output clock signal 6d having a duty ratio of 50%.

The other circuits are for creating a select signal for obtaining a desired clock signal, and two similar signal processing circuits are provided for obtaining an output signal with a duty ratio of 50%.
It has a system. In FIG. 4, the part with 1 in the circuit name is for forming the rising edge of the output pulse signal, and the part with 2 is for forming the falling edge of the output pulse signal.

In order to generate a select signal for selecting the output line of the line selector 1 (6-2) and the line selector 2 (6-3), the output signal 6 of each line selector is generated.
The a and 6b pulses are counted by the clock counter 1 (6-6) and the clock counter 2 (6-11), and the count value here is one horizontal cycle of 20 clocks, and therefore the 5-bit signals 6e and 6i. Is output as.

Output signals 6e and 6i of the clock counter 1 (6-6) and the clock counter 2 (6-11) are input to the data generator 1 (6-7) and the data generator 2 (6-12). . Each of the data generator 1 (6-7) and the data generator 2 (6-12) can be composed of a ROM (read only memory) or the like, and a line (selecting an output signal from the clock counter as an address signal) It outputs a data signal related to the (phase) interval. From one of the data generators 1 (6-7), data indicating an even line interval (the number of selected phase intervals) to be selected by the line selector 1 (6-2) to form the rising edge of the output pulse signal is output. The other data generator 2 (6-12) outputs data indicating the line interval to be selected by the line selector 2 (6-3) to form the falling edge of the output pulse signal.

FIG. 5 is an explanatory diagram of a timing example of signals of respective parts of the clock pulse frequency conversion circuit. The actual data contents are the selection interval 1 and the selection interval 2 shown in the lower part of FIG. The selection interval 1 is a value set in advance for a desired screen display, and the set value changes if the screen display state is changed. The screen display state corresponding to the values shown in FIG. 5 has the expansion rate shown in Table 1 below.

[0046]

[Table 1]

The selection interval 2 is the average value of the previous selection interval value and the next selection interval value in the selection interval 1. The line interval represents the phase difference (delay amount) between the signal of the currently selected line and the signal of the next selected line. Here, the input reference clock is multiphased into a 10-phase signal. Therefore, if the phase interval is 10 phases, one cycle is delayed.

Output signals 6f and 6j from the data generator 1 (6-7) and the data generator 2 (6-12) are added by the adder 1
(6-8), select signals 6g and 6 indicating the selected line in the current line selector in the adder 2 (6-13)
k is added to generate select signals 6h and 6l for designating the line to be selected next. The number of lines that can be selected is 1
Since it is 0 line, these adders are also decimal adders.

The select signal sent to the line selector 1 (6-2) and the line selector 2 (6-3) holds the data contents in the data latch 1 (6-9) and the data latch 2 (6-14). Data latch 1 (6-9),
The data latch 2 (6-14) is connected to the line selector 1 (6
-2), the data of the next select signal is latched at the falling edge of the output pulse of the line selector 2 (6-3), and the line to be selected is switched.

In the process of creating the select signal for instructing the output lines of the line selector 1 (6-2) and the line selector 2 (6-3), reset is always applied at the start point of one horizontal cycle of the video signal, and each part of the unit is reset. The output data also becomes the initial value. Data latch 1 and data latch 2 at reset
The desired output pulse signal can be obtained by setting the output data of (1) so that 0 phase and 3 phase are selected as in the selected phase 1 and the selected phase 2 shown in FIG.

Next, the operation of the clock pulse frequency conversion circuit according to the first embodiment will be described with reference to the timing chart of FIG. 5 (a partially enlarged view of FIG. 6). Figure 6
Then, the signals 6a to 6l and the clock pulse output CKOUT are shown in detail. Here, similarly to the setting in FIG. 4, it is assumed that the input reference clock pulse has 10 phases and is used.
The number of clocks in one horizontal cycle of the video signal is simplified to 20 clocks.

In FIG. 5, CK0 to CK9 are input reference clock pulses converted into 10-phase clock pulses having the same phase difference by a delay line. The phase difference between each phase is 10 cycles of the reference clock pulse.
The values are set so that they are equally divided.

In FIGS. 5 and 6, the two signals 6a and 6b are signals output from the line selector 1 and the line selector 2 as the signals of the lines designated by the select signals S0 to S4, respectively.

At this time, depending on the phase difference between the previous line and the next line selected by the line selector, FIG.
As shown in the time chart, at the time of switching the selection at the falling edge of the previous selection line output signal, if the Hi level part of the next selection line comes, the selection line is switched to the Lo level for a moment, and immediately after that the Hi level part. Occurs, a rising edge is formed here, and the pulse including the rising edge is output erroneously where a pulse including the rising edge is originally output. Therefore, similarly, FIG. The circuit shown in is provided at the output of the line selector.

The circuit of FIG. 7B triggers the M / M (monostable multivibrator) at the falling edge of the pulse signal of the selected line, and rather than the Lo state which transiently occurs at the time of line selection switching. A slightly wider negative pulse is created and used as a reset signal for the F / F (flip-flop). On the other hand, the F / F data input is fixed to the Hi level, and the line selected pulse signal is used as the clock input, so that the line selection pulse signal rises to the Hi level at the rising edge and the line selection pulse signal falls. At the edge, by resetting with the M / M output signal generated in synchronization with it, it becomes Lo level, and it becomes possible to obtain the pulse signal having the phase difference as set.

The signal 6c is narrowed by detecting the rising edges of the output signals 6a and 6b of the line selector 1 (6-2) and the line selector 2 (6-3) in the pulse edge detector (6-4). Pulse signal, and they are added to form a single system signal.

The signal 6d is obtained by dividing the frequency of the signal by the flip-flop (6-5) to form a clock pulse output signal having a desired duty ratio of 50%.

The two signals 6e and 6i are 5-bit data obtained by counting the number of rising edges of 6a and 6b after resetting, and the numerical values in FIGS. 5 and 6 represent the data values. The arrow indicates the period during which the data value is output.

The two signals 6f and 6j are the same as the signal 6e.
And 6i for each data value of data generator 1 (6-
7), the line selector 1 (6-2) and the line selector 2 (6-, which are output from the data generator 2 (6-12).
It is a data value indicating the selected phase interval for designating the line to be selected next in 3).

Two signals 6g and 6k are output from the data latch 1 (6-9) and the data latch 2 (6-14), the line selector 1 (6-2) and the line selector 2 respectively.
The select signal (6-3) is a data value indicating the current select line.

The two signals 6h and 6l are added to the adder 1 (6
-8), which is a data value output from the adder 2 (6-13) and input to the data latch 1 (6-10) and data latch 2 (6-14), which indicates the line to be selected next.

Each of the data 6f, 6g, 6h, 6j, 6k, 6l is a 4-bit signal, and the data values thereof are shown in FIG.
The numerical values shown in FIG. 6 are obtained. The arrows in FIGS. 5 and 6 indicate the period during which the data value is output.

Further, as Comparative Example 1 , the clock pulse frequency conversion circuit may have a configuration as shown in FIG.

The clock pulse of frequency f2 output from the clock pulse generation circuit 2 (1-2) is input to the PLL oscillator (14-1) as the reference clock pulse 14a. Clock pulse P output from the PLL oscillator
(14b) is input to the fixed frequency dividing circuit (14-2), and the output signal 14c that has been frequency-divided at a constant frequency dividing ratio is input to the PLL oscillator (14-1) as a comparison signal. The clock pulse P multiplied by the reciprocal of is obtained.

The clock pulse P is a variable frequency dividing circuit (1
4-3), and the frequency-divided output 14d is output as a clock pulse signal 14d that is converted to have a plurality of frequencies stepwise without changing the number of pulses of the video signal in one horizontal scanning period. To be done.

The frequency division ratio of the variable frequency dividing circuit (14-3) is a count data generator (14-6) for generating count data 14g which is the number of clocks in each region where the frequency of the clock pulse output changes stepwise. ) Is selected by the data selector (14-5) by the data selection signal 14f for each area, and the division ratio switching control circuit (14-4) compares the output data 14h with the variable division circuit output 14d. Then, when they become equal to each other, it is determined by the reset signal 14e output to switch the frequency division ratio.

Next, details of the clock pulse frequency conversion circuit according to the first comparative example will be described with reference to FIGS.

Here, as an example, it is general that the image effective area in one horizontal scanning period of the image signal is divided into five areas, and the expansion / contraction form in the screen display is usually symmetrical.
Assuming that the expansion and contraction rates and the area lengths of the areas 1 and 5 and the areas 2 and 4 are the same, the number of clocks of the area 1 (area 5) is β, the clock pulse output frequency is 8f / 7, and the clock of the area 2 (area 4). Number, γ, clock pulse output frequency f, region 3 clock number δ, clock pulse output frequency 8f
/ 9. However, the frequency of the reference clock pulse input is f
I am trying.

In the blanking area outside the video effective area, the number of clocks from the H reset position, which is the starting point of one horizontal scanning period, to the area 1 is α, and the clock pulse output frequency is f.

The reference clock pulse 15a of frequency f is P
It is input to the LL oscillator (15-1) and the PLL oscillator (1
5-1) is a clock pulse P (1
5b) is output. In FIG. 9, the reset signal 15c of the counter B composed of a 4-bit binary counter is created by inputting the lower 3 bits BQ0, BQ1, and BQ2 of the count output to the NAND gate (15-4), and the division ratio is 8 To be set. And. Since the output signal BQ2 of the counter B is used as the comparison signal of the PLL oscillator (15-1), the clock pulse P has a frequency 8f which is 8 times the frequency of the reference clock pulse input 15a.

The clock pulse P (15a) is also input to the counter A which is composed of a 4-bit binary counter like the counter B. The reset signal 15d that determines the frequency division ratio of the counter A includes three NAND gates (1
5-5, 15-6, 15-7) and one AND gate (15-8). In this case, the NAND gate (15-5) is supplied with the second and third bits AQ1 and AQ2 of the counter A to generate a reset signal with a division ratio of 7, and the NAND gate (15-6) is supplied with the reset signal. Inputs the lower 3 bits AQ0, AQ1, and AQ2 to create a reset signal with a division ratio of 8, and the NAND gate (15-7)
AQ3 of the most significant bit is input to generate a reset signal having a frequency division ratio of 9, and is input to the counter A through the AND gate (15-8). AR is the choice of three division ratios
It is performed by three signals of 1, AR2, and AR3.

Since the frequency division ratio of the counter A is set to three types of 7, 8, and 9, the third bit AQ2 is used as the counter output and is used as the clock pulse output 15e. The clock pulse output 15e is also used as a signal for detecting the number of clocks in order to switch the frequency division ratio for each area, and therefore is also input to the clock counter (15-9).

The clock counter (15-9) is set to 1 first.
It is reset by the H reset signal 15h at the start point of the horizontal scanning period to start counting, and the count output 15f is input to the comparator (15-10). Comparator (15
-10) is a count data generator (1) including a register circuit for converting serial data from a system controller (not shown) in the set device into parallel data and outputting the parallel data.
5-12) output data 15j to the data selector (15
The data 15i selected in -11) is also input and compared with the previous count output 15f.

From the count data generator (15-12), as shown in FIG. 10, there are three kinds of frequencies of clock pulse output in the image effective area and four kinds including the blanking area. (Between H reset position and area 1), area 1 (area 5), area 2
(Area 4), four types of data corresponding to the clock numbers α, β, γ, and δ in the region 3 are output. Data selector (15
In -11), the data corresponding to each area is selected. The data selection of the data selector (15-11) can be controlled by four types of 2-bit control signals CQ0 and CQ1.

The comparator (15-10) compares the data value output from the data selector (15-11) with the count value output from the clock counter. OUT 15g is output to reset the clock counter (15-9), the up / down counter (15-13) counts it as a region switching signal, and CQ0 and CQ1 are output. CQ
0 and CQ1 serve as control signals for the data selector (15-11) and also AND gates (15-13, 15).
-15), INV (inverter) gate (15-14)
AR1, AR2, which is also input to, and selects a reset signal for switching the three frequency division ratios of the counter A (15-3),
Create AR3.

The outputs CQ0 and CQ1 of the up-down counter (15-13) are reset to the H-reset signal 15h at the start point of one horizontal scanning period, as shown in FIG. become. At this time, the counting direction of the up / down counter (15-13) is set to the up side.

A data value α indicating the number of clocks in the blanking area is output from the data selector (15-11) to the comparator (15-10), and the count value of the clock counter (15-9) is α. Then, the pulse signal COM for switching to the area 1 is output from the comparator (15-10). OUT is output, the clock counter (15-9) is reset to start a new count operation, the count value of the up-down counter (15-13) is incremented by 1, and the up-down counter (15-13) is incremented. ) Outputs CQ0 and CQ1 are in the Hi and Lo states. As a result, the data selector (15-1
In 1), the data value β indicating the number of clocks in the region 1 is selected and output to the comparator (15-10).

When the count value of the clock counter (15-9) becomes β, the pulse signal COM for switching to the area 2 from the comparator (15-10). OUT is output, the clock counter (15-9) is reset to start a new counting operation, the count value of the up-down counter (15-13) is further increased by 1, and the up-down counter (15- The outputs CQ0 and CQ1 of 13) are in the Lo and Hi states. As a result, the data selector (15-11) selects the data value γ indicating the number of clocks in the area 2 and outputs it to the comparator (15-10).

When the count value of the clock counter (15-9) becomes γ, the pulse signal COM for switching to the area 3 is output from the comparator (15-10). OUT is output, the clock counter (15-9) is reset to start a new counting operation, the count value of the up-down counter (15-13) is further increased by 1, and the up-down counter (15- The outputs CQ0 and CQ1 of 13) are in the Hi and Hi states. At this time, the counting direction of the up / down counter (15-13) is switched to the down side. As a result, the data selector (15-11) selects the data value δ indicating the number of clocks in the region 3 and outputs it to the comparator (15-10).

When the count value of the clock counter (15-9) becomes δ, the pulse signal COM for switching from the comparator (15-10) to the region 4, that is, the clock number data value to the region 2. OUT is output, the clock counter (15-9) is reset to start a new counting operation, and the up / down counter (1
The count value of 5-13) is decremented by 1, and the outputs CQ0 and CQ1 of the up / down counter (15-13) are in the Lo and Hi states. As a result, the data selector (15-11) selects the data value γ indicating the number of clocks in the area 2, that is, the area 4, and the comparator (15-
10) is output.

When the count value of the clock counter (15-9) becomes γ, the pulse signal COM for switching from the comparator (15-10) to the region 5, that is, the clock number data value to the region 1. OUT is output, the clock counter (15-9) is reset to start a new counting operation, and the up / down counter (1
The count value of 5-13) is further decreased by one, and the output CQ0, C of the up-down counter (15-13) is decreased.
Q1 is in a Hi or Lo state. As a result, the data selector (15-11) selects the data value β indicating the number of clocks in the area 1, that is, the area 5, and the comparator (15
-10) is output.

When the count value of the clock counter (15-9) becomes β, the pulse signal COM for switching to the blanking area is output from the comparator (15-10).
OUT is output, and the up / down counter (15-1
The count value of 3) is further decreased by 1 and the output C
Q0 and CQ1 are in the Lo and Lo states. After that, the blanking area is not displayed on the screen. Therefore, even if the data value of the clock number from the data selector (15-11) is not specified, the H reset signal at the start point of the next horizontal scanning period is input. Up-down counter (1
If the output state of 5-13) is maintained, there is no problem in operation.

CQ of output of comparator (15-10)
0 and CQ1 are also used to create AR1, AR2, and AR3 that control switching of the reset signal that determines the division ratio of the counter A.

AR1 in which the counter A (15-3) is a frequency-dividing counter is C by an AND gate (15-13).
Obtained as an AND output of the inverted signals of Q0 and CQ1,
This division ratio is selected in regions 1 and 5 of 0.
The clock pulse output is multiplied by 8 by the PLL oscillator (15-1) and divided by 7 by the counter A (15-3).
The signal has a frequency of 8f / 7. Areas 1 and 5 are the start and end of the video effective area, and are the left and right edges on the screen, and this area is the area where the original signal is expanded.

AR3, which uses the counter A (15-3) as a divide-by-9 counter, is C by an AND gate (15-15).
It is obtained as an AND output of Q0 and CQ1, and this frequency division ratio is selected in the region 3 of FIG. The clock pulse output is multiplied by 8 by the PLL oscillator (15-1), and the counter A
Since the frequency is divided by 9 in (15-3), the signal has a frequency of 8f / 9. The area 3 is at the center of the effective image area and is also the central portion on the screen, and this portion is an area where the original signal is compressed.

The AR2, which uses the counter A (15-3) as a divide-by-eight frequency counter, uses the INV gate (15-14).
It is obtained as an inverted signal of CQ0, and this frequency division ratio is selected in the regions 2 and 4 and the blanking region of FIG. The clock pulse output is multiplied by 8 by the PLL oscillator (15-1) and divided by 8 by the counter A (15-3), so that it becomes a signal having the same frequency f as the reference clock pulse input. The areas 2 and 4 are located between the expanded areas of the areas 1 and 5 and the compressed area of the area 3, and this area is an area where the original signal is not compressed or expanded.

So far, the case where the clock pulse output is obtained by using the output of the clock pulse generation circuit 2 (1-2) of FIG. 1 as the reference clock pulse input has been described. Figure 11
FIG. 6 is an explanatory diagram of a clock pulse frequency conversion circuit according to Comparative Example 2 . The clock pulse generation circuit 1 (1-
For the signals that change the frequency in the video display area and the blanking area output from 1), if the circuit section that sets the frequency division ratio corresponding to those frequencies is provided, the clock pulse generation circuit 1 outputs the clock pulse. The signal output from can also be obtained, and the configuration at that time is shown in FIG.
As shown in. In the circuit configuration of FIG. 11, the reference clock pulse of the single clock pulse generation circuit (12-1) needs to be set by the division ratio setting circuit section in the clock pulse frequency conversion circuit (12-2). Convert to clock pulse with different frequency.

Up to this point, the liquid crystal panel (1-
9) The video signal to be displayed above has a region having multiple expansion / contraction ratios in the time axis direction within the horizontal scanning period, and even when the aspect ratio of the video signal and the display screen is different, the video is displayed in the full horizontal direction of the display screen. The embodiment of the liquid crystal display device capable of displaying has been described. Separately, the clock pulse generation circuit and the clock pulse frequency conversion circuit are used in the same manner as in the above embodiment, and in addition, an A / D converter circuit, a line memory, and a D / A converter circuit are used to display only on the liquid crystal panel. However, the second embodiment that enables display on a general television receiver or the like is not shown in FIG.
2 is a configuration block shown in FIG.

In FIG. 12, as in FIG. 1, the clock pulse generation circuit 1 (3-1) has a frequency f1 in the image display area.
Clock pulse of frequency f
The 1'clock pulse is switched and output to the subsequent selector switch (3-4).

The clock pulse generation circuit 2 (3-2) is
A switch (3-
Output to 4).

Clock pulse frequency conversion circuit (3-3)
Then, the clock pulse of the frequency f2 output from the clock pulse generation circuit 2 (3-2) is input, and using it as a reference pulse, the number of pulses in one horizontal scanning period of the video signal is not changed, and is gradually changed. A switch (3-) that switches the clock pulse converted into a pulse signal having a plurality of frequencies.
Output to 4).

The three clock pulses output from the clock pulse generation circuit 1 (3-1), the clock pulse generation circuit 2 (3-2) and the clock pulse frequency conversion circuit (3-3) are the same as those shown in FIG. ), (B), (c), the changeover switch (3) according to the clock changeover signal 3b from the system controller (not shown) in the image display device, which indicates which of the three image display forms is to be selected. Three
-4) is switched to output the selected clock pulse to the A / D converter circuit (3-5) and line memory (3-6).

The clock pulse generation circuit 2 (3-2)
The clock pulse of the frequency f2 output from is input to the line memory (3-6) and the D / A converter circuit (3-7).

The clock pulse output from the changeover switch (3-4) is used as a clock for the write system,
The clock pulse generation circuit 2 (3-) is used as the sampling clock signal of the / D converter circuit (3-5) and the write clock signal of the line memory (3-6).
The clock pulse of the frequency f2 output from 2) is used as the read system clock, and the read clock signal of the line memory (3-6) and the D / A converter circuit (3-
Video signal 3a which is used as the sampling clock signal of 7) and is input from the video amplifier circuit (not shown) to the A / D converter circuit (3-5) due to the difference in frequency between the write system clock and the read system clock. , And the processed video signal 3c is output from the D / A converter circuit (3-7). The video signal compression / expansion processing performed here has the same content as that described in the configuration of FIG. 1 above, and the screen form in which the processed output video signal is displayed on the television receiver or the like is also the same.

Further, the clock pulse frequency conversion circuit has the configuration shown in FIGS.
If a circuit unit for setting the frequency division ratio of the counter A is provided so as to output signals having frequencies corresponding to the frequencies f1 and f1 'of the output signal of the clock pulse generation circuit 1, the clock pulse generation circuit 1 outputs the clock pulse output. You can also get a signal,
The configuration at that time is as shown in FIG.

The data value of each part of the circuit set in the description of each of the above embodiments is not limited to one kind, and it depends on how the screen display is made.
It goes without saying that it will change.

[0097]

As is apparent from the above description, according to the invention of claim 1, for example, when a video signal with an aspect ratio of 3: 4 is displayed on a screen with an aspect ratio of 9:16, Even if the aspect ratios of the video display screen are different, the video signal to be displayed has a contracted part or an expanded part in the time axis direction within the horizontal scanning period so that there is little visual discomfort and the display screen fills the horizontal direction. It is possible to display images on the screen.

According to the first aspect of the present invention, a pulse signal of a plurality of phases for delaying the input pulse signal by a constant time is taken out by a configuration in which delay elements having a constant delay time are simply connected in series. With this configuration, the clock pulse frequency can be converted.

According to the second aspect of the present invention, a pulse signal having a predetermined ratio can be realized with a simple structure. According to the invention of claim 3, in a video display device of any display screen,
Even if the video signal and the video display screen have different aspect ratios, the video signal to be displayed has a reduced portion or an extended portion in the time axis direction within the horizontal scanning period, so that there is less visual discomfort and the horizontal display screen is displayed. It becomes possible to display the image in all directions.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a liquid crystal image display device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a clock pulse frequency conversion circuit according to the first embodiment.

FIG. 3 is a block diagram showing a configuration of a polyphase delay circuit.

FIG. 4 is a detailed circuit block diagram of the clock pulse frequency conversion circuit of FIG.

FIG. 5 is an explanatory diagram of a timing example of signals of respective parts of the clock pulse frequency conversion circuit according to the first embodiment.

6 is an explanatory diagram of a timing example shown by partially enlarging FIG.

FIG. 7 is an explanatory diagram of a line selector output unit of the clock pulse frequency conversion circuit according to the first embodiment, FIG.
Is a timing time chart, and (b) is a circuit diagram.

FIG. 8 is a diagram showing a clock pulse frequency conversion circuit according to a first comparative example .

9 is a diagram showing a clock pulse frequency conversion circuit according to Comparative Example 1. FIG.

FIG. 10 is a timing explanatory diagram of the clock pulse frequency conversion circuit according to the first comparative example .

11 is a block diagram of a liquid crystal image display device according to Comparative Example 2. FIG.

FIG. 12 is a block diagram of a video signal processing circuit according to a second embodiment of the present invention.

13 is a block diagram of a video signal processing circuit provided with the clock pulse frequency conversion circuit of FIGS. 8 and 9. FIG.

14A to 14C are diagrams showing display forms of video signals on a screen in three display modes, respectively.

15A to 15C are schematic diagrams showing a relationship between a clock pulse frequency and a display area on a liquid crystal panel.

FIG. 16 is a diagram showing an input / output relationship when a clock pulse is generated by FM modulation according to a conventional example.

FIG. 17 is a diagram showing an input / output relationship when a clock pulse is generated by FM modulation of a conventional example.

[Explanation of symbols]

(1-1) Clock pulse generation circuit (1-2) Reference clock pulse generation circuit (1-3) Clock pulse frequency conversion circuit (1-4) Switch for switching clock pulse (1-5) Control circuit (1-6) Shift register (1-7) Sample and hold circuit (1-8) Buffer circuit (1-9) Liquid crystal panel 1a Video signal 1b Clock switching signal

Claims (3)

(57) [Claims] 1. An image display device using liquid crystal, comprising: a liquid crystal drive circuit including a shift register, a sample hold circuit, and a buffer circuit; and a reference clock pulse generation circuit for outputting a reference clock pulse signal serving as the sample pulse. A clock pulse frequency conversion circuit for converting the input reference clock pulse signal into a pulse signal having a plurality of frequencies stepwise without changing the number of samples in one horizontal scanning period of the video signal, and a plurality of clock pulse systems. The clock pulse frequency conversion circuit has a delay element with a constant delay time connected in series, and the output of each delay element can be taken out so that the input reference clock pulse signal A multi-phase delay circuit that makes a pulse signal of a plurality of phases delayed in steps, and the multi-phase delay circuit Phase selection changeover switch for selecting a phase signal to be output from a plurality of phase pulse signals output from the channel, and a phase selection signal generation circuit for instructing which phase of the pulse signal is selected by the phase selection changeover switch And a liquid crystal image display device characterized by comprising a region having a plurality of expansion / contraction ratios in the time axis direction in the horizontal scanning period in the video signal displayed on the liquid crystal panel. 2. A phase selection signal generating circuit selects a pulse signal of a plurality of phases output from a multi-phase delay circuit as a pulse signal of a phase selected by a phase selection changeover switch with an even number of selected phase intervals. 2. The liquid crystal image display device according to claim 1, wherein the liquid crystal image display device is performed by using the selected phase interval number and a pulse signal of a phase corresponding to the phase interval number having a predetermined ratio. 3. A video signal processing circuit, comprising: a reference clock pulse generation circuit, an AD converter, a line memory, and a clock pulse frequency conversion circuit, wherein the reference clock pulse generation circuit outputs a reference clock pulse signal of a predetermined frequency. The clock pulse frequency conversion circuit has a fixed delay time.
Delay elements are connected in series and each delay element output
Input reference clock so that power can be extracted
Multi-phase pulse in which the pulse signal is delayed by a fixed time interval
The multi-phase delay circuit used as a signal and the output from the multi-phase delay circuit
The signal of the phase to be output from the multi-phase pulse signal
Phase selection switch to select and the phase selection switching
Indicate which phase of pulse signal to select with the switch
A phase selection signal generating circuit for changing the frequency of the clock pulse signal output from the reference clock pulse generating circuit without changing the number of samples in one horizontal scanning period of the video signal. And a pulse signal output from the clock pulse frequency conversion circuit.
By using the sampling clock signal of the D converter and the write clock signal of the line memory and the reference clock pulse signal as the read clock signal of the line memory, a plurality of expansion / contraction ratios in the time axis direction can be applied to the video signal in the horizontal scanning period. A video signal processing circuit for a video display device, characterized in that a region having the same is provided.