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JP3410259B2 - Manufacturing method of semiconductor device - Google Patents
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JP3410259B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JP3410259B2
JP3410259B2 JP26219095A JP26219095A JP3410259B2 JP 3410259 B2 JP3410259 B2 JP 3410259B2 JP 26219095 A JP26219095 A JP 26219095A JP 26219095 A JP26219095 A JP 26219095A JP 3410259 B2 JP3410259 B2 JP 3410259B2
Authority
JP
Japan
Prior art keywords
semiconductor
wafer
electrode
bump
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP26219095A
Other languages
Japanese (ja)
Other versions
JPH0982712A (en
Inventor
裕司 尾崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP26219095A priority Critical patent/JP3410259B2/en
Publication of JPH0982712A publication Critical patent/JPH0982712A/en
Application granted granted Critical
Publication of JP3410259B2 publication Critical patent/JP3410259B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251Changing the shapes of bumps
    • H10W72/01255Changing the shapes of bumps by using masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251Changing the shapes of bumps
    • H10W72/01257Changing the shapes of bumps by reflowing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、例えば半導体ウエハ(以下、これを単にウエ
ハと呼ぶ)の一面に複数形成された各半導体集積回路
(半導体IC)の各電極上に一括してバンプを形成する
際に適用して好適なものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, for example, on each electrode of each semiconductor integrated circuit (semiconductor IC) formed on one surface of a semiconductor wafer (hereinafter, simply referred to as a wafer). This is suitable when applied to collectively forming bumps.

【0002】[0002]

【従来の技術】従来、例えばベアチツプ実装用のICチ
ツプにおいては、ウエハと呼ばれる半導体の単結晶板の
一面に、所定パターンでエツジング、酸化及び又は不純
物注入等の所定処理を施すことにより複数の半導体IC
を形成し、これら各半導体ICの各電極上にバンプと呼
ばれる突起電極をそれぞれ形成した後、各半導体ICを
それぞれ個別に切り離すことにより形成されている。こ
の場合このようなICチツプの製造工程において、ウエ
ハに形成された各半導体ICの各電極上にそれぞれバン
プを形成する工程は、通常、図2(A)〜(C)に示す
以下の手順により行われている。
2. Description of the Related Art Conventionally, for example, in an IC chip for mounting a bare chip, a plurality of semiconductors are formed by subjecting one surface of a semiconductor single crystal plate called a wafer to a predetermined process such as edging, oxidation and / or impurity implantation. IC
Is formed, bump electrodes called bumps are formed on the respective electrodes of the respective semiconductor ICs, and then the respective semiconductor ICs are individually separated. In this case, in the process of manufacturing such an IC chip, the process of forming bumps on each electrode of each semiconductor IC formed on the wafer is usually performed by the following procedure shown in FIGS. 2 (A) to 2 (C). Has been done.

【0003】すなわちまず図2(A)に示すように、複
数の半導体ICが形成されたウエハ1の一面1A上に、
これら各半導体ICの各電極位置にそれぞれ対応させて
開口2Aが設けられたメタルマスク2を密着させ、又は
当該ウエハ1の一面1A上に各半導体ICの各電極位置
にそれぞれ対応して開口するようにパターニングしたフ
オトレジストからなるレジトス層3を積層形成する。次
いで図2(B)に示すように、このメタルマスク2又は
レジスト層3の各開口2A、3Aをそれぞれ介して露出
する各半導体ICの各電極上に、蒸着法又はめつき法を
用いてバンプ用の金属材(以下、これをバンプ金属材と
呼ぶ)を所定の厚みに堆積させることによりバンプ金属
層4を形成する。
That is, first, as shown in FIG. 2A, on one surface 1A of a wafer 1 on which a plurality of semiconductor ICs are formed,
The metal mask 2 provided with the openings 2A corresponding to the respective electrode positions of the respective semiconductor ICs is brought into close contact, or the one surface 1A of the wafer 1 is opened corresponding to the respective electrode positions of the respective semiconductor ICs. Then, a resist layer 3 made of a photoresist that has been patterned is laminated. Then, as shown in FIG. 2B, bumps are formed on the electrodes of the semiconductor ICs exposed through the openings 2A and 3A of the metal mask 2 or the resist layer 3 by vapor deposition or plating. The bump metal layer 4 is formed by depositing a metal material (hereinafter referred to as a bump metal material) for a predetermined thickness.

【0004】続いてメタルマスク2又はレジスト層3を
ウエハ1の一面1A上から除去し、この後当該各半導体
ICの各電極上に形成した各バンプ金属層4を加熱溶融
する。これによりウエハ1に形成された各半導体ICの
各電極上に、図2(C)に示すような球形状のバンプ5
を形成することができる。
Subsequently, the metal mask 2 or the resist layer 3 is removed from the one surface 1A of the wafer 1, and then each bump metal layer 4 formed on each electrode of each semiconductor IC is heated and melted. As a result, spherical bumps 5 as shown in FIG. 2C are formed on the electrodes of the semiconductor ICs formed on the wafer 1.
Can be formed.

【0005】[0005]

【発明が解決しようとする課題】ところでこのような従
来のバンプ形成方法では、メタルマスク2又はレジスト
層3の各開口2A、3Aが全て同じサイズで形成されて
いる。ところがこのようなバンプ形成方法において、ウ
エハ1の一面1A上にバンプ金属材を堆積させる方法と
して蒸着法を用いる場合には、ウエハ1に形成された各
半導体IC部の各電極間において蒸着装置の蒸発源まで
の距離に差があるために、まためつき法を用いる場合に
は、ウエハ1の一面1A内における抵抗分布のばらつき
のために、最終的に各半導体ICの各電極上にそれぞれ
形成されるバンプ5の高さに±10〔%〕以上のばらつき
が生じる問題があつた。
By the way, in such a conventional bump forming method, all the openings 2A and 3A of the metal mask 2 or the resist layer 3 are formed in the same size. However, in such a bump forming method, when the vapor deposition method is used as a method of depositing the bump metal material on the one surface 1A of the wafer 1, the vapor deposition apparatus is provided between the electrodes of the semiconductor IC portions formed on the wafer 1. When the fold method is used because of the difference in the distance to the evaporation source, the resistance distribution in the one surface 1A of the wafer 1 is varied, so that the electrodes are finally formed on each electrode of each semiconductor IC. There is a problem that the height of the bumps 5 to be formed varies by ± 10% or more.

【0006】このため従来ではこのようなバンプ5の高
さのばらつきを解消するために、蒸着装置やめつき装置
の構造を工夫してはいるものの、このばらつきを完全に
は吸収しきれず、問題の解決策としては未だ不十分であ
つた。またこのようなバンプ5の高さのばらつきは、ウ
エハ1の口径が大きくなるほど(例えば6インチ以上)
大きくなる問題があつた。
For this reason, conventionally, in order to eliminate such a variation in the height of the bump 5, the structure of the vapor deposition apparatus or the plating apparatus has been devised, but this variation cannot be completely absorbed, which causes a problem. The solution was still inadequate. In addition, such a variation in the height of the bumps 5 increases as the diameter of the wafer 1 increases (for example, 6 inches or more).
There was a growing problem.

【0007】本発明は以上の点を考慮してなされたもの
で、各電極上に均一な高さのバンプを形成し得る半導体
装置の製造方法を提案しようとするものである。
The present invention has been made in consideration of the above points, and an object thereof is to propose a method of manufacturing a semiconductor device capable of forming bumps of uniform height on each electrode.

【0008】[0008]

【課題を解決するための手段】かかる課題を解決するた
め本発明においては、半導体ウエハの一面に形成された
各半導体集積回路の各電極上にバンプ用の金属材を堆積
させる工程において使用するマスクとして、各開口内に
堆積する金属材の体積が一定となるように各開口の大き
さがそれぞれ選定されたものを用いるようにした。すな
わちこのようなマスクを用いることによつて、各半導体
集積回路の各電極及びその周辺部上にそれぞれ一定の体
積で金属材を堆積させることができるため、これら各半
導体集積回路の各電極上に体積の等しいバンプを形成す
ることができる。
In order to solve such a problem, in the present invention, a mask used in the step of depositing a metal material for bumps on each electrode of each semiconductor integrated circuit formed on one surface of a semiconductor wafer. As the above, the size of each opening is selected so that the volume of the metal material deposited in each opening is constant. That is, by using such a mask, it is possible to deposit a metal material in a constant volume on each electrode of each semiconductor integrated circuit and its peripheral portion, and therefore, on each electrode of each semiconductor integrated circuit. Bumps having the same volume can be formed.

【0009】[0009]

【発明の実施の形態】以下図面について、本発明の一実
施例を詳述する。
BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.

【0010】図2(A)〜(C)との対応部分に同一符
号を付して示す図1(A)〜(D)は、実施例による半
導体装置の製造方法のうちの特にバンプの形成工程を示
すものであり、まずウエハ1に所定パターンでエツジン
グ、酸化及び又は不純物注入等の所定処理を施すことに
より当該ウエハ1の一面1Aに複数の半導体ICを形成
し、次いで当該ウエハ1の一面1A上に、図1(A)に
示すように、各半導体ICの各電極にそれぞれ対応させ
て開口10Aが設けられたメタルマスク10を密着さ
せ、又は各半導体ICの各電極にそれぞれ対応させて開
口するようにパターニングされたフオトレジストからな
るレジスト層11を積層形成する。
FIGS. 1A to 1D, in which parts corresponding to those in FIGS. 2A to 2C are designated by the same reference numerals, particularly bump formation in the method of manufacturing a semiconductor device according to the embodiment. First, a plurality of semiconductor ICs are formed on one surface 1A of the wafer 1 by performing a predetermined process such as edging, oxidation, and / or impurity implantation on the wafer 1 in a predetermined pattern, and then one surface of the wafer 1 is shown. As shown in FIG. 1A, a metal mask 10 having openings 10A corresponding to respective electrodes of each semiconductor IC is adhered onto 1A, or each electrode of each semiconductor IC is associated with each other. A resist layer 11 made of a photoresist that is patterned so as to have openings is laminated.

【0011】この場合メタルマスク10又はレジスト層
11の各開口10A、11Aの大きさは、ウエハ1の一
面1A上に蒸着法又はめつき法によりバンプ金属材を堆
積させる際に形成されるバンプ層に高さにばらつきが生
じることを考慮して、メタルマスク10又はレジスト層
11の開口10A、11Aの面積と、当該開口10A、
11Aを介してウエハ1の一面1A上に堆積されるバン
プ金属材の厚みとの積が常に一定(すなわち各開口10
A、11A内に体積するバンプ金属材の体積が一定)と
なるように選定するようにする。またこの工程終了まで
の間に、ウエハ1に形成された各半導体ICの各電極上
にバンプ金属材と濡れ性の良い金属からなる金属下地層
を一定面積で積層形成しておく。
In this case, the size of each opening 10A, 11A of the metal mask 10 or the resist layer 11 is such that the bump layer formed when the bump metal material is deposited on the one surface 1A of the wafer 1 by the vapor deposition method or the plating method. In consideration of variations in height, the area of the openings 10A, 11A of the metal mask 10 or the resist layer 11 and the opening 10A,
The product of the thickness of the bump metal material deposited on the one surface 1A of the wafer 1 via 11A is always constant (that is, each opening 10
The bump metal material in A and 11A has a constant volume. Further, by the end of this step, a metal base layer made of a metal having a good wettability with the bump metal material is laminated and formed on each electrode of each semiconductor IC formed on the wafer 1 in a predetermined area.

【0012】続いて図1(B)に示すように、これら各
半導体ICの各電極上に形成された金属下地層上に、メ
タルマスク10又はレジスト層11の各開口10A、1
1Aを介してバンプ金属材を蒸着法又はめつき法により
堆積させる。このときメタルマスク10又はレジスト層
11の各開口10A、11Aがそれぞれ上述のように大
きさが選定されているため、各半導体ICの各電極上に
それぞれ形成されるバンプ金属層12の体積(すなわち
メタルマスク10又はレジスト層11の各開口10A、
11A内に堆積されるバンプ金属材の体積)はウエハ1
の一面1A上においていずれも一定となる。
Subsequently, as shown in FIG. 1B, the openings 10A, 1A of the metal mask 10 or the resist layer 11 are formed on the metal underlayer formed on each electrode of each semiconductor IC.
A bump metal material is deposited through 1A by a vapor deposition method or a plating method. At this time, since the sizes of the openings 10A and 11A of the metal mask 10 or the resist layer 11 are selected as described above, the volume of the bump metal layer 12 formed on each electrode of each semiconductor IC (that is, Each opening 10A of the metal mask 10 or the resist layer 11,
The volume of the bump metal material deposited in 11A is the wafer 1
All are constant on one surface 1A.

【0013】次いでウエハ1の一面1A上からメタルマ
スク10又はレジスト層11を除去し、この後各半導体
ICの各電極及びその周辺部上に形成されたバンプ金属
層12を加熱溶融させる。これにより図1(C)及び図
1(D)に示すように、ウエハ1に形成された各半導体
ICの各電極14上に金属下地層15を介して球形状の
バンプ13を形成することができる。さらにこの後ウエ
ハ1を、各半導体ICをそれぞれ個別に切り離すように
分割する。これにより各電極14上にそれぞれ球形状の
バンプ13が形成されてなるICチツプを得ることがで
きる。
Next, the metal mask 10 or the resist layer 11 is removed from the one surface 1A of the wafer 1, and thereafter the bump metal layer 12 formed on each electrode of each semiconductor IC and its peripheral portion is heated and melted. Thereby, as shown in FIGS. 1C and 1D, the spherical bumps 13 can be formed on the electrodes 14 of the semiconductor ICs formed on the wafer 1 via the metal underlayer 15. it can. Further, thereafter, the wafer 1 is divided so that each semiconductor IC is individually separated. This makes it possible to obtain an IC chip in which the spherical bumps 13 are formed on the respective electrodes 14.

【0014】以上の構成において、この実施例による半
導体装置の製造方法では、上述のように各バンプ金属層
12の体積が一定となるようにメタルマスク10又はレ
ジスト層11の開口10A、11Aの大きさを選定して
いるため、各半導体ICの各電極14及びその周辺部上
に一定量のバンプ金属材を供給することができる。従つ
てこのような方法を用いることによつて、各バンプ13
の体積を一定にすることができる分、ウエハ1に形成さ
れた各半導体ICの各電極14上に均一な高さのバンプ
13を形成することができる。
With the above structure, in the method of manufacturing a semiconductor device according to this embodiment, the sizes of the openings 10A and 11A of the metal mask 10 or the resist layer 11 are set so that the volume of each bump metal layer 12 becomes constant as described above. Since the thickness is selected, a certain amount of bump metal material can be supplied onto each electrode 14 of each semiconductor IC and its peripheral portion. Therefore, by using such a method, each bump 13
The bumps 13 having a uniform height can be formed on the respective electrodes 14 of the respective semiconductor ICs formed on the wafer 1 by the amount that the volume can be made constant.

【0015】従つてこのようなバンプ形成方法を半導体
装置の製造工程に適用することによつて、各電極14上
に均一な高さのバンプ13が設けられた半導体装置を得
ることができる。さらにこの方法は、ウエハサイズに規
制されないため、例えば6インチ以上の口径の大きいウ
エハ1に形成された各半導体ICの各電極14上にバン
プ13を形成する場合にも適用することができ、この場
合にも各半導体ICの各電極上に精度良く均一な高さの
バンプ13を形成することができる。
Accordingly, by applying such a bump forming method to the semiconductor device manufacturing process, a semiconductor device having bumps 13 of uniform height provided on each electrode 14 can be obtained. Further, since this method is not restricted by the wafer size, it can be applied to the case where the bump 13 is formed on each electrode 14 of each semiconductor IC formed on the wafer 1 having a large diameter of 6 inches or more. Also in this case, the bumps 13 of uniform height can be accurately formed on each electrode of each semiconductor IC.

【0016】以上の構成によれば、ウエハ1に形成され
た各半導体ICの各電極14上にバンプ金属材を蒸着法
又はめつき法等により堆積させる際のマスクとなるメタ
ルマスク10又はレジスト層11の各開口10A、11
Aの大きさを、当該各開口10A、11A内に堆積され
るバンプ金属材の体積が一定となるようにぞれぞれ選定
するようにしたことにより、各半導体ICの各電極14
上に一定の体積のバンプ金属材を供給することができ、
かくして各電極14上に均一な高さのバンプ13を形成
することのできる半導体装置の製造方法を実現できる。
According to the above structure, the metal mask 10 or the resist layer serving as a mask for depositing the bump metal material on each electrode 14 of each semiconductor IC formed on the wafer 1 by the vapor deposition method or the plating method. 11 openings 10A, 11
The size of A is selected so that the volume of the bump metal material deposited in each of the openings 10A and 11A is constant, so that each electrode 14 of each semiconductor IC is selected.
Can supply a certain volume of bump metal material on top,
Thus, it is possible to realize a method of manufacturing a semiconductor device in which the bumps 13 having a uniform height can be formed on each electrode 14.

【0017】なお上述の実施例においては、ウエハ1に
形成された各半導体ICの各電極14上にバンプ金属材
を蒸着法又はめつき法等により堆積させる際のマスクと
して、メタルマスク10又はパターニングしたフオトレ
ジストからなるレジスト層11を適用するようにした場
合について述べたが、本発明はこれに限らず、要は、ウ
エハ1の一面1Aに形成された各半導体ICの各電極1
4にそれぞれ対応させて複数の開口が設けられ、かつ各
開口の大きさが各開口10A、11A内に堆積されるバ
ンプ金属材の体積が一定となるようにぞれぞれ選定され
ているものであるのならば、マスクとしてこの他種々の
ものを適用できる。
In the above embodiment, the metal mask 10 or the patterning is used as a mask for depositing the bump metal material on each electrode 14 of each semiconductor IC formed on the wafer 1 by the vapor deposition method or the plating method. The case where the resist layer 11 made of the photoresist described above is applied has been described, but the present invention is not limited to this, and the point is that each electrode 1 of each semiconductor IC formed on one surface 1A of the wafer 1 is
4, a plurality of openings are provided in correspondence with each other, and the size of each opening is selected so that the volume of the bump metal material deposited in each opening 10A, 11A is constant. If so, various other masks can be applied.

【0018】[0018]

【発明の効果】上述のように本発明によれば、半導体ウ
エハの一面に形成された各半導体集積回路の各電極上に
バンプ用の金属材を堆積させる工程に使用するマスクと
して、各開口内に堆積する金属材の体積が一定となるよ
うに各開口の大きさがそれぞれ選定されたものを用いる
ようにしたことにより、各半導体集積回路の各電極及び
その周辺部上にそれぞれ一定量のバンプ用の金属材を供
給することができ、かくして各電極上に均一な高さのバ
ンプを形成し得る半導体装置の製造方法を実現できる。
As described above, according to the present invention, the inside of each opening is used as a mask used in the step of depositing a metal material for bumps on each electrode of each semiconductor integrated circuit formed on one surface of a semiconductor wafer. Since the size of each opening is selected so that the volume of the metal material deposited on the substrate is constant, a constant amount of bumps is formed on each electrode and its peripheral portion of each semiconductor integrated circuit. It is possible to supply a metal material for use in the semiconductor device, and thus to realize a method for manufacturing a semiconductor device capable of forming bumps of uniform height on each electrode.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例による半導体装置の製造工程に適用する
バンプ形成方法の説明に供する断面図である。
FIG. 1 is a sectional view for explaining a bump forming method applied to a manufacturing process of a semiconductor device according to an embodiment.

【図2】従来の半導体装置の製造工程時に適用されてい
たバンプ形成方法の説明に供する断面図である。
FIG. 2 is a cross-sectional view provided for explaining a bump forming method that is applied in a conventional manufacturing process of a semiconductor device.

【符号の説明】[Explanation of symbols]

1……ウエハ、1A……一面、10……メタルマスク、
10A、11A……開口、11……レジスト層、12…
…バンプ金属層、13……バンプ、14……電極。
1 ... Wafer, 1A ... One side, 10 ... Metal mask,
10A, 11A ... Aperture, 11 ... Resist layer, 12 ...
... bump metal layer, 13 ... bump, 14 ... electrode.

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体ウエハに所定の処理を施すことによ
りその一面に複数の半導体集積回路を形成する第1の工
程と、 上記半導体ウエハの上記一面上に、各上記半導体集積回
路の各電極にそれぞれ対応させて複数の開口が設けられ
たマスクを配置する第2の工程と、 上記マスクの各上記開口をそれぞれ介して露出する各上
記半導体集積回路の各上記電極上にバンプ用の金属材を
堆積させることによりバンプ金属層をそれぞれ形成する
第3の工程と、 上記半導体ウエハの上記一面上から上記マクスを除去し
た後、各上記バンプ金属層を加熱溶融させることにより
各上記半導体集積回路の各上記電極上に各上記バンプ金
属層からなるバンプを形成する第4の工程と、 各上記半導体集積回路をそれぞれ切り離すように上記半
導体ウエハを分割する第5の工程とを具え、上記第2の
工程において使用する上記マスクとして、各上記開口内
に堆積する上記金属材の体積が一定となるように各上記
開口の大きさがそれぞれ選定されたものを用いるように
したことを特徴とする半導体装置の製造方法。
1. A first step of forming a plurality of semiconductor integrated circuits on one surface of a semiconductor wafer by subjecting the semiconductor wafer to a predetermined process, and to each electrode of each semiconductor integrated circuit on the one surface of the semiconductor wafer. A second step of arranging a mask provided with a plurality of openings corresponding to each other, and a metal material for bumps on the electrodes of the semiconductor integrated circuits exposed through the openings of the mask, respectively. A third step of forming bump metal layers by depositing, respectively, and removing the mask from the one surface of the semiconductor wafer, and then heating and melting each bump metal layer to form each of the semiconductor integrated circuits. A fourth step of forming bumps made of the bump metal layers on the electrodes, and dividing the semiconductor wafer so as to separate the semiconductor integrated circuits from each other. A mask including the fifth step, wherein the size of each opening is selected so that the volume of the metal material deposited in each opening is constant as the mask used in the second step. A method of manufacturing a semiconductor device, characterized in that
【請求項2】上記半導体ウエハは、口径が6インチ以上
でなることを特徴とする請求項1に記載の半導体装置の
製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor wafer has a diameter of 6 inches or more.
JP26219095A 1995-09-14 1995-09-14 Manufacturing method of semiconductor device Expired - Fee Related JP3410259B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26219095A JP3410259B2 (en) 1995-09-14 1995-09-14 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26219095A JP3410259B2 (en) 1995-09-14 1995-09-14 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPH0982712A JPH0982712A (en) 1997-03-28
JP3410259B2 true JP3410259B2 (en) 2003-05-26

Family

ID=17372330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26219095A Expired - Fee Related JP3410259B2 (en) 1995-09-14 1995-09-14 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP3410259B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4629912B2 (en) * 2001-05-25 2011-02-09 富士通セミコンダクター株式会社 Method of forming solder bump
JP5658442B2 (en) * 2009-06-02 2015-01-28 株式会社東芝 Electronic parts and manufacturing method thereof

Also Published As

Publication number Publication date
JPH0982712A (en) 1997-03-28

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