JP3411346B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device called a planar structure.

[0002]

2. Description of the Related Art A general MOS type semiconductor integrated circuit device is
Element isolation is performed by a field oxide film, and a source region and a drain region are formed by introducing impurities into a substrate by a self-alignment method using a gate electrode as a mask. Since one or two contacts are required for the source region and the drain region for each transistor, there is a drawback that high integration is hindered by the contact margin and the wiring pitch.

In order to solve the problem, a semiconductor integrated circuit device called a planar structure has been proposed (Japanese Patent Laid-Open Nos. 61-288464 and 63-9).
6953, etc.). In the planar structure, continuous diffusion regions for source regions of a plurality of MOS transistors and continuous diffusion regions for drain regions of a plurality of MOS transistors are formed on a substrate in parallel with each other, and an insulating film is formed on the substrate. A word line that intersects both diffusion regions is formed via the. The word line also serves as a gate electrode, a gate oxide film is formed on the substrate below the word line, and the substrate surface sandwiched between the source region and the drain region becomes the channel region, and the source region including the channel region is formed. The region, the drain region, the gate oxide film and the gate electrode form a memory transistor.

In the planar structure, it is not necessary to provide a field oxide film for element isolation, and since the source region and the drain region are shared by a plurality of transistors, the contact thereof can be several or tens of transistors. Only one is required, which is convenient for high integration.

The threshold voltage of each memory transistor is set by ion implantation to determine the ROM code. For example, when the memory transistor is an N-channel type, boron is injected into the channel region of the memory transistor to increase the threshold voltage, or it is not injected and the threshold voltage is kept low. When a word line of a memory transistor is selected and a voltage is applied, if the threshold voltage of the memory transistor is low, a current flows from the bit line (drain region) to the source region. If the voltage is high, no current flows, so the contents of the ROM are read by the sense circuit connected to the bit line.

[0006]

When further miniaturization is attempted in the planar structure, the miniaturization is restricted by the short channel effect due to the diffusion layers of the source region and the drain region. In a normal MOS transistor such as a peripheral transistor, the problem of the short channel effect can be avoided by making the diffusion layer an LDD structure.
In the planar structure, it is difficult to adopt the LDD structure due to its structure.

Since the drain region and the source region are formed by the diffusion layer formed on the substrate, the resistance value is high,
Further, it is conceivable that a junction is formed on the bottom surface and the side wall of the drain region and the source region to generate a parasitic capacitance, and the high resistance and the parasitic capacitance slow the operation speed. The present invention aims to further increase the operation speed of a memory device having a planar structure.

[0008]

According to the present invention, a first band-shaped layer having a two-layer structure composed of a silicon epitaxial layer and a drain impurity diffusion layer thereon is formed on a source region made of an impurity diffusion layer having a large area. A plurality of gate electrodes are formed in parallel with each other, a gate oxide film is formed on the side surface of the silicon epitaxial layer, and both impurity diffusion layers are covered with an insulating film. A word line of a second strip-shaped layer that also serves as a gate electrode is formed by a conductive layer that extends in a strip shape in a direction intersecting with one strip-shaped layer and is formed in parallel to each other, and the first strip-shaped layer and the word line are formed. Is a memory element, and in each memory element, at least the silicon epitaxial layer is divided or divided by the groove in the extending direction of the first strip-shaped layer according to the information to be stored. It has one of the states of the squid, a semiconductor memory device in which a channel is formed in the side surface of the silicon epitaxial layer of each intersection.

Further, according to the present invention, a plurality of first strip-shaped layers having a two-layer structure, which are composed of a silicon epitaxial layer and an impurity diffusion layer for drain thereabove, are provided in parallel on a source region formed of an impurity diffusion layer having a large area. A gate oxide film is formed on the side surface of the silicon epitaxial layer, both impurity diffusion layers are covered with an insulating film, and the gate oxide film intersects the first strip layer through the insulating film. The word line of the second strip-shaped layer also serving as the gate electrode is formed by the conductive layers formed in parallel with each other and extending in the strip-shaped direction, and the intersection between the first strip-shaped layer and the word line is formed in the memory element. In each memory element, at least the silicon epitaxial layer is divided by one or two or more grooves in the extending direction of the first strip-shaped layer according to the information to be stored. It is take one of the following states or not, a semiconductor memory device of multi-level channel on the side surface of the silicon epitaxial layer is formed on each intersection.

In a preferred embodiment, a refractory metal layer or refractory metal silicide layer is formed on the surface of the drain impurity diffusion layer. In another preferred embodiment, the word line is a refractory metal layer, a refractory metal silicide layer, or a conductive layer having a polycide structure in which refractory metal silicide is laminated on polysilicon.

The manufacturing method of the present invention manufactures a semiconductor memory device including the following steps (A) to (G). (A)
A step of forming a source region by introducing a first conductivity type impurity into a large area of a silicon substrate surface, (B) a step of forming a second conductivity type silicon epitaxial layer on a silicon substrate having a source region on the surface, (C) ) A first conductivity type silicon epitaxial layer is deposited on the second conductivity type silicon epitaxial layer, or a first conductivity type impurity is introduced into the surface of the second conductivity type silicon epitaxial layer to form a surface region of the first conductivity type silicon epitaxial layer. And (D) crossing portions of the second-conductivity-type silicon epitaxial layer and the first-conductivity-type layer thereabove in a plurality of strips parallel to each other and crossing the strip-shaped pattern formed later. A step of patterning a shape having a required number of grooves in the extending direction of the strip-shaped pattern at intersections required according to the information to be stored, (E) second A thermal oxidation step of forming a gate oxide film on the side surface of the electro-type silicon epitaxial layer and an oxide film on the other exposed surface, and (F) Polycrystalline silicon having a low resistance from the gate oxide film and the other oxide film. A step of forming a film or a conductive film having a refractory metal film or a refractory metal silicide film thereon, (G) patterning the conductive film into mutually parallel strips intersecting the strip pattern to form word lines Process.

In a preferred aspect of the manufacturing method of the present invention, in the step (C), a refractory metal film or a refractory metal silicide film is further formed on the first conductivity type layer on the second conductivity type silicon epitaxial layer. To do.

[0013]

1 is a schematic plan view of a memory portion showing an embodiment, and FIG. 2 is a sectional view of memory elements 6a to 6d in FIG. In FIG. 1, there are provided bit lines 2 on a silicon substrate, which are parallel to each other and extend in the vertical direction in the form of strips, and a plurality of parallel word lines 4 which extend in the form of strips in the direction intersecting the bit lines 2. And the intersections of the word lines 4 are memory elements 6a to 6d, respectively. The memory element 6b is divided into two regions by the groove in the extending direction of the bit line 2, the memory element 6c is divided into three regions by the groove in the extending direction of the bit line 2, and the memory element 6d is formed in the extending direction of the bit line 2. The groove is divided into four regions. The memory element 6a is not divided by such a groove.

A more detailed structure of the memory devices 6a to 6d will be described with reference to FIG. A source region 12 formed of an N-type diffusion layer is formed by introducing an N-type impurity such as arsenic or phosphorus into the surface of the P-type silicon substrate 10. Source area 1
Reference numeral 2 denotes a diffusion region serving as a source of the memory element, which is formed over a wide area in common with a plurality of memory elements without being patterned.

A P-type silicon epitaxial layer 14 is formed on the source region 12 in the direction perpendicular to the plane of the drawing in FIG. 2 and in the vertical direction in FIG. 1, and a P-type silicon epitaxial layer 14 is formed on the epitaxial layer 14. The N-type silicon layer 16 thus formed constitutes the bit line 2. A gate oxide film 18 is formed on the side surface of the epitaxial layer 14, and the source region 12 and the N-type silicon layer 16 are formed.
Is covered with an oxide film 20 thicker than the gate oxide film 18. The word lines 4 formed on the gate oxide film 18 and the oxide film 20 are formed as strip-shaped patterns that are parallel to each other in the direction intersecting the bit lines 2. For example, a polysilicon film whose resistance is reduced by introducing impurities is patterned. It has been transformed into Although not shown in the figure, an interlayer insulating film is formed so as to cover the word line 4 and the bit line 2, and a contact hole is opened in a necessary portion of the interlayer insulating film. The formed metal wiring is connected to the lower portion.

In the memory device 6a, the N-type silicon layer 16 of the bit line 2 and the epitaxial layer 14 thereunder are formed as one rectangular pattern. Memory element 6b
Then, the N-type silicon layer 16 and the epitaxial layer 1 thereunder
4 is formed by the groove 24 extending in the length direction of the bit line.
It is divided into two areas. Similarly, the N-type silicon layer 16 and the epitaxial layer 14 below the N-type silicon layer 16 serve as the memory element 6
The area c is divided into three areas, and the memory element 6d is divided into four areas.

In this embodiment, if a memory element is selected and read by the word line 4 and the bit line 2, the epitaxial layer 1 of the memory element is selected.
Channels are formed on both sides of 4 and a current i flows as indicated by an arrow. If the on-current flowing through one channel is i, the on-current 2i flows when the read memory element is 6a, and the read memory element is 6b.
Then the epitaxial layer 14 divided into two regions
Since a channel is formed on each side surface of, the on-current 4i flows. Similarly, in the memory element 6c, the on-current 6i,
An on-current 8i flows through the memory element 6d. The sense amplifier connected to the bit line 2 discriminates between these ON current differences.

In this embodiment, four kinds of data can be written in one memory element, and two kinds of data can be written in a normal memory element.
It is possible to store bits. Assuming that one memory element stores 1 bit as in the conventional memory element, only two types of memory elements, 6a and 6b, need be provided. Such embodiments are also included in the present invention.

FIG. 3 shows another embodiment using the memory element 6a as an example. Compared to the memory device 6a of FIG. 2, the word line 4 is formed of a single layer of low resistance polysilicon film in FIG. 2, whereas the word line 4 of FIG. 3 is formed of low resistance polysilicon film 4a. And a tungsten film 30 formed on top of this, which is a two-layer structure. The tungsten film 30 may be another refractory metal film such as molybdenum, or the word line may have a polycide structure by using a refractory metal silicide film such as tungsten silicide or molybdenum silicide. Further, the word line may be a single layer of high melting point metal film or high melting point metal silicide film. As described above, by forming the word line with a refractory metal film or a polycide structure, it is possible to reduce the resistance and it becomes suitable for high speed operation.

Although the bit line 2 is an N type silicon epitaxial layer in FIG. 2, the bit line 2 may be an N type diffusion layer in which N type impurities are introduced into the surface of the epitaxial layer 14 by ion implantation or the like. The bit line 2 may be formed by further laminating a refractory metal film such as tungsten or molybdenum or a refractory metal silicide film on the surface thereof. By stacking the refractory metal film and the refractory metal silicide film in this way, the resistance of the bit line 2 is reduced, which is convenient for high-speed operation.

Next, the manufacturing method of the embodiment shown in FIG. 2 will be described with reference to FIG. (A) N-type impurities such as arsenic and phosphorus are ion-implanted into the P-type silicon substrate 2 at 30 to 100 KeV to about 10 ¹⁴ to 10 ¹⁶ / cm ² to form an N type diffusion layer 12 to be a source region of a memory element. . Reference numeral 32 is a silicon oxide film formed on the surface of the silicon substrate before the ion implantation.

(B) After removing the silicon oxide film 32,
Silicon epitaxial layer 3 containing a low concentration of P-type impurities
4 is deposited, and a silicon epitaxial layer 36 containing a high concentration of N-type impurities is deposited thereon. Instead of depositing the silicon epitaxial layer 36, N-type impurities may be implanted into the surface of the epitaxial layer 34. The epitaxial layer 34 becomes a layer which will be patterned later to form a channel region, and the N-type silicon layer 36 becomes a bit line including a drain region. A refractory metal film or a refractory metal silicide film may be further deposited on the N-type silicon layer 36. Taking a case where a titanium silicide film is formed on the N-type silicon layer 36 as an example, a titanium film is deposited on the N-type silicon layer 36 and annealed in nitrogen, and then the unreacted titanium film is selectively removed. do it.

(C) Next, an N-type silicon layer 36 is formed by photolithography and etching (including a refractory metal film or refractory metal silicide film, if any).
And the epitaxial layer 34 thereunder are patterned to form the N-type silicon layer 16 and the epitaxial layer 14, respectively. This patterning requires a plurality of parallel stripes, and a groove in the extending direction of the stripe pattern is required at an intersection required to store information among intersections with a word line to be formed later. As many as possible.

(D) Next, a gate oxide film 18 is formed on the side surface of the epitaxial layer 14 by thermal oxidation, and the surfaces of the N-type silicon layer 16 and the N-type diffusion layer 12 are covered with a silicon oxide film 20 thicker than that. U 100 to 2 for the gate oxide film 18
If it is 50 Å, the silicon oxide film 20 is formed to a thickness of about 500 to 1000 Å by accelerated oxidation by diffusion of impurities.

(E) On the oxide films 18 and 20, a polysilicon film 38 containing an impurity which becomes a word line including a gate electrode is deposited. The polysilicon film 38 is a refractory metal film,
A polycide film structure in which a refractory metal silicide film is laminated on a refractory metal silicide film or a polysilicon film may be used.

After that, patterning is performed by photolithography and etching to form parallel word lines 4 extending in the direction orthogonal to the bit lines. further,
Then, an interlayer insulating film is deposited by a normal process, a contact hole is opened, a metal film is deposited, and patterned to form a wiring. Finally, a passivation film is formed.

[0027]

According to the present invention, since the side surface of the epitaxial layer of the memory element serves as the channel region, the channel length of the memorized element is determined by the film thickness of the epitaxial layer and does not hinder miniaturization. Moreover, since channels can be formed on both sides with respect to one gate electrode, it is possible to obtain an ON current that is twice as high as a normal ON current. Since the memory element has a vertical structure, a region on the drain side is unnecessary as compared with the planar structure described as the conventional example, and high integration can be achieved. Since the source has a large area, the resistance is reduced. Regarding capacitance, since the channel length is determined by the film thickness of the epitaxial layer, it is not necessary to thin the gate oxide film even if it is miniaturized.
It is possible to prevent an increase in capacity. Further, by forming a large-area source region, the peripheral length of the memory diffusion layer (source region) can be reduced and the junction capacitance can be reduced. The operation speed can be increased by reducing the resistance and the capacitance. Since the channel doping can be adjusted by the concentration of the epitaxial layer, defects are reduced as compared with the ion implantation method, and the concentration profile of the dopant is improved, so that a stable threshold voltage can be obtained. Since high energy injection for writing data is unnecessary, the process is simplified and damage to the device is reduced. If a multi-valued memory is formed by dividing the memory element in the present invention, higher integration can be achieved.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing a memory area of an embodiment.

FIG. 2 is a cross-sectional view showing each memory element in the embodiment of FIG.

FIG. 3 is a cross-sectional view showing one memory device in another embodiment.

FIG. 4 is a process cross-sectional view showing the manufacturing method of the embodiment.

[Explanation of symbols]

2 bit lines 4 word lines 6a to 6d memory device 10 Silicon substrate 12 N-type diffusion layer in source region 14 P-type silicon epitaxial layer 18 Gate oxide film 24 grooves dividing the memory element

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8246 H01L 27/112

Claims (6)

(57) [Claims] 1. A plurality of first band-shaped layers having a two-layer structure composed of a silicon epitaxial layer and an impurity diffusion layer for drain formed thereon are formed in parallel on a source region formed of an impurity diffusion layer having a large area. A gate oxide film is formed on a side surface of the silicon epitaxial layer, the impurity diffusion layers are covered with an insulating film, and the gate oxide film and the first insulating film intersect the first strip layer through the insulating film. A plurality of conductive layers extending in a striped shape in a direction parallel to each other are formed in parallel with each other to form a word line of a second strip-shaped layer that also serves as a gate electrode, and a crossing portion between the first strip-shaped layer and the word line is a memory element. In each memory element, at least the silicon epitaxial layer is divided or not divided by the groove in the extending direction of the first strip-shaped layer, depending on the information to be stored. Taking a state, the semiconductor memory device in which a channel is formed in the side surface of the silicon epitaxial layer of each intersection. 2. A plurality of first band-shaped layers having a two-layer structure composed of a silicon epitaxial layer and an impurity diffusion layer for drain formed thereon are formed in parallel on a source region formed of an impurity diffusion layer having a large area. A gate oxide film is formed on a side surface of the silicon epitaxial layer, the impurity diffusion layers are covered with an insulating film, and the gate oxide film and the first insulating film intersect the first strip layer through the insulating film. A plurality of conductive layers extending in a striped shape in a direction parallel to each other are formed in parallel with each other to form a word line of a second strip-shaped layer that also serves as a gate electrode, and a crossing portion between the first strip-shaped layer and the word line is a memory element. In each memory element, at least the silicon epitaxial layer is divided by one or two or more grooves in the extending direction of the first strip-shaped layer according to the information to be stored. It takes one of the following states or not,
A multi-value semiconductor memory device in which a channel is formed on the side surface of the silicon epitaxial layer at each intersection. 3. The semiconductor memory device according to claim 1, wherein a refractory metal layer or a refractory metal silicide layer is formed on the surface of the drain impurity diffusion layer. 4. The semiconductor memory according to claim 1, wherein the word line is a refractory metal layer, a refractory metal silicide layer, or a conductive layer having a polycide structure in which refractory metal silicide is laminated on polysilicon. apparatus. 5. A method of manufacturing a semiconductor memory device including the following steps (A) to (G). (A) A step of forming a source region by introducing impurities of the first conductivity type into a wide area of the surface of the silicon substrate, and (B) forming a second conductivity type silicon epitaxial layer on the silicon substrate having the source region on the surface. And (C) depositing a first conductivity type silicon epitaxial layer on the second conductivity type silicon epitaxial layer, or introducing a first conductivity type impurity into the surface of the second conductivity type silicon epitaxial layer to form a surface region thereof. As a first conductivity type layer, and (D) the second conductivity type silicon epitaxial layer and the first conductivity type layer above it in a plurality of parallel strips and intersecting this strip pattern formed later. The pattern having a required number of grooves in the extending direction of the band-shaped pattern is formed at the intersections required to store information among the intersections with the word lines. (E) thermal oxidation step of forming a gate oxide film on the side surface of the second conductivity type silicon epitaxial layer and an oxide film on the other exposed surface, (F) gate oxide film and other oxide film A step of forming a conductive film having a low resistance polycrystalline silicon film or a refractory metal film or a refractory metal silicide film on the polycrystalline silicon film from above, (G) the conductive films are parallel to each other and intersect the strip-shaped pattern The process of patterning into strips to form word lines. 6. The refractory metal film or refractory metal silicide film is further formed on the first conductivity type layer on the second conductivity type silicon epitaxial layer in the step (C). Of manufacturing a semiconductor memory device of.