JP3412876B2 - Buzzer drive - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buzzer drive device which sounds a buzzer for notifying the operation of the switch part when using a switch part which generates an operation signal only when operated like a so-called touch switch. Is.

[0002]

2. Description of the Related Art Conventionally, as an illumination device such as a learning stand, there has been provided an illumination device for turning on / off a lamp La by using a touch switch as shown in FIG.
The touch switch is a touch plate 1 made of a conductive material.
When a person touches the touch plate 11, the voltage generated between the ground and the person by the commercial AC power supply AC is divided by the resistors R ₁ and R ₂ and is compared with the reference voltage by the comparator CP ₁ . It has become. The reference voltage is obtained by dividing the DC power supply V _DD, which is separately provided, by resistors R ₃ and R ₄ . However, the resistance R ₁ ,
When the potential at the connection point of R ₂ exceeds the reference voltage, the output of the comparator CP ₁ becomes H level and the operation signal is generated. A capacitor C ₁ is connected in parallel to the resistor R ₂ so as to prevent malfunction due to high frequency noise.

Comparator CP forming the switch unit 1
_The operation signal output from ₁ turns on / off the switching element including the transistor Q ₁ via the flip-flop FF. The collector of the transistor Q ₁ - is between the emitter light emitting diode PE is a light emitting element of the photocoupler PC is connected in series, the output of the flip-flop FF becomes the transistor Q ₁ is turned on becomes H level, the light receiving element of the photocoupler PC Photo Triac P
T turns on. Photo Triac PT is a lamp La
Is connected in series, and this series circuit is connected to a commercial AC power supply AC. Therefore, the output of the flip-flop FF is inverted every time the operation signal is generated, and eventually the lamp La is
Each time a person touches the touch plate 11, lighting and extinction are alternately repeated.

By the way, when the touch plate 11 is touched by a person, it is possible to confirm that the operation signal is generated, so that when the touch plate 11 is touched, the operation confirmation buzzer Bz is activated for a short time. Has become. The buzzer Bz is composed of a piezoelectric element or the like, and is driven by an oscillation circuit 2 which is an astable multivibrator that outputs an audio frequency. The start / stop of the oscillator circuit 2 is controlled by the operation signal generated by the time limit circuit 6 in response to the operation signal.

That is, the time limit circuit 6 is a series circuit of a resistor Rd and a capacitor Cd connected between both ends of the power source V _DD , and a switching transistor Q ₃ which is connected in parallel to the capacitor Cd and is turned on / off by an operation signal. And a NOT circuit NT whose input end is connected to a connection point between the resistor Rd and the capacitor Cd. Since the transistor Q ₃ is turned on in the period of generation of the operation signal, the electric charge of the capacitor Cd is discharged, the output of the NOT circuit NT becomes H level. At this time, the oscillation circuit 2 operates and the buzzer Bz sounds. Further, after the operation signal is stopped, the transistor Q ₃ is turned off and the capacitor Cd is connected to the resistor Rd.
Since it is charged through the capacitor Cd, the period until the terminal voltage of the capacitor Cd exceeds the threshold voltage of the NOT circuit NT is N
The output of the OT circuit NT is kept at H level.
That is, if an operation signal is generated, at least the resistance Rd
And buzzer Bz for the time specified by capacitor Cd
Sounds.

[0006]

In the above-mentioned conventional structure, the minimum time for the buzzer Bz to ring is defined by the resistor Rd and the capacitor Cd, so that it is attempted to secure a sufficient ringing time for the buzzer Bz. Therefore, it is necessary to use a capacitor having a large capacitance as the capacitor Cd. For example, the minimum time for the buzzer Bz to ring is 0.5
Seconds, the capacitor Cd is 1 μF and the resistor Rd is 72
It is necessary to set it to 0 kΩ or the like, and in general, an electrolytic capacitor is used in order to secure the capacitance of this level.

However, since the electrolytic capacitor has a large volume and a relatively short life, there is a problem that it cannot be made small and have a long life. Further, in the circuit configuration shown in FIG. 11, since it is necessary to use the capacitor Cd having a large capacitance, it is inconvenient to integrate it as a gate array or a standard cell.
Therefore, rational integration cannot be achieved, which is one of the causes of hindering miniaturization.

An object of the present invention is to solve the above problems, and to provide a buzzer drive device capable of ensuring a ringing time of a buzzer without using a capacitor having a large capacity. is there.

[0009]

According to a first aspect of the present invention, drive signal generating means for outputting a rectangular wave of an audible frequency to sound a buzzer, switch means for generating an operation signal at the time of operation, and drive signal generating means. A frequency dividing means for frequency-dividing the output of the drive circuit until the period becomes perceptible, and a drive signal is generated when the drive signal generating means is started by an operation signal and the output of the frequency dividing means is inverted after the drive signal generating means is started. Latch means for stopping the means.

According to a second aspect of the present invention, in the first aspect of the present invention, the drive signal generating means outputs a clock signal for turning on / off a switching element of the inverter circuit, and an output of the clock circuit at an audible frequency. And a second frequency dividing means for performing frequency division until. According to a third aspect of the present invention, in the first aspect of the present invention, the time keeping means for counting the power-off time and the power supply for switching the load operation state each time the power is turned off when the power-off time is within a specified time. And an operation selection means for setting the load to a specified operation state when the cutoff state exceeds a specified time, and the timing means shares at least one of the drive signal generation means and the frequency division means. And

According to a fourth aspect of the present invention, in the third aspect of the present invention, a reference signal is generated which outputs a rectangular wave having an output frequency lower than that of the drive signal generating means so that the frequency of the output of the frequency dividing means becomes the specified time. Means are provided, and a clocking means is constituted by the reference signal generating means and the frequency dividing means. According to a fifth aspect of the invention, in the third aspect of the invention, a third frequency dividing means for dividing the output of the frequency dividing means until the cycle reaches the specified time is provided after the frequency dividing means, and a drive signal is generated. It is characterized in that the means, the frequency dividing means and the second frequency dividing means constitute a time measuring means.

[0012]

According to the structure of the invention of claim 1, the output of the drive signal generating means for outputting the rectangular wave of the audible frequency for ringing the buzzer is divided, and the output of the dividing means from the generation of the operation signal by the switch means. The buzzer ringing time is timed by delaying the time until the inversion of the buzzer by the latching means. Compared with the case where the buzzer ringing time is timed using a resistor and a capacitor, By eliminating the need for a large capacitor, it can be reasonably integrated into a circuit, which leads to miniaturization and high reliability.

According to the second aspect of the present invention, the clock signal for turning on / off the switching element of the inverter circuit is divided to obtain a rectangular wave for driving the buzzer. When provided, a part of the circuit for driving the buzzer and the inverter circuit can be shared, and the number of constituent parts can be reduced compared to the case where both are provided separately.

According to the third aspect of the invention, when a buzzer is provided in the load control device that switches the operating state of the load in accordance with the cutoff time of the power supply, a clocking means for measuring the cutoff time of the power supply is provided. At least one of the drive signal generation means and the frequency division means is shared, which leads to a reduction in the number of constituent parts. According to the structure of the invention of claim 4, the reference signal generating means for outputting a rectangular wave is provided separately from the drive signal generating means, and the output of the reference signal generating means is frequency-divided to measure the power-off time. Since the means is configured, the frequency dividing means can be shared by the load control device and the drive portion of the buzzer.

According to the fifth aspect of the present invention, the load control device and the drive portion of the buzzer share the drive signal generating means, and the frequency dividing means is further provided after the frequency dividing means. Therefore, sharing the drive signal generating means leads to a reduction in the number of constituent parts.

[0016]

【Example】

(Embodiment 1) In this embodiment, as shown in FIG. 1, a frequency divider circuit 3 for dividing the output of the oscillation circuit 2 is provided, and the frequency divider circuit 3 secures the ringing time of the buzzer Bz. The switch section 1 generates an operation signal each time a person operates it, and this operation signal is input to the set terminal of the latch circuit 4 formed of an RS flip-flop, and the oscillation circuit 2 is started through the latch circuit 4. Further, the output of the oscillation circuit 2 sounds the buzzer Bz and is also input to the frequency _dividing circuit 3 including a large number of flip-flops FF _{1 to} FF _n , and the frequency _dividing circuit 3 outputs 1/2 ⁿ (n is the frequency _dividing circuit 3). Of the flip-flops FF _{1 to} FF _n ). Here, the oscillation circuit 2 outputs a rectangular wave of an audible frequency, and the frequency dividing circuit 3 frequency-divides the output of the oscillation circuit 2 until the period becomes a perceptible time (for example, about 0.5 seconds). The output of the frequency dividing circuit 3 is input to the reset terminal of the latch circuit 4, and when the output of the frequency dividing circuit 3 is inverted after the oscillation circuit 2 is started, the latch circuit 4 is reset and the oscillation circuit 2 stops.

Therefore, when an operation signal is generated by the operation of the switch unit 1, the latch circuit 4 is set and the oscillation circuit 2 is started, and the buzzer Bz sounds, and even if the operation signal is stopped, the latch circuit 4 is activated. By maintaining the output of the circuit 4, the oscillator circuit 2 continues to operate.
Since the output of the oscillation circuit 2 is divided by the frequency dividing circuit 3, the output of the frequency dividing circuit 3 is inverted and the latch circuit 4 is reset when the time defined by the frequency dividing ratio has elapsed from the start of the oscillation circuit 2. Will be done. That is, the oscillation circuit 2
Stops and returns to its original state. Thus, the ringing time of the buzzer Bz is defined by the output frequency of the oscillator circuit 2 and the frequency division ratio of the frequency divider circuit 3, and this time is as stable as the output frequency of the oscillator circuit 2. Have.

Further, in the conventional configuration shown in FIG. 11, the buzzer Bz sounds at the time when the operation signal is generated, and the timed operation by the time circuit 6 is started at the time when the operation signal is stopped. Although the ringing time of the buzzer Bz was changed depending on the operation time of the section 1, the ringing time of the buzzer Bz is constant according to the configuration of this embodiment.

When this embodiment is applied to the conventional lighting circuit shown in FIG. 11, it becomes as shown in FIG. That is, the time limit circuit 6 in FIG. 11 is replaced by the frequency dividing circuit 3 and the latch circuit 4, and other configurations are shown in FIG.
The parts denoted by the same reference numerals have the same function. Here, the reset terminal of the flip-flop FF is provided to prevent malfunction when the power supply V _DD becomes unstable. Further, the oscillator circuit 2 includes three NAND circuits N
A _{1 to} NA ₃ and two resistors R ₅ and R ₆ and a capacitor C ₃
Consists of. However, when the output of the latch circuit 4 becomes H level, the output of the NAND circuit NA ₁ becomes L level, the capacitor C ₃ is discharged through the resistor R ₅ , and the resistor R ₆ is connected in the NAND circuit NA ₁ . The input also becomes L level. As a result, the output of the NAND circuit NA ₁ becomes H.
When the capacitor C ₃ becomes level and the capacitor C ₃ is charged and the terminal voltage of the capacitor C ₃ rises, the output of the NAND circuit NA ₁ becomes L level again and the above operation is repeated. In this way, the output of the NAND circuit NA ₂ is inverted with the time constant defined by the capacitor C ₃ and the resistors R ₅ and R _6, and the rectangular wave is output from the NAND circuit NA _3. .

In this embodiment, the number of parts is increased as compared with the configuration of FIG. 11, but the frequency dividing circuit 3 and the latch circuit 4 are different in the NA of the other flip-flop FF and the oscillation circuit 2.
Since it can be integrated with the ND circuits NA _{1 to} NA ₃ by a gate array or the like, the circuit configuration is suitable for integration by using the gate array or the like. Therefore, the size can be reduced as compared with the case of using a capacitor having a large capacity.

(Embodiment 2) In this embodiment, the buzzer driving device of Embodiment 1 is applied to a discharge lamp lighting device,
The discharge lamp lighting device, as shown in FIG. 4, performs full-wave rectification on a commercial AC power source AC by a rectifier RE such as a diode bridge, and smoothes the obtained DC power source by a capacitor C ₄ .
It is configured to be converted into a high frequency by the inverter circuit 5 and to supply the high frequency power to the discharge lamp (fluorescent lamp) DL. The inverter circuit 5 includes an inductor L ₁ ,
A switching element Q _{2 including} L ₂ , capacitors C ₅ and C ₆ , and an FET is provided, and a rectangular wave clock signal output from the clock circuit 12 is applied to the gate of the switching element Q ₂ via the drive circuit 13. The switching element Q ₂ is turned on / off. When the switching element Q ₂ is turned on / off, the resonance current flowing in the resonance circuit including the inductors L ₁ and L ₂ and the capacitor C ₅ is given to the discharge lamp DL, and the discharge lamp DL has the frequency of the clock signal. High frequency power is given.

The discharge lamp lighting device using such an inverter circuit 5 can be used regardless of the frequency of the commercial AC power supply, and the flicker of the discharge lamp DL can be prevented. Moreover, small inductors can be used as the inductors L ₁ and L ₂ , resulting in light weight and power saving. Here, in the above-described discharge lamp lighting device, since the clock circuit 12 that outputs a rectangular wave is provided, it is conceivable to use the clock circuit 12 as the oscillation circuit 2 in order to share a part of the circuit configuration. However, the output frequency of the clock circuit 12 is usually set to 40 kHz or more in consideration of noise given to peripheral devices and is not an audible frequency, so a frequency (several kHz) for ringing the buzzer Bz is obtained. As shown in FIG. 3, the output of the clock circuit 12 is reduced to the audible frequency by the frequency dividing circuit 14 as shown in FIG. Therefore, the same function as that of the oscillation circuit 2 in the first embodiment can be obtained by the clock circuit 12 and the frequency dividing circuit 14. The clock circuit 12 starts when an operation signal is input from the switch unit 1 at the time of stop, and stops when the next operation signal is input from the switch unit 1.

Whenever an operation signal is output from the switch unit 1, the timer circuit 15 performs a timed operation each time, and the frequency dividing circuit 14 operates during the timed operation to activate the buzzer B.
z sounds by the output of the frequency dividing circuit 14. Here, as the timer circuit 15, the frequency dividing circuit 3 (the output of the frequency dividing circuit 14 serves as an input) and the latch circuit 4 shown in the first embodiment are used, or the time limit circuit having the conventional configuration shown in FIG. 6
Can be used.

In the above embodiment, the output frequency of the clock circuit 12 is constant. However, when the discharge lamp DL is dimmed, the output frequency of the clock circuit 12 is made variable, so that the frequency dividing circuit 14 is responsive to the dimming level. It is possible to keep the ringing frequency of the buzzer Bz substantially constant by changing the frequency division ratio. Further, if the frequency division ratio of the frequency dividing circuit 14 is fixed, the ringing frequency of the buzzer Bz changes according to the dimming level, which serves as a guide for knowing the dimming level. Here, the buzzer Bz is not used only for confirming the operation of the switch unit 1, but a detection means for detecting the end of life of the discharge lamp DL, etc. is provided, and when the discharge lamp DL reaches the end of its life, the buzzer Bz sounds to discharge the discharge lamp. You may make it notify about the replacement time of DL. Other configurations are similar to those of the first embodiment. Further, the inverter circuit 5 is not limited to the above configuration, and it goes without saying that other configurations such as a half bridge system and a full bridge system may be used.

(Embodiment 3) This embodiment has a so-called two-wire load control function of switching on / off of a lamp by shutting off the power supply within a predetermined time, and when the power supply is on. It also has a function of sounding the buzzer Bz for a certain period of time. Both functions, there is being selected by the changeover switch SW ₁ to SW ₅ shown in FIG. 5, becomes the operation mode for turning on and off of the lamp according to power shutdown by selecting the contact a,
If the contact b is selected, the operation mode is set in which the buzzer Bz is sounded for a certain time when the power is turned on. Here, the changeover switches SW _{1 to} SW ₅ are interlocked with each other and may be manually operated, or the contacts a and b may be switched by another control signal using a semiconductor switch element or the like.

First, a part commonly used in each operation mode will be described. As shown in FIG. 5, commercial AC power supply A
C is the lamp La via the contact b of the changeover switch SW _1.
Is connected to a series circuit of a triac T and the triac T is turned on / off in response to turning on / off of the transistor Q ₁ via a photocoupler PC. That is, the photocoupler PC is the light emitting diode PE.
And a phototriac PT are optically coupled, and the light emitting diode PE is connected in series between the collector and the emitter of the transistor Q _1.
Is inserted between one end of the lamp La and the gate of the triac T. Therefore, when the transistor Q ₁ is turned on, the triac T is turned on and the lamp La is turned on.

By the way, the commercial AC power source AC has a resistor R
A series circuit of ₁₁ and R ₁₂ is connected via a switch SW,
Capacitor C ₁₁ for smoothing is connected in parallel to the voltage across the resistor R ₁₂ is the resistance R _12. Further, a series circuit of a dropper resistor R ₁₃ , a diode D ₁ and a zener diode ZD ₁ is connected to the commercial AC power supply AC via a changeover switch SW ₁ , and a capacitor C ₁₂ connected in parallel with the zener diode ZD _1. To obtain a DC power supply. This DC power supply serves as a power supply for the control circuit unit including the buzzer driving device. The voltage across the capacitor C ₁₂ is divided by the resistors R ₁₄ and R ₁₅ to become a reference voltage, and the comparator CP ₂ compares the potential at the connection point of the resistors R ₁₁ and R _{12 with} the reference voltage. Therefore, the comparator CP ₂ has the switch SW turned on and the commercial AC power source A.
When C is cut off, or when the switch SW is turned off while the commercial AC power supply AC is energized, the output is set to the L level. Here, the capacitor C ₁₂ is a commercial AC power source A
It has a capacity enough to supply power to the control circuit section even if C is cut off for a predetermined time. Also, changeover switch SW
The contact point a of ₁ is connected to the connection point of the switch SW and the resistor R ₁₁ .

The control circuit unit includes two oscillating circuit 2a having different output frequencies, and 2b, one of the oscillation circuit 2a selected by the changeover switch SW _2, a divider circuit 3 which divides the output of 2b The output of the frequency dividing circuit 3 is inverted and then input to one input terminal of the AND circuit AN ₁ .
The output frequency of the oscillator circuit 2b is an audible frequency, and the output frequency of the oscillator circuit 2a is set to a frequency lower than that of the oscillator circuit 2b. The other input terminal of the AND circuit AN ₁ is connected to the output of the comparator CP ₂ or the comparator C _2.
Either of the output of P ₂ and the inverted output of the NOT circuit NT ₂ is selected by the changeover switch SW ₃ and input. The output of the AND circuit AN ₁ is input to the reset terminal of the flip-flop FFa. The output of the comparator CP ₂ is input to the clock terminal of the flip-flop FFa, and the output of the flip-flop FFa is inverted every time the input to the clock terminal rises. The output terminal of the flip-flop FFa is connected to the contact a of the switch SW _4, contact b of the changeover switch SW ₄ is connected to the output of the comparator CP _2.

On the other hand, the output signal of the frequency dividing circuit 3 and the signal selected by the changeover switch SW ₃ are the NAND circuit N
It is inputted to the reset terminal of the latch circuit 4 which is an RS flip-flop through A ₄ . Since the signal selected by the changeover switch SW ₃ is input to the set terminal of the latch circuit 4, the non-inverted output of the latch circuit 4 is AN.
It is connected to one input end of the D circuit AN ₂ . The changeover switch SW ₅ is connected to the other input terminal of the AND circuit AN ₂ and is connected to the negative electrode of the capacitor C ₁₂ to keep the output at the L level and the state where the output of the oscillation circuit 2b is input is selected. To be done. Further, the inverted output of the latch circuit 4 is used for resetting the frequency dividing circuit 3. Next, the operation will be described with reference to FIGS. 6 and 7. Symbols s _{1 to} s ₁₃ in FIGS. 6 and 7 indicate signals of corresponding portions in FIG. First, referring to FIG. 6 will be described the case where the contact a of the changeover switch SW ₁ to SW ₅ is selected. In this state, the switch SW is normally kept on, and when the switch SW is turned off within a predetermined time, the lamp La is switched on / off. That is, since the switch SW is turned on, the output of the comparator CP ₂ becomes H level as shown in FIG. 6A, and the output of the AND circuit AN ₁ becomes L level as shown in FIG. 6D. Further, the output of the comparator CP ₂ is input to the clock terminal of the flip-flop FFa, and as shown in FIG.
The output of a becomes H level. That is, the transistor Q
₁ is turned on and the lamp La lights up. Since the output of the NOT circuit NT ₂ is at L level, the NAND circuit N 2
The output of A ₄ becomes H level as shown in FIG. 6 (g), the inverted output of the latch circuit 4 becomes H level as shown in FIG. 6 (h), and the frequency dividing circuit 3 is in the reset state.

On the other hand, when the commercial AC power source AC is cut off or the switch SW is turned off, the output of the comparator CP ₂ becomes H level, and the output of the NOT circuit NT ₂ becomes as shown in FIG.
As shown in (l), it becomes H level, and the output of the frequency divider circuit 3 also becomes H level.
Since it is at the level, the non-inverted output of the NAND circuit NA ₄ becomes the L level. Therefore, the reset state of the frequency dividing circuit 3 is released, and frequency division of the output of the oscillation circuit 2a is started.
Here, if the commercial AC power supply AC (switch SW) is restored within the time defined by the output frequency of the oscillation circuit 2a and the frequency division ratio of the frequency division circuit 3, the output of the frequency division circuit 3 is maintained at the H level. Since it is dripping, the output of the AND circuit AN ₁ maintains the L level, and the flip-flop FFa is not reset. Therefore, the output of the flip-flop FFa is inverted by the rising of the output of the comparator CP ₂ and L
The level becomes high, the transistor Q ₁ is turned off, and the lamp La is turned off. When the commercial AC power supply AC (switch SW) is cut off again and is returned within the specified time, the output of the flip-flop FFa becomes H level, so that the lamp L
a lights up.

When the commercial AC power supply AC (switch SW) is not cut off even after the stipulated time has passed after being cut off,
Since the output of the frequency dividing circuit 3 becomes L level as shown by the hatched portion in FIG. 6C, the output of the AND circuit AN ₁ becomes H level, and the flip-flop FFa becomes as shown in FIGS. 6E and 6F.
Is reset, the output becomes L level, and the lamp La is forcibly turned off. After that, when the commercial AC power supply AC (switch SW) is restored, the lamp La lights up. Here, when the contact a of the changeover switches SW _{1 to} SW ₅ is selected, the output of the AND circuit AN ₂ is at the L level, so the buzzer Bz does not ring.

By the way, when the contacts b of the changeover switches SW _{1 to} SW ₅ are selected, the voltage across the capacitor C ₁₂ is kept constant regardless of whether the switch SW is on or off. In this state, the switch SW is turned on.
The lamp La is turned on / off in conjunction with turning off. That is, when the switch SW is turned on, the output of the comparator CP ₂ becomes H level as shown in FIG. 7A, and the transistor Q ₁ as shown in FIG. 7F is passed through the changeover switches SW ₃ and SW ₄ . Since the base of is set to the H level, the lamp La lights up regardless of the output of the frequency dividing circuit 3. Also,
Similarly, if the switch SW is turned off, the comparator CP
The output of ₂ goes to L level and the transistor Q ₁ is turned off, so that the lamp La is turned off.

When the switch SW is turned on and the output of the comparator CP ₂ becomes H level, the latch circuit 4 is set and one input of the AND circuit AN ₂ becomes H level as shown in FIG. 7 (i). The output of the oscillation circuit 2b input through the changeover switch SW ₅ passes through the AND circuit AN ₂ and the buzzer Bz is sounded. Further, since the reset state of the frequency dividing circuit 3 is released by setting the latch circuit 4, the frequency dividing operation is started, and the output frequency of the oscillation circuit 2b is higher than that of the oscillation circuit 2a. As shown in (c), the output of the frequency dividing circuit 3 becomes L level in a relatively short time. That is, FIG.
As shown in (g), the output of the NAND circuit NA ₄ rises and the latch circuit 4 is reset. As a result, buzzer B
The ringing of z stops.

As is clear from the above operation, the output of the oscillation circuit 2b is used to ring the buzzer Bz, so that the output frequency of the oscillation circuit 2b is set to the audible frequency. The frequency division ratio of the frequency divider circuit 3 is set according to the relationship between the output frequency of the oscillator circuit 2b and the ringing time of the buzzer Bz. The output frequency of the oscillator circuit 2a is set according to the frequency division ratio of the frequency divider circuit 3. If the frequency division ratio is set in such a procedure, the frequency division ratio can be minimized without unnecessarily increasing it. Also,
The frequency dividing circuit 3 can be shared while enabling operation in two types of operation modes.

(Embodiment 4) In this embodiment, a so-called two-wire type load control function is provided in which the state of a load such as a lamp is switched stepwise in response to a short-term interruption of the commercial AC power supply AC. In addition, an example in which the buzzer sounds for a short time to notify the user when the load state is switched will be described. Commercial AC power supply AC is single-phase 2-wire, single-phase 3-wire,
Three phases may be used, and the operation of shutting off / returning can be performed by a wall switch or the like not shown.

As shown in FIG. 8, a power cutoff detection circuit 21 for detecting cutoff / return of the commercial AC power supply AC is provided. When the power cutoff detection circuit 21 detects the return after the cutoff of the commercial AC power supply AC, it is reset. Timer circuit 23 through circuit 22
Is reset. That is, the timer circuit 23 measures the elapsed time from the time when the interruption of the commercial AC power supply AC is detected, and uses a time constant circuit composed of a resistor and a capacitor or a frequency dividing circuit for dividing a clock signal. Consists of The time measured by the timer circuit 23 is input to the first time determination circuit 24 and the second time determination circuit 25, and the first time determination circuit 24 uses the commercial AC power supply A
It is determined whether or not the time from the cutoff of C to the return is within the specified time, and the second time determination circuit 25 limits the time from the return of the commercial AC power supply AC.

In the first time determination circuit 24, the operating state of the load LD is switched when it is determined that it is within the specified time, and the operating state of the load LD is returned to the initial state when it is determined that the specified time is exceeded. Here, FIG.
In the configuration shown in (1), the switching element S such as a relay or a thyristor connected in series to the load LD is turned on / off by the output of the first time determination circuit 24, and on / off can be selected as the operating state of the load LD. Although the initial state of the load LD is in the OFF state, when the load LD is a lamp or the like, the dimming step may be performed stepwise so that the load LD is in the operating state. For such control, the firing angle of the phase control or the operating frequency of the inverter circuit may be switched by the output of the first time determination circuit 24. When the first time determination circuit 24 generates an output that switches the operating state of the load LD, the timer circuit 23 is reset through the reset circuit 22.

The second time judgment circuit 25 is provided with a buzzer circuit 26 during a timed operation from the recovery after the commercial AC power supply AC is cut off.
To drive the buzzer. That is, when the operating state of the load LD changes, the buzzer sounds for a certain period of time to notify that the state of the load LD has changed. The control power supply circuit 27 supplies a direct-current power obtained by stepping down, rectifying, and smoothing the commercial AC power supply AC to each of the above circuits. The control power supply circuit 27 is configured to be able to supply power to each circuit for a period longer than the cutoff time of the commercial AC power supply AC when the operation state of the load LD is changed by cutting off the commercial AC power supply AC for a short time. Has been done. Also, in the above description,
Although the operation state of the load LD is switched by cutting off the commercial AC power supply AC by means not shown, a mechanical switch or a non-mechanical switch may be provided in the device. In this case, the buzzer sounds by resetting the reset circuit 22 with these switches.

FIG. 9 shows a specific example of the present embodiment, and the components having the same reference numerals as those of the configuration of the third embodiment shown in FIG. 5 have the same function. Further, this embodiment since not intended switching the operation mode, the changeover switch SW ₁ to SW ₅ is omitted. A crystal oscillating circuit is used as the oscillating circuit 2 so that the time can be accurately measured, and the frequency dividing circuit 3 uses a dividing ratio for measuring the interruption time of the commercial AC power supply AC as the buzzer ringing time. It is set to be larger than the frequency division ratio for time limit. That is, the oscillator circuit 2 and the frequency divider circuit 3 form the timer circuit 23.

When the commercial AC power supply AC is not cut off, the comparator C which constitutes the power supply cutoff detection circuit 21.
The output of P ₂ is at H level, and the second time determination circuit 2
AND circuit AN which outputs the logical product of the negation of the output of the latch circuit 4 and the output of the comparator CP _2.
The output of ₃ becomes H level (see FIG. 10 (j)). AN
Since the output terminal of the D circuit AN ₃ is connected to one input terminal of the OR circuit OR _1, the output of the OR circuit OR ₁ also becomes H level (see FIG. 10 (g)), the frequency dividing circuit 4 is reset Be kept in a state. At the other input terminal of the OR circuit OR ₁ ,
R set when the output of the comparator CP ₂ rises and reset when the output of the oscillator circuit 2 rises
The non-inverting output terminal of the S flip-flop FFb is connected. Here, the RS flip-flop FFb, the AND circuit AN ₃ , and the OR circuit OR ₁ constitute a reset circuit 22.

When the commercial AC power supply AC is cut off, the output of the comparator CP ₂ becomes L level, the output of the AND circuit AN ₃ becomes L level, and the reset state of the frequency dividing circuit ₃ is released. The frequency division of the output of the oscillation circuit 2 is started. When the cutoff state of the commercial AC power supply AC ends within the time defined by the output frequency of the oscillation circuit 2 and the frequency division ratio of the frequency dividing circuit 3 and the commercial AC power supply AC is restored,
Since the output of the frequency dividing circuit 3 (FIG. 10B) is still kept at the H level, the output of the frequency dividing circuit 3 and the comparator C
The output of the AND circuit AN ₄ (NOR circuit) as the first time determination circuit 24 which outputs the negative logical product of the output of P ₂ is maintained at the L level (FIG. 10 (c)). That is,
The flip-flop FFa having the output terminal of the AND circuit AN ₄ connected to the reset terminal is not reset, and the output state of the flip-flop FFa is inverted by the rise of the output of the comparator CP ₂ (FIG. 10 (d)). In this way, each time the commercial AC power supply AC is cut off, the on / off state of the transistor Q ₁ is reversed, and the on / off state of the lamp La is switched.

On the other hand, when the commercial AC power supply AC does not return within the specified time, the output of the frequency dividing circuit 3 becomes L level (see the right end portion of FIG. 10B).
The output of the circuit AN ₄ becomes H level, and the flip-flop circuit FFa is reset. Therefore,
The transistor Q ₁ is turned off and the lamp La is turned off, which is the initial state. After that, when the commercial AC power supply AC is restored, the reset state of the flip-flop FFa is released, but the lamp La is kept in the off state.

When the commercial AC power supply AC returns after the commercial AC power supply AC is cut off and the output of the comparator CP ₂ becomes L level, the RS flip-flop FF
b is once set, and the output of the RS flip-flop FFb becomes H level only for a period of about one pulse of the output of the oscillation circuit 2 (see FIG. 10 (h)). Therefore, the output of the AND circuit AN ₃ is L immediately after the commercial AC power supply AC is restored.
Although it is at the level (see FIG. 10 (j)), the frequency dividing operation is started immediately after the frequency dividing circuit 3 is once reset. The latch circuit 4 is set by the output of the comparator CP _{2, and} the output of the middle stage of the frequency dividing circuit 3 (see FIG. 10 (f)).
However, when the commercial AC power supply AC is once shut off and then restored, the latch circuit 4 is reset.
Is set to set the output to the H level, and then, when the output of the middle stage of the frequency dividing circuit 3 rises, the output becomes the L level (see FIG. 10 (e)). Therefore, the AND circuit AN ₂ in which the output of the latch circuit 4 is used as one input and the output of the oscillation circuit 2 is input to the other input, the AND circuit AN ₂ operates only when the output of the latch circuit 4 is at the H level. The output will be passed (see FIG. 10 (i)). As a result, the AND circuit AN is operated for a fixed time after the commercial AC power supply AC is restored.
Output of the oscillation circuit 2 is input to the buzzer circuit 26 through _2, so that the buzzer sounding. In short, the buzzer sounds for a fixed time after the commercial AC power supply AC is restored. Here, it goes without saying that the output frequency of the oscillation circuit 2 is set to the audible frequency.

In the configuration of the present embodiment, the oscillator circuit 2 is used in common for measuring the interruption time of the commercial AC power supply AC and the ringing of the buzzer, and a part of the frequency dividing circuit 3 is also used.
It is possible to reduce the number of constituent parts to achieve miniaturization and cost reduction. In particular, when making an integrated circuit, the chip area can be reduced and the number of output terminals can be reduced. Other configurations are similar to those of the third embodiment.

[0045]

According to the invention of claim 1, the output of the drive signal generating means for outputting a rectangular wave of an audible frequency for ringing the buzzer is divided, and the output of the dividing means is inverted from the generation of the operation signal by the switch means. The buzzer ringing time is timed by using the latching means to time the time, so a large-capacity capacitor is not required when compared with the case where the buzzer ringing time is timed using a resistor and a capacitor. Therefore, it has an advantage that it can be reasonably integrated into a circuit, and further leads to miniaturization and high reliability.

According to the second aspect of the invention, the clock signal for turning on / off the switching element of the inverter circuit is divided to obtain a rectangular wave for driving the buzzer. Therefore, when the buzzer is provided in the inverter circuit, the buzzer is used. There is an advantage that a part of the driving circuit and the inverter circuit can be shared, and the number of constituent parts can be reduced as compared with the case where both are provided separately.

According to the third aspect of the present invention, when a buzzer is provided in the load control device that switches the operating state of the load in accordance with the cutoff time of the power supply, the clocking means for measuring the cutoff time of the power supply is drive signal generating means. Since at least one of the frequency dividing means and the frequency dividing means is shared, there is an advantage that the number of constituent parts can be reduced. According to a fourth aspect of the invention, reference signal generating means for outputting a rectangular wave is provided separately from the drive signal generating means, and the time measuring means for counting the power-off time by dividing the output of the reference signal generating means is configured. Therefore, there is an advantage that the frequency dividing means can be shared by the load control device and the drive portion of the buzzer.

According to the fifth aspect of the present invention, the load control device and the drive portion of the buzzer share the drive signal generating means, and the frequency dividing means is further provided after the frequency dividing means. The sharing of the generating means has an effect of reducing the number of component parts.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment.

FIG. 2 is a circuit diagram showing a first embodiment.

FIG. 3 is a block diagram showing a second embodiment.

FIG. 4 is a circuit diagram of an inverter circuit used in a second embodiment.

FIG. 5 is a circuit diagram showing a third embodiment.

FIG. 6 is an operation explanatory diagram of the third embodiment.

FIG. 7 is an operation explanatory diagram of the third embodiment.

FIG. 8 is a block diagram showing a fourth embodiment.

FIG. 9 is a circuit diagram showing a fourth embodiment.

FIG. 10 is an operation explanatory diagram of the fourth embodiment.

FIG. 11 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1 Switch Unit 2 Oscillation Circuit 2a Oscillation Circuit 2b Oscillation Circuit 3 Dividing Circuit 4 Latch Circuit 5 Inverter Circuit 12 Clock Circuit 14 Dividing Circuit 21 Power Shutdown Detection Circuit 23 Timer Circuit 24 First Time Judgment Circuit 25 Second Time Judgment Circuit Bz Buzzer Q ₁ Switching element

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-55-106381 (JP, A) Actually open 3-29995 (JP, U) Actually open 58-60292 (JP, U) (58) Field (Int.Cl. ⁷ , DB name) G08B 3/10 G10K 9/12 105

Claims (5)

(57) [Claims] 1. A drive signal generating means for outputting a rectangular wave of an audible frequency to sound a buzzer, a switch means for generating an operation signal at the time of operation, and a length such that a cycle of the output of the drive signal generating means can be perceived. And a latching means for starting the drive signal generating means by the operation signal and stopping the drive signal generating means when the output of the frequency dividing means is inverted after the start of the drive signal generating means. A buzzer driving device characterized by being formed. 2. The drive signal generating means includes a clock circuit for generating a clock signal for turning on / off a switching element of an inverter circuit, and a second frequency dividing means for frequency-dividing an output of the clock circuit to an audible frequency. The buzzer drive device according to claim 1, wherein the buzzer drive device comprises: 3. A time measuring means for measuring a power-off time,
If the power-off time is within the specified time, the operation state of the load is switched every time the power is cut off, and if the power-off status exceeds the specified time, the load is set to the specified operation state. 2. The buzzer drive device according to claim 1, wherein the timekeeping means shares at least one of the drive signal generating means and the frequency dividing means. 4. A reference signal generating means for outputting a rectangular wave having an output frequency lower than that of the drive signal generating means is provided so that the output cycle of the frequency dividing means becomes the specified time, the reference signal generating means and the frequency dividing means. The buzzer driving device according to claim 3, wherein the means constitutes a time measuring means. 5. A third frequency dividing means is provided after the frequency dividing means to divide the output of the frequency dividing means until the cycle reaches the specified time, and a drive signal generating means, a frequency dividing means, and a second frequency dividing means are provided. 4. The buzzer driving device according to claim 3, wherein the frequency dividing means and the time measuring means are configured.