JP3415366B2 - POH termination processing apparatus, POH termination processing method, and pointer / POH termination processing apparatus in SDH transmission system - Google Patents

Description

Detailed Description of the Invention

(Technical field to which the invention belongs) Conventional technology Means for solving the problems to be solved by the invention (FIG. 1) Embodiment of the invention (A) Outline description of SDH transmission system (FIG. 2) (FIG. 10) (B) Outline explanation of POH termination processing (FIGS. 11 to 27) (B1) Termination processing of J1 and J2 bytes (FIGS. 11 to 1)
3) (B2) B3 byte termination processing (FIGS. 14 to 16) (B3) C2 byte termination processing (FIGS. 17 and 18) (B4) G1 byte termination processing (FIGS. 19 and 20) (B5) V5 byte termination processing (FIGS. 21 to 25) (B6) Performance monitor (PM) function (FIG. 26,
27) (C) Description of POH termination processing device (FIGS. 28 to 122) (C1) Overall configuration description of POH termination processing device (FIGS. 28 to 22)
(FIG. 40) (C2) Description of timing generation unit (FIGS. 41 to 59) (C3) Description of J1 / J2 byte termination processing unit (FIG. 60 to FIG. 60)
82) (C4) Description of B3 / V5 Byte Termination Processing Unit (FIG. 83)
(FIG. 100) (C5) Description of C2 / V5 Byte Termination Processing Unit (FIG. 101)
(FIG. 109) (C6) Description of G1 / V5 byte termination processing unit (FIG. 110)
~ Fig. 122) (D) Other effects of the invention

[0002]

TECHNICAL FIELD The present invention relates to SDH (Synchrono).
The present invention relates to a POH (path overhead) termination processing device, a POH termination processing method, and a pointer / POH termination processing device in a us Digital Hierarchy) transmission system.

[0003]

2. Description of the Related Art In SDH transmission technology, normally, two lines, a working line and a protection line, are set between transmission terminal equipments, and the receiving station checks the quality of the communication line of the working line and the protection line. Then, the communication line is appropriately switched from the regular line to the standby line in accordance with the degree of deterioration of the quality of the regular line.

For this reason, in the transmitting terminal device, the frame format of the multiplexed signal (considering the case of STM-1 frame) transmitted by the SDH transmission system and this STM
-1 TU multiplexed (mapped) in one frame-
The line quality is confirmed based on TU format signals such as 3, TU-2 and TU-12. Specifically, TU- multiplexed in the received STM-1 frame
3, BIP (Bit Interleaved P) for path error monitoring for POH in TU-2 or TU-12 signal
arity) operation and other various POH termination processing to detect the deterioration of the line quality,
A control signal for line switching is generated in TU-2 and TU-12 format units.

By the way, in the STM-1 frame, the TU
-3 is mapped to 3 channels at maximum, TU2 is mapped to 21 channels at maximum, and TU12 is mapped to 63 channels at maximum. Therefore, the above POH termination processing is independently performed by the number of channels corresponding to the signal size of the TU format signal. It needs to be done (in parallel). For this reason,
Normally, in the transmitting terminal device, H1 of the STM-1 frame is
The start position of the VC-4 format is detected by the pointer value of H2 byte, and this start position and TU-3, TU-
2, TU-12 multiplex setting information (mapping setting information)
The TU format signal multiplexed on the VC-4 is separated based on the
OH termination processing is being performed.

Therefore, when all the signals multiplexed in the STM-1 frame are TU-12, it is necessary to perform POH termination processing for 63 channels of TU-12.
Circuit for POH termination processing for up to 63 channels (PO
H termination processing device) is required.

[0007]

However, as described above, in the conventional SDH transmission technique, the TU format signal is separated from the STM-1 frame and the POH termination processing for each TU format signal is performed in parallel. The transmission terminal station device needs to be provided with POH termination processing devices having the same configuration for up to 63 channels, which causes a problem that the device scale and power consumption increase significantly.

The present invention was devised in view of the above problems, and performs the POH termination arithmetic processing as it is without separating the multiplexed signals transmitted by the SDH transmission system for each channel. An object of the present invention is to provide a POH termination processing device, a POH termination processing method, and a pointer / POH termination processing device in the SDH transmission method, which can significantly reduce the device scale and power consumption.

[0009]

FIG. 1 is a block diagram of the principle of the present invention. The POH termination processing apparatus shown in FIG. 1 is a signal in which a plurality of channel information transmitted by the SDH transmission system is multiplexed. POH terminating processing is performed on each of the channels, and a POH terminating arithmetic processing unit 1 common to each channel on which the POH terminating arithmetic processing is performed on this multiplex signal and the arithmetic result in the POH terminating arithmetic processing unit 1 are stored for each channel. Readable and writable storage unit 2 and back
POH timing signal serial generator (not shown)
Alternatively , it is configured with an address creating unit .

The POH termination processing device shown in FIG. 1 uses the stored information about the corresponding channel stored in the storage unit 2 when performing the POH termination calculation process on the multiplexed signal. By performing the POH termination arithmetic processing in the arithmetic processing unit 1 and storing the obtained POH termination arithmetic result in the storage area of the corresponding channel of the storage unit 2, the multiplexed signal is not separated for each channel and the POH is kept serial. It is designed to perform a terminal calculation process.

As a result, in the POH termination processing device described above, the multiplexed signal is not separated for each channel, and the P signal remains serial.
The OH termination arithmetic processing can be performed, and it is not necessary to provide a circuit for the POH termination arithmetic processing for each channel in the multiplex signal (the above claims 1, 2, 23, 24). In the POH termination processing device, the POH termination arithmetic processing unit 1 performs the POH termination arithmetic processing, and stores the stored information about the corresponding channel read from the storage unit 2 and the POH byte that performs the processing in the multiplexed signal. A latch section for temporarily storing data and data is provided, and this latch section is made to latch the storage information held in the storage section 2 and POH byte data for processing in the multiplexed signal at the POH detection timing. Then, the storage information necessary for the POH termination calculation processing is supplied to the POH termination calculation processing section 1 at a desired timing, so that the POH termination calculation processing section 1 operates only when necessary (claim). 3 ).

By the way, the above-mentioned POH termination arithmetic processing unit 1
May be configured as a J1, J2 byte serial termination processing unit that serially terminates the J1 byte and J2 byte included in the multiplexed signal. In this case, the storage unit 2
The operation result in the J1, J2 byte serial termination processing unit is stored for each channel, and the storage information is supplied to the J1, J2 byte serial termination processing unit.

As a result, in this POH termination processing device,
J1 byte [considering an STM-1 frame as a multiplexed signal, included in the POH of VC (Virtual Container) -3] has a termination processing and a low-order group signal size different from the multiplexed signal containing this J1 byte. The J2 byte termination processing included in the POH of the multiplex signal can be serially performed by the J1 and J2 byte serial termination processing section common to each channel (claim 4 ).

Therefore, concretely, the J1 and J2 byte serial termination processing section is configured to include the following sections. A multi-frame pattern serial detection unit that serially detects multi-frame patterns of J1 bytes and J2 bytes. A multi-frame pattern number serial control unit that serially controls the number of multi-frames of J1 byte and J2 byte.

.LOM (Loss of J1 byte and J2 byte
LOM serial detection unit that serially detects (of multiframe).・ J1 byte and J2 byte CRC (Cyclic Redundanc)
CRC serial detector that performs y check) detection serially.・ J1 byte and J2 byte TIM (Trace Indicator)
TIM serial detector that serially performs (mismatch) detection.

Then, in this case, the above-mentioned storage unit 2 performs each calculation in the above-mentioned multi-frame pattern serial detection unit, multi-frame pattern number serial control unit, LOM serial detection unit, CRC serial detection unit and TIM serial detection unit. The result is stored for each channel, and the storage information is supplied to the multi-frame pattern serial detector, the multi-frame pattern number serial controller, the LOM serial detector, the CRC serial detector, and the TIM serial detector. It

As a result, in the present POH termination processing device,
Various alarm information such as LOM, CRC, and TIM can be serially obtained by the J1 and J2 byte serial termination processing unit common to each channel.
5 ). In addition, the POH termination arithmetic processing unit 1 shown in FIG. 1 uses the BIP (B
It Interleaved Parity) termination processing and the above B3 byte and V5 byte BIPPM (BIP Performance Monitor)
May be configured as a B3, V5 byte serial termination processing unit that serially performs the termination processing of
The storage unit 2 stores the calculation result in the B3, V5 byte serial termination processing unit for each channel, and
It is configured to supply stored information to the 3, V5 byte serial termination unit.

As a result, in the present POH termination processing device,
B3 termination (operation) processing for B3 bytes (included in POH of VC-3 when STM-1 frame is considered as a multiplex signal) and signal size of low-order group different from the multiplex signal including this B3 byte Multiple signal PO with
BIP termination processing for V5 byte included in H,
It can be serially performed by the B3, V5 byte serial termination processing unit common to each channel.
6 ).

Therefore, specifically, the B3, V5 byte serial termination processing unit is configured to include the following units.・ BIP8 (Bit Interleaved Parit
y-8) A BIP8 arithmetic serial processing unit that performs arithmetic serially.・ BIP2 (Bit Interleaved Parit
y-2) A BIP2 arithmetic serial processing unit that serially performs arithmetic operations.

A BIP error selecting section for selecting a BIP error signal output from the BIP8 arithmetic serial processing section and the BIP2 arithmetic serial processing section. BI that serially performs addition operation of BIPPM based on the BIP error signal selected by the BIP error selection unit
PPM serial adder. In this case, the storage unit 2 stores the BIPP.
The calculation result in the M serial addition unit is stored for each channel, and the storage information is supplied to the BIPPM serial addition unit.

As a result, in the present POH termination processing device,
BIP errors that should normally be detected by POH termination processing for channels of different signal sizes can be detected serially in the B3, V5 byte serial termination processing unit common to each channel (above, claim 7 ). In addition,
The B3, V5 byte serial termination processing unit may be configured to include the following units.

BIP8 arithmetic serial processing unit for serially performing BIP8 arithmetic operation on multiple signals-First BIPPM serial addition unit for serially performing addition operation of BIPPM based on the BIP error signal from the BIP8 arithmetic serial processing unit. A BIP2 operation serial processing unit that serially performs BIP2 operation for multiple signals.

BI from the BIP2 arithmetic serial processing unit
A second BIPPM serial addition unit that serially performs addition operation of BIPPM based on the P error signal. Then, in this case, the storage unit 2 stores the first BI described above.
A first storage unit capable of storing each calculation result in the PPM serial addition unit for each channel and supplying storage information to the first BIPPM serial addition unit, and the second BI described above.
Each PPM serial addition unit stores a calculation result for each channel, and is provided with a second storage unit capable of supplying storage information to the second BIPPM serial addition unit.

That is, the B3, V5 byte serial termination processing section described above performs the BIP error signal (BI) by the BIP8 serial termination processing and the BIP2 serial termination processing, respectively.
After independently obtaining PPM), each BIPPM is selectively output. As a result, BIPPM can be serially obtained with a simple configuration.
This is very effective when there is no particular need to make the storage unit 2 for holding M common to all signal sizes (above, claim 8 ).

Further, the POH termination arithmetic processing unit 1 shown in FIG. 1 serially performs UNE (Unequipped) termination processing of C2 bytes and V5 bytes included in the multiplexed signal.
The storage unit 2 may be configured as an EQ serial termination processing unit. In this case, the storage unit 2 stores the calculation result of this UNEQ serial termination processing unit for each channel, and
It is configured to provide stored information to the serial termination unit.

As a result, in the present POH termination processing device,
UNEQ for C2 byte (included in POH of VC-3, considering STM-1 frame as multiplexed signal)
The termination processing and the UNEQ termination processing for the V5 byte included in the POH of the multiplex signal having the signal size of the low order group different from the multiplex signal including the C2 byte are performed by the UNEQ serial termination processing unit common to each channel. It can be performed serially (above, claim 9 ).

Therefore, specifically, the above-mentioned UNEQ serial termination processing unit is configured to include the following units. -A C2UNEQ display serial detection unit that serially detects whether or not the C2 byte is in UNEQ display. -V5UNEQ display serial detection unit that serially detects whether or not the V5 byte is in UNEQ display.

C2UNEQ display serial detector and V
5UNEQ Display UNEQ output from the serial detector
A UNEQ display selection section for selecting a display detection signal. A UNEQ serial detection unit that serially performs UNEQ display of C2 bytes and V5 bytes based on the UNEQ display detection signal selected by the UNEQ display selection unit. Then, in this case, the storage unit 2 is configured to store the detection result of the UNEQ serial detection unit for each channel and to supply the stored information to the UNEQ serial detection unit.

As a result, in the present POH termination processing device,
The UNEQ display, which should normally be performed by the POH termination processing for each channel having a different signal size, can be performed serially in the UNEQ serial termination processing unit common to each channel (above, claim 10 ). In addition, this UN
The EQ serial termination processing unit may be configured to include the following units.

A C2 UNEQ display serial detection unit that serially detects whether or not the C2 byte is in UNEQ display.・ UNEQ from the above C2UNEQ display serial detector
A first UNEQ serial detector for serially performing C2 byte UNEQ display based on a display detection signal. -V5UNEQ display serial detection unit that serially detects whether or not the V5 byte is in UNEQ display.

The V5 byte UN based on the UNEQ display detection signal from the V5 UNEQ display serial detection section.
A second UNEQ serial detector for serially displaying EQ. A UNEQ display selection unit that selects the UNEQ display output from the first UNEQ serial detection unit and the second UNEQ serial detection unit. In this case, the storage unit 2 shown in FIG.
The detection result of the Q serial detection unit is stored for each channel, and the detection result of the first UNEQ serial detection unit and the detection result of the second UNEQ serial detection unit are stored for each channel. Memorized in the second
It is configured to include a second storage unit capable of supplying storage information to the UNEQ serial detection unit.

That is, the above-mentioned UNEQ serial termination processing unit is used for the C2 byte UNEQ display processing and the V5 byte U.
After performing the NEQ display processing independently and serially, each UNEQ display is selectively output. As a result, the UNEQ display can be performed serially with a simple configuration, and it is very effective when there is no particular need to share the storage unit 2 for holding the UNEQ display with all signal sizes. (The above is claim 1
1 ).

Further, the POH termination arithmetic processing unit shown in FIG. 1 has S of C2 bytes and V5 bytes included in the multiplexed signal.
It may be configured as an SLM serial termination processing unit that performs termination processing of LM (Signal Lavel Mismatch) serially,
In this case, the storage unit 2 stores the calculation result of this SLM serial termination processing unit for each channel, and
It is configured to supply stored information to the M serial termination unit.

As a result, in the present POH termination processing device,
The SLM terminating process for the C2 byte and the SLM terminating process for the V5 byte can be serially performed by the SLM serial terminating unit common to each channel (above, claim 12 ). Therefore, specifically, the above SLM
The serial termination processing unit includes the following units.

A C2 mismatch serial detection unit that serially detects that the C2 byte is mismatch detected. A V5 mismatch serial detection unit that serially detects that the V5 byte is mismatch detected. A mismatch detection / selection unit that selects the mismatch detection signals output from the C2 mismatch serial detection unit and the V5 mismatch serial detection unit.

An SLM serial detection section that serially detects C2 byte and V5 byte SLMs based on the mismatch detection signal selected by the mismatch detection selection section. In this case, the storage unit 2 stores the detection results of the SLM serial detection unit for each channel, and
It is configured to provide stored information to the M serial detector.

As a result, in the present POH termination processing device,
Usually it can be performed in serially SLM detection to be performed by the POH termination processing for each channel with different signal sizes, in a common SLM serial termination processing section for each channel (or, according to claim 1 3). The SLM serial termination processing unit may be configured by including the following units.

A C2 mismatch serial detection unit that serially detects that the C2 byte is mismatch detected. A first SLM serial detection unit that serially detects the C2 byte SLM based on the mismatch detection signal from the C2 mismatch serial detection unit. A V5 mismatch serial detection unit that serially detects that the V5 byte is mismatch detected.

A second SLM serial detection section for serially detecting the V5 byte SLM based on the mismatch detection signal from the V5 mismatch serial detection section. -SLM that selects the SLM output from the first SLM serial detection unit and the second SLM serial detection unit
Selector. Then, in this case, the storage unit 2 stores each detection result of the first SLM serial detection unit for each channel, and also supplies the storage information to the first SLM serial detection unit and the second SLM serial. Each detection result of the detection unit is stored for each channel, and a second storage unit capable of supplying storage information to the second SLM serial detection unit is configured.

That is, the SLM serial termination processing unit described above is used to detect C2 bytes of SLM and V5 bytes of SLM.
After performing the detection process serially independently,
Each SLM is selectively output. As a result, SLM detection can be performed serially with a simple configuration, and it is very effective when there is no particular need to share the storage unit 2 holding the SLM for all signal sizes ( above, claim 1 4).

Further, the POH termination arithmetic processing unit shown in FIG. 1 has F of G1 byte and V5 byte included in the multiplexed signal.
End processing of EBE (Far End Block Error) and the above G
1-byte and V5-byte FEBEPM (FEBE Performanc
FEB that performs terminal processing of e Moniter) serially
The storage unit 2 may be configured as an E serial termination processing unit. In this case, the storage unit 2 stores the calculation result of the FEBE serial termination processing unit for each channel and
It is configured to provide stored information to the serial termination unit.

As a result, in the present POH termination processing device,
FEBE for G1 byte (included in POH of VC-3 when considering STM-1 frame as multiplexed signal)
And FEBEPM termination processing, and FEBE for V5 bytes included in POH of a multiplex signal having a signal size of a low-order group different from the multiplex signal including this G1 byte
And FEBEPM termination processing can be serially performed by the FEBE serial termination processing unit common to each channel (the above is claim 15 ).

Therefore, specifically, the above-mentioned FEBE serial termination processing unit is configured to include the following units.・ G1F that serially detects FEBE of G1 byte
EBE serial detector.・ V5F that performs FEBE detection of V5 bytes serially
EBE serial detector.

An FEBE selection section for selecting the FEBE detection signal output from the G1FEBE serial detection section and the V1FEBE serial detection section. A FEBEPM serial adder that serially performs FEBEPM addition operation based on the FEBE detection signal selected by the FEBE selector. Then, in this case, the storage unit 2 is configured to store each addition result in the FEEBEPM serial addition unit for each channel and supply storage information to the FEEBEPM serial addition unit.

As a result, in the present POH termination processing device,
The FEBE and FEEBEPM termination processing, which should normally be performed by the POH termination processing for each channel having a different signal size, can be performed serially in the FEBE serial termination processing unit common to each channel (above, claim 16 ). The FEBE serial termination processing unit may be configured by including the following units.

A G1FEBE serial detection unit for serially performing FEBE detection of the G1 byte. A first FEBEPM serial addition unit that serially performs FEBEPM addition operation based on the FEBE detection signal from the G1FEBE serial detection unit.・ V5F that performs FEBE detection of V5 bytes serially
EBE serial detector.

A second FEBEPM serial adder for serially performing FEBEPM addition operation based on the FEBE detection signal from the V5FEBE serial detector. -The above-mentioned first FEBEPM serial addition unit and second FE
A FEBEPM selection unit that selects the FEBEPM output from the BEPM serial addition unit. Then, in this case, the storage unit 2 is configured to store each addition result in the FEEBEPM serial addition unit for each channel and supply storage information to the FEEBEPM serial addition unit.

That is, the FEBE serial termination processing section described above detects the FEBE for the G1 byte and performs the FEB.
After performing the addition operation of EPM, the detection of FEBE for V5 byte, and the addition operation of FEBEPM independently and serially, each FEBEPM is selectively output. This makes F simple
The detection of EBE and FEEBEPM can be performed serially, and it is very effective when there is no particular need to share the storage unit 2 holding the FEBEPM for all signal sizes. 17 ).

Further, the POH termination arithmetic processing section 1 shown in FIG. 1 is configured as a FERF serial termination processing section for serially performing termination processing of FERF (Far End Receive Failure) of G1 byte and V5 byte included in the multiplexed signal. Alternatively, in this case, the storage unit 2 is configured to store the calculation result in the FERF serial termination processing unit for each channel and to supply the storage information to the FERF serial termination processing unit.

As a result, in the present POH termination processing device,
The FERF termination processing for the G1 byte and the FERF termination processing for the V5 byte can be serially performed by the FERF serial termination processing unit common to each channel (the above is claim 18 ). Therefore, specifically, the above-mentioned FERF serial termination processing unit is configured to include the following units.

A G1 FERF display serial detection section for serially detecting that the G1 byte is displaying FERF. -V5F ERF display serial detection unit that serially detects that the V5 byte is displaying FERF.・ The above G1FERF display serial detector and V5FE
An FERF display detection / selection unit that selects an FERF display detection signal output from the RF display serial detection unit.

G1 byte and V based on the FERF display detection signal selected by the FERF display detection selection section.
FERF serial detector that serially detects 5-byte FERF. Then, in this case, the storage unit 2 stores each detection result of the FERF serial detection unit for each channel, and
It is configured to provide stored information to the ERF serial detector.

As a result, in the present POH termination processing device,
The FERF termination processing, which should normally be performed by the POH termination processing for each channel having a different signal size, can be performed serially in the FERF serial termination processing unit common to each channel (above, claim 19 ). The FERF serial termination processing unit may be configured by including the following units.

A G1 FERF display serial detection unit that serially detects that the G1 byte is displaying FERF. A first FERF serial detection unit that serially performs the FERF detection of the G1 byte based on the FERF display detection signal from the G1 FERF display serial detection unit.

A V5F ERF display serial detection unit that serially detects that the V5 byte is displaying the FERF. A second FERF serial detection unit that serially performs the above-mentioned V5 byte FERF detection based on the FERF display detection signal from the V5 FERF display serial detection unit.

An FERF display selection unit for selecting the FERF display output from the first FERF serial detection unit and the second FERF serial detection unit. Then, in this case, the storage unit 2 stores the detection results of the first FERF serial detection unit for each channel, and the first storage unit that can supply storage information to the first FERF serial detection unit and the second FERF serial detection unit. The detection result of the detection unit is stored for each channel, and the second FER is used.
It is configured to include a second storage unit capable of supplying storage information to the F serial detection unit.

That is, the above-mentioned FEBE serial termination processing unit serially performs the FERF detection / display processing for the G1 byte and the FERF detection / display processing for the V5 byte independently and then serially.
Is selectively output. As a result, the FERF can be displayed serially with a simple configuration, which is very effective when it is not particularly necessary to make the storage unit 2 for holding the FERF common to all signal sizes. (The above is claim 20 ).

Further, the POH termination processing device shown in FIG. 1 performs processing in the POH termination calculation processing section 1 based on the timing signal indicating the positions of the J1 byte and V5 byte of the multiplexed signal and the type information of the multiplexed signal. By providing the POH timing signal serial generation unit that serially generates the POH timing signal for, the POH timing signal required for the POH termination calculation processing unit 1 can be serially generated in common for each channel ( Claim
1 ).

Therefore, specifically, the POH timing signal serial generator described above is configured to include the following units.・ SPE (Synchronous Payload Env.
elope) Count value initialization unit that initializes the count value.

A count value addition control unit for controlling addition of the SPE count value based on the signal from the count value initialization unit. A storage unit that can hold the SPE count addition value in the count value addition control unit for each channel and can supply the held data for each channel to the count value initialization unit, which is freely writable and readable.

A POH timing signal generation section for generating a POH timing signal for processing in the POH termination calculation processing section 1 based on the signal from the count value initialization section and the type information of the multiplexed signal. In the POH termination processing device configured as described above, in the POH timing signal serial generation unit, information regarding the start position (J1 byte, V5 byte) of the SPE in the multiplexed signal is held in the storage unit for each channel. , POH for the processing in the POH termination arithmetic processing unit 1 by sequentially updating.
The OH timing signal can be serially generated by the POH timing signal serial generation unit common to each channel (above, claim 21) . In addition, the POH shown in FIG.
The termination processing device is provided with an address creation unit that creates address information for identifying each channel of the multiplexed signal, so that the address creation unit common to each channel creates the address information for the storage unit 2. Therefore, it is not necessary to provide the circuits for generating the address information for the storage unit 2 by the corresponding number of channels, and the POH termination arithmetic processing unit 1 performs a special process for identifying each channel. It becomes unnecessary to carry out (Claim 2 ).

The POH termination processing device shown in FIG.
The POH termination arithmetic processing unit 1 may be configured to include the following units. A J1 and J2 byte serial termination processing unit that serially terminates the J1 byte and J2 byte included in the multiplexed signal.・ BI of B3 byte and V5 byte included in the multiplexed signal
Termination process of P and BIP of B3 byte and V5 byte mentioned above
A B3, V5 byte serial termination processing unit that performs PM termination processing serially.

C2 byte and V5 included in the multiplexed signal
A UNEQ / SLM serial terminating unit that serially terminates the UNEQ of the byte and also terminates the SLM of the C2 byte and the V5 byte described above.・ FE of G1 byte and V5 byte included in the multiplexed signal
BE termination processing and F of G1 byte and V5 byte described above
An FEBE / FERF serial termination processing unit that performs termination processing of EBEPM serially and termination processing of FERF of G1 byte and V5 byte described above in serial.

In this case, the storage unit 2 stores the J
1, J2 byte serial termination processing section, B3, V5 byte serial termination processing section, UNEQ / SLM serial termination processing section, FEBE / FERF serial termination processing section stores the calculation results for each channel, and these J
It is configured to supply storage information to the 1, J2 byte serial termination processing section, the B3, V5 byte serial termination processing section, the UNEQ / SLM serial termination processing section, and the FEBE / FERF serial termination processing section.

In the POH termination processing device configured as described above, termination processing for J1 and J2 bytes for performing multi-frame pattern detection of multiple signals, and B3 and V5 bytes for obtaining BIP (BIPPM) from multiple signals are performed. C to get termination, UNEQ, SLM
2, V5 byte termination processing, FEBE (FEBE
The termination for the G1, V5 byte for obtaining the termination and FERF for G1, V5 byte for obtaining PM), respectively, can be performed serially to common to the channels (or more, according to claim 2 2).

Note that the pointer / POH termination processing device of the present invention performs pointer processing and P-processing on a signal transmitted by the SDH transmission method in which a plurality of channel information is multiplexed.
In the pointer / POH termination processing device that performs OH termination processing, the serial pointer processing unit that performs the pointer processing on the multiplexed signal without separating it for each channel and the positions of the J1 byte and V5 byte of the multiplexed signal are described.
Based on the timing signal shown and the type information of the multiplexed signal.
The POH timing signal for POH termination processing.
Really generated, or knowledge of each channel of the above multiple signals
Address information for differentiating is generated, and the POH remains serial without separating the multiplexed signal for each channel.
It is characterized in that it is configured with a serial POH termination processing section that performs termination processing.

As a result, in the pointer / POH termination processing device described above, both the pointer processing and the POH termination processing for the multiplexed signal transmitted by the SDH transmission method are performed.
In each case, the multiplexed signal can be serially performed without being separated for each channel (above, claim 25 , claim 26 ).

[0068]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (A) Outline of SDH transmission method As is well known, SDH is a standardized standard for the purpose of unifying interfaces for effectively multiplexing high-speed services and existing low-speed services in various countries around the world. All data transmission speeds (bit rates) should be 15
Data transmission rate (155 Mbps) with 5 Mbps (more accurately, 155.52 Mbps) as a basic rate (multiplexing unit)
ps × n: However, by uniformly multiplexing with n = 1, 4, 16, 64), various data including existing low-speed data (low-order group information) can be multiplexed. , It is possible to flexibly respond to new services in the future.

Specifically, in this SDH, virtual
A virtual "box" called a container (VC) is defined, some low-order group information is put into this "box" to make high-order group information, and some of these "boxes" are collected to make a larger "box". By adopting a method such as putting it in a box,
Various kinds of information having different transmission rates are finally put in one large "box" so that they can be transmitted.

For example, as shown in FIG. 2, the basic multiplexing unit of SDH is STM-1 (Synchronous Transfer Mode L).
evel 1) This is called a frame, and in this STM-1 frame, there is one AU-4 to which a management pointer [AU (Administrative Unit) pointer] for indicating the accommodation position of the VC-4 and frequency synchronization described later is added. It is accommodated, and further, in this VC-4 frame, 1 channel (channel) of 138 Mbps series data called C (Container) -4 or 3 channels of TUG (Tributary Unit Group) -3 are accommodated. It has become.

Further, in this TUG-3 frame,
TU (Tributary Unit) -3 (34 Mbps series) is 1c
h or TUG-2 (6 Mbps series) 7ch
TU-2 is multiplexed for 1ch or TU-12 is multiplexed for 3ch in TUG-2. The above-mentioned TU-3 adds a path overhead (POH: transfer destination information) to a 34 Mbps series frame called C-3 to form a VC-3, and stores the accommodation position in the VC-3.
This is a frame added with a TU pointer for frequency synchronization.

TU-2 is a frame in which POH is added to a C-2 (6 Mpbs series) frame to form VC-2, and a TU pointer is added to this VC-2.
U-12 adds POH to a C-12 (2 Mbps series) frame to form a VC-12, and this VC-12 has a T
This is a frame to which a U pointer is added. Therefore, STM
Within one frame of -1 signal, at most 3c for TU-3
In the case of h and TU-2, a maximum of 21 ch is multiplexed, and in the case of TU-12, a maximum of 63 ch is multiplexed.

Here, hereinafter, the above STM-1, TU-
Each frame format of 3, TU-2, and TU-12 will be described. In addition, hereinafter, the above-mentioned TU-3, TU
-2, TU-12, etc. are simply TU3, TU2, TU
Notated as 12, etc. STM-1 Frame Format FIG. 3 is a view showing the frame format of the above STM-1. As shown in FIG. 3, the STM-1 frame has 9 rows × 270 columns (column = BYTE). The first 9 rows × 9 columns are composed of a section overhead (SOH) 231 and an AU (AU4) pointer 232, and the next 9 rows × 261 columns are a payload (SPE) containing multiplexing information. : Synchronous Payload Envel
ope) 233.

The section overhead 231
Consists of various operation and maintenance information such as A1 and A2 bytes indicating the frame synchronization pattern of the STM-1 frame and B1 byte for code error monitoring, and the AU4 pointer 232 is a VC (VC4: H1 bytes (H1 # 1 to H1 # 3 bytes) and H2 bytes (H2 # 1) indicating the accommodation position (start address) of FIG. 4).
~ H2 # 3 bytes), H3 bytes (H3 # 1 to H3 # 3
Bytes).

However, normally, the H1 byte (H1
# 1 byte), H2 byte (H2 # 1 byte) stores the actual AU4 pointer value, and H1 # 2 byte, H2 #
Fixed values are stored in 2 bytes, H1 # 3 bytes, and H2 # 3 bytes as dependent pointers (CI: Concatination Indication). Then, for example, as shown in FIG. 3, the offset pointer value indicating the address of the first byte of VC4 starts at address 0 after H3 # 3 bytes and H1 # 1.
Since it is stipulated that the byte before ends at address 782, if the AU4 pointer value is "0", STM-1 and VC
4 indicates that the frame phase is the same as that of V4, and VC4 is sequentially accommodated immediately after the H3 byte (H3 # 3 byte).

On the other hand, if the AU4 pointer value is a value other than "0", the frame phases of STM-1 and VC4 do not match, and for example, as shown in FIG. 4, the first byte (J1 byte) of VC4 is It shows that the VC 4 is housed so as to be located at the address shifted from 0 by the amount corresponding to the phase shift. Since the offset pointer value of AU4 is normally defined every 3 bytes, the frame phase of VC4 changes by 3 bytes when the pointer value changes by one.

Further, the above H3 byte (H3 # 1 to H3
# 3 bytes) and the 3 bytes following this H3 byte (# 1 to # 1
The # 3 byte) is a frequency adjustment byte called a negative stuff byte and a positive stuff byte, respectively, and is a transmission frame (STM-1).
In the case where there is a slight difference between the clock frequency of the above and the clock frequency of the multiplexing information (VC4), the frequency adjustment is performed by using these positive / negative stuff bytes (by performing the stuff control). It is possible to prevent the loss of transfer information by absorbing the clock frequency difference and phase fluctuation of the transmission frame.

TU3 Frame Format Next, FIG. 5 is a diagram showing the frame format of TU3 described above. As shown in FIG. 5, the TU3 frame is
It is represented by a two-dimensional byte array of 9 rows x 86 columns (BYTE). Of the first 9 rows x 1 column, H1 bytes and H2 bytes are VCs in the payload 233 (VC3: see Fig. 6).
Is a TU (TU3) pointer for accommodating the accommodation position and frequency synchronization, and the H3 byte and the subsequent 1 byte (offset pointer value “0”) for the frequency (frame phase) adjustment respectively. Negative stuff bytes and positive stuff bytes. The remaining 6 rows other than the H1 to H3 bytes in the first 9 rows × 1 column
Fixed stuff bytes in the row x 1 column part
Is.

Then, as shown in FIG. 5, the offset pointer value indicating the address of the first byte of VC4 is H3.
Since it is specified that the byte after is started at address 0 and the byte before H3 is ended at address 764, if the TU3 pointer value is "0", the frame phase of TU3 and VC3 match, and VC3 is H3 byte. It is indicated that they are sequentially accommodated immediately after (address 0).

On the other hand, if the TU3 pointer value is a value other than "0", the frame phases of TU3 and VC3 do not match, and, for example, as shown in FIG.
It indicates that the VC3 is sequentially accommodated so that (1 byte) is located at the address shifted from the address 0 by the amount corresponding to the phase shift. By the way, in FIG. 6, the 9-row × 1-column portion including the J1 byte indicated by reference numeral 235 is called a VC3 path overhead (VC3-POH), and is a VC3 path assembly point (multiplexed) defined as a path. Processing is added and stored up to the decomposition point (separation processing) after the information is transmitted. By monitoring this VC3-POH 235, the status such as a code error of the transmission information is monitored end to end. You can do it.

Therefore, the VC3-POH 235 has, in addition to the J1 byte described above, B3 byte, C2 byte, and G1 byte.
It has a format including bytes, F2 bytes, H4 bytes, and Z3 to Z5 bytes. The functions of the above bytes are shown below. (1) J1 byte: Called as a path trace signal, by repeatedly transmitting a fixed pattern signal, the receiving side confirms whether or not the connection with the transmitting side is normally maintained (path continuity confirmation). Used to do (monitor)
To be done.

(2) B3 byte: Used for path error monitoring, and the operation result by an operation process called BIP (BiP) 8 described later is inserted as B3 byte of the next frame. (3) C2 byte: a byte (signal label) for expressing the mapping structure of VC3, and as described later, VC
Various information such as UNEQ display indicating that 3 does not accommodate the payload is set.

(4) G1 byte: a byte used to represent the path status, a function (FEBE) for returning the error monitoring result of the received path to the VC3 transmission side, and a path termination status to the transmission side. Playback alarm display function (FER)
F) and used. (5) F2 byte: The user channel is a byte that can be freely used by the network operator.

(6) Z3 to Z5 bytes: These are bytes prepared internationally as a spare. In this embodiment,
By POH termination processing described later, J1 byte, B3 byte, C2 byte, and G1 byte of each of the above bytes are monitored (termination processing). TU2 Frame Format FIG. 7 shows the frame format of TU2. As shown in FIG. 7, the TU2 frame has 4 rows.
Expressed by a two-dimensional byte array of 108 columns (BYTE), V1 byte and V2 byte of the first 4 rows × 1 column are VC2
(See FIG. 8) TU for indicating accommodation position and frequency synchronization
This is a (TU2) pointer, and the V3 byte and the subsequent 1 byte (on the right side of the paper) are the negative stuff byte and the positive stuff byte for frequency (frame phase) adjustment, respectively. The V4 byte is a spare byte reserved internationally for future use.
Not currently used.

Then, as shown in FIG. 7, the offset pointer value indicating the address of the first byte of VC2 is V2.
Since it is specified that the byte after is started at address 0 and the byte before V2 is ended at address 427, if the TU2 pointer value is "0", the frame phase of TU2 and VC2 also match, It indicates that VC2 is sequentially accommodated immediately after the V2 byte (address 0).

On the other hand, if the TU2 pointer value is a value other than "0", the frame phases of TU2 and VC2 do not match, and, for example, as shown in FIG.
It indicates that the VC2 is accommodated so that (5 bytes) is located at an address shifted from 0 by an amount corresponding to the phase shift. By the way, in FIG. 8, V indicated by reference numeral 236
The part of 4 rows x 1 column containing 5 bytes is called the path overhead of VC2 (VC2-POH).
By monitoring the VC2-POH 236, it is possible to monitor the status such as a code error of the transmission information end to end.

Therefore, the VC2-POH 236 has J2 byte, Z6 byte, Z7 in addition to the above V5 byte.
It has a format that includes bytes. Since the path overhead of the VC12 has the same format as that of the VC2-POH236, the functions of the above-mentioned respective bytes will be collectively described in the following description of the TU12 frame format.

TU12 Frame Format FIG. 9 is a diagram showing the frame format of the TU12 described above. As shown in FIG. 9, the TU12 frame has 4 frames.
Represented by a two-dimensional byte array of row × 36 columns (BYTE), V1 byte and V2 byte of the first 4 rows × 1 column are VCs, as in the TU2 frame format described above.
12 (see FIG. 10) is a TU (TU12) pointer for accommodating position indication and frequency synchronization, and V3 byte and one byte following (toward the right side of the drawing) are negatives for frequency (frame phase) adjustment. A staff byte and a positive staff byte. In addition, this TU12
The V4 byte in is also a reserved byte reserved internationally for future use.

Then, as shown in FIG.
The offset pointer value indicating the address of the first byte of the
2 bytes after start at address 0 and V2 before byte 139
Since the TU12 pointer value is "0", the frame phases of TU12 and VC12 match each other, and VC12 is sequentially accommodated immediately after the V2 byte (address 0). Indicates that

On the other hand, if the TU12 pointer value is a value other than "0", the frame phases of the TU12 and the VC12 do not match, and for example, as shown in FIG. 10, the leading byte (V5 byte) of the VC12 is out of phase. It indicates that the VC 12 is housed so as to be located at the address shifted from the 0 address by a considerable amount. By the way, in FIG. 10, the portion of 4 rows × 1 column including the V5 byte indicated by reference numeral 237 is called the path overhead (VC12-POH) of the VC12,
Like the VC2-POH236, it has a format including J2 bytes, Z6 bytes, and Z7 bytes in addition to the above V5 bytes. The function of each of these bytes is shown below.

(1) V5 byte: Path error monitoring of VC2 or VC12 by arithmetic processing called BIP2 described later, FEBE for returning the presence / absence of received BIP2 to the transmitting side, VC2 / VC12 mapping structure display by signal label , Bytes used for VC2 / VC12 path game alarm indication (FERF). That is, this V5 byte is the same as the above-mentioned VC3-POH23.
Each function of B3, C2 and G1 bytes included in No. 5 is allocated in one byte (8 bits).

(2) J2 byte: VC3-PO described above
This byte is used as a path trace signal similarly to the J1 byte included in H235, and is used for confirming the path continuity. (3) Z6, Z7 bytes: These are spare bytes. In this embodiment, V5 bytes and J2 bytes of each of the above bytes are monitored (termination processing) by POH termination processing described later.

(B) Outline explanation of POH termination processing In the SDH transmission system, as described above, VC3 / VC2 /
By monitoring (terminating) each of the POHs 235 to 237 of the VC 12, the status such as a code error of the transmission information is monitored end to end. Here, an outline of the POH terminating processing will be described.

(B1) J1 and J2 Byte Termination Processing As described above, J1 included in the VC3-POH 235.
By monitoring the byte, the J2 byte included in the VC2 / VC12-POH 236, 237, it is possible to confirm the path continuity. For example, as shown in FIG. 11, POH (“A”) is added to the transmission side device “# 1”, and POH (“A”) is added to the transmission side device “# 2” as the correct line setting.
Considering that ("B") is added, the receiving device "# 3" monitors the J1 and J2 bytes by terminating the received POH ("A", "B").

Here, specifically, the J1 and J2 bytes (path trace signal) are VC3 / VC2 / VC12.
Is a signal obtained by adding a trace signal (path name) composed of 15 characters of ASCII characters to the path signal of, and has a format as shown in FIG. 12, for example, and has a 16-byte multi-frame with 15 characters of ASCII. Character (AS
The CII data bit "X") can be transferred.

As a result, the receiving device "# 3" checks whether the received value (reception path name) and the expected reception value (path name to be received) match, and the received signal is You can check whether it is connected to the correct device, and if it does not match, a TIM that indicates that
(Trace Indicator Mismatch) is detected
An alarm occurs.

In the frame format of the path trace signal shown in FIG. 12, 16 frames (1
The MSB (most significant bit) of 6 bits) is called a multi-frame indicator, and the path trace signal is detected by detecting this multi-frame indicator ("1000 0000 00000000"). This multi-frame indicator is out of frame synchronization (LOM: Loss
Of Multiframe) detection, under the following conditions,
Out-of-frame detection of 7 steps forward and 3 steps backward is performed.

Frame mismatch detection condition: 1 in the received signal when processing the 16th byte of the multiframe
The 6-bit frame indicator pattern is "1000 00
If it is not 00 0000 0000 "・ Frame match detection condition: When processing the 16th byte of the multiframe, the 16-bit frame indication pattern in the received signal is" 1000 0000 0000 0000 ".
In addition, in FIG. 12, the MS with the frame number “0”
Bit "C" except B is CRC (Cyclic Redundancy Ch
eck) -7 parity bit, which is used for CRC-7 operation by a generator polynomial of X ⁷ + X ³ +1.

For example, as shown in FIG. 13, on the receiving side,
The received data (path trace data) of the frame number “0” is set to 80 (HEX), and the CRC-7 operation is performed on the received data (bits 1 to 8) of the frame numbers “0” to “15”. A CRC error is detected by comparing the calculation result with the reception CRC bit of the frame number "0" of the next multiframe. In addition, here, the detection of the CRC error is performed in the front three stages and the rear three stages.

(B2) B3 Byte Termination Processing The B3 byte (see FIG. 14 for the format) contained in the VC3-POH 235 is transferred to the BIP8 (Bit Interleaved Parit).
y -8) By performing termination processing using an error parity method called operation, it is possible to detect an error (code error) in the path of the VC3 signal. However, in this case,
Even parity is applied as the error parity method.

More specifically, this BIP8 operation is a method of calculating the parity for every 8 bits of the counted data (byte unit) as shown in FIG. 15A, and counting the parity of the same digit in byte units. Then, Figure 1
As shown in FIG. 5 (b), the result is displayed on the same digit of BIP8. For example, on the receiving side, as shown in FIG. 16, data of one frame (85 bytes × 9 = 765 bytes) of the VC3 signal is subjected to all parity calculations in units of 1 byte (8 bits), A parity error is detected for each bit unit of MSB to LSB (least significant bit) by comparing with the B3 byte extracted from the subsequent next frame. When a parity error is detected in one frame, one alarm is generated.

(B3) C2 Byte Termination Process By terminating the C2 byte (see FIG. 17 for the format) included in the VC3-POH 235 (monitoring the signal label), the mapping structure of the VC3 signal can be recognized. , A mismatch of signal labels (mismatch: SLM) and UNEQ (indicating that the VC3 signal does not accommodate the payload) can be detected.

Here, C2 byte (signal label)
18, the value (8-bit mapping code) set according to the mapping structure of the VC3 signal is defined, and when the VC3 signal does not accommodate the payload, UNEQ display ALL is displayed. "0" is set. On the receiving side, the C2 byte is monitored, and, for example, when the C2 byte having the UNEQ display (ALL “0”) is detected for four consecutive frames, the UNE is displayed.
When a Q detection alarm is generated and the C2 byte other than the UNEQ display is detected for 6 consecutive frames, the UNEQ detection alarm is released.

At this time, the receiving side performs SLM detection by comparing the expected reception value of C2 bytes set by the maintenance person with the actual received value of C2 bytes. When the discrepancy with the value is detected seven consecutive times, the SLM detection alarm is generated, and when the coincidence is detected three consecutive times, the SLM detection alarm is released.

(B4) G1 Byte Termination Processing By terminating the G1 byte contained in the VC3-POH 235, the path state of the VC3 signal can be recognized. The G1 byte has a format as shown in FIG. 19, for example, and the upper 4 bits of the G1 byte (8 bits) are FEBE (Far End Block E).
rror) bits (see FIG. 19),
The subsequent 1 bit is assigned as a FERF (Far End Receive Failure) bit (see FIG. 19). The remaining 3 bits (see FIG. 19) are currently unused.

As described above, the FEBE bit is used to return the number of parity error bits to the opposite device (transmission side) when a B3 (BIP8) parity error of the received VC3 signal is detected. With the bits used, for example, as shown in FIG. 20, the number of detected errors in the termination process of the B3 byte is set as the number of detected errors of FEBE. As shown in FIG. 20, the FEBE bit is currently defined with 8 types of states (16 types) that can be represented by 4 bits.

The FERF bit is a bit used to inform the opposite device that a failure has occurred in the receiving side device that terminates the VC3 signal.
"1" indicates "VC3 Far End Receive Failure" notification status. Then, on the receiving side, this G1 byte is monitored,
The receive code of the upper 4 bits (FEBE bit) is "00"
If it is other than "00", the number of errors in the game is detected and counted as one alarm. Also, when "1" of the FERF bit is detected, it is regarded as an FERF alarm. In this case, "1" of the FERF bit is 10 An FERF alarm is generated when consecutive frames are detected, and R is generated when "0" of the FERF bit is consecutively detected for 10 frames.
Clear the ERF alarm.

(B5) V5 Byte Termination Processing The V5 byte included in the VC2-POH236 or VC12-POH237 has a format as shown in FIG. 21, and the upper 2 of the V5 bytes (8 bits) are included. Bit is BIP2 bit (see FIG. 21), followed by 1 bit is FEBE bit (see FIG. 21), followed by 1
The bit is an RFI bit for notifying the microcomputer of V5 byte (see FIG. 21), the subsequent 3 bits are a signal label (see FIG. 21), and the least significant 1 bit is a FERF bit (see FIG. 21). Each is assigned.

Therefore, by terminating the V5 byte on the receiving side, the BIP2 operation can be performed to VC2 / VC1.
Error in 2 signal path (code error), mapping structure of signal label to VC2 / VC12 signal, FEBE
It is possible to detect the path state of the VC2 / VC12 signal from the bit and the FERF bit. Here, in the BIP2 operation, even parity is applied by the same error parity method as the BIP8 operation for the B3 byte described above. In this BIP2 operation, however, as shown in FIG. The parity is calculated every other bit (byte unit). Therefore, the parity is counted for each odd bit and even bit in one byte, and the count result is displayed in the upper 2 bits of the V5 byte as shown in FIG.

As a result, on the receiving side, as shown by the shaded portion in FIG. 23, all the parity calculations are performed every one bit in the range of the counted data for one multiframe of the VC2 / VC12 signal, and the calculation is performed. The result is compared with the BIP2 bit of the V5 byte extracted from the next multi-frame, and a parity error is detected in both MSB and LSB. When a parity error is detected in one multiframe (maximum 2 bits), 1 alarm is generated.

Then, V5 of the received VC2 / VC12
(BIP2) When a parity error is detected, the number of parity error bits (V5
The number of detected errors in bytes) is set as FEBE and is returned to the player device. As shown in FIG. 24, the FEBE bit of the V5 byte currently has two types of states that can be represented by the 1 bit. Therefore, when the number of detected errors in the V5 byte is "2" or more, all of them are "1". It is defined as ".

Next, the V5 byte signal label is a value [3 bits (bit numbers B5 to B7) mapping code set according to the mapping structure of the VC2 / VC12 signal, as shown in FIG. 25, for example. ] Is specified, and this signal label is also VC3-POH235.
Similarly to the C2 byte included in, when the VC2 / VC12 signal does not accommodate the payload, it is UNEQ indicating AL.
L "0" is set.

On the receiving side, the signal label is monitored and, for example, when the V5 byte whose signal label is UNEQ display (ALL "0") is detected for four consecutive frames, a UNEQ detection alarm is generated. ,
When the V5 byte whose signal label is other than UNEQ display is detected for 5 consecutive frames, the UNEQ detection alarm is released.

At this time, if the receiving side compares the expected reception value of the signal label set by the maintenance person with the actual reception value of the signal label, and detects a mismatch of the signal labels seven times in a row. Mismatch (SLM)
When a detection alarm is generated and a signal label match is detected three times in a row, the SLM detection alarm is released.

Next, the above FERF bit is VC2 /
It is a bit used to notify the opposite device that a failure has occurred in the receiving side device that terminates the VC12 signal. It is a normal state when "0" and "VC2 / VC12 Far End Re when" 1 ".
ceive Failure "notification status, and on the receiving side,
Monitor the FERF bit of this V5 byte, and
When a bit "1" is detected, an FERF alarm is generated. Also in this case, when a FERF bit "1" is continuously detected for 10 frames, a RERF alarm is generated,
When "0" of the FERF bit is detected for 10 consecutive frames, the RERF alarm is released.

(B6) Performance Monitor (PM) Function The performance monitor function is a function used for line quality monitoring and line maintenance of the transmission line in service, and in this embodiment, as will be described later, a microcomputer is used. A parity error (BIP8, BIP8, B
The number of detected IP2) and FEBE errors is counted, and the count result is notified to the microcomputer.

26 (a) to 26 (f) show examples of BIP error performance monitor operation, and FIGS. 27 (a) to 27 (g) show F.
An example of an EBE error performance monitor operation is shown. (C) Description of POH termination processing device (C1) Description of overall configuration of POH termination processing device FIG. 28 is a block diagram showing an example of an SDH transmission network. In FIG. 28, 301 is a subscriber terminal and 302 is a line termination device. (NT), 303 and 306 are transmission terminal devices (LT), 304 is a switching device (SW), 305 is a multiplexing device (MUX), and 307 is a relay transmission line.

In the SDH transmission network shown in FIG. 28, the data from a plurality of subscriber terminals 301 is sent to the STM-n frame (where n = 1, 4,
16, 64), and the transmission terminal device 306 terminates / replaces overhead (SOH, POH),
Processing such as termination / replacement of the AU / TU pointer is performed, and the data is transmitted to the opposite subscriber terminal 301 side through the relay transmission line 307.

FIG. 29 shows a PO as an embodiment of the present invention.
FIG. 29 is a block diagram showing a configuration of a main part of the transmission terminal station device 306 to which the H termination processing device is applied.
The transmission terminal device 306 includes an SOH termination processing unit 4, an AU pointer processing unit 5, a TU pointer processing unit 6, an elastic memory (ES) unit 7, a POH termination processing unit (POH termination processing device) 8 and a path switch alarm insertion. It is configured to include an active system 3A and a standby system 3B each having a section 9.

Then, the transmission terminal station device 3 shown in FIG.
In 06, when various alarms defined by the SDH transmission method are detected in the POH termination processing unit 8, each alarm information of TIM, UNEQ, and SLM is sent to the path switch alarm insertion unit 9 among various alarm detection information. At the same time, the BIPPM is notified to the microcomputer (μ-COM) 10. In response to this notification, the microcomputer 10 performs an alarm process by software, and then the path switch alarm insertion unit 9 is notified. Set the path switch alarm insertion. That is, TIM, SL
TU that detected each of M, UNEQ, and BIPPM alarms
Set the channel signal to ALL "1".

As a result, the cross connect device (XC)
An abnormality is detected at 11, and the active system 3A is switched to the standby system 3B. FIG. 30 is a block diagram showing the configuration of the transmission terminal station device 306 focusing on the TU pointer processing unit 6 and the POH termination processing unit 8 described above. As shown in FIG. 30, the TU pointer processing unit 6 uses the TU pointer serial Processing unit 61 and TU pointer timing generation unit 62
It is configured with
The J1 / V5 byte timing signal generated by the U pointer processing unit 61, the SPE enable signal, and the TU address signal (T
UAD), mapping signals, etc. are used for the processing in the POH termination processing unit 8, respectively.

Therefore, as shown in FIG. 31, the TU pointer serial processing unit (serial pointer processing unit) 61.
Is a pointer extraction unit 61-1 and a pointer processing unit 61-
2, RAM (random access memory) control unit 61-
3, a RAM 61-4 is included, and the TU pointer timing generation unit 62 is configured to include an address generation unit 62-1.

Here, in the TU pointer timing generation unit 62, the address generation unit (address generation unit)
62-1 is a TU that is multiplexed in an STM-1 frame (VC4 signal) based on a frame signal generated based on detection of a frame synchronization pattern (A1, A2 bytes) included in SOH of an STM-1 frame. An address (channel address) to be assigned to each level channel (multiplexed data) is generated. In the present embodiment, this TU channel address is used as POH as address information (TUAD) for identifying the TU channel of the VC4 signal. It is adapted to be used for the processing in the termination processing unit 8.

In the TU pointer serial processor 61, the pointer extractor 61-1 serially extracts pointer bytes (including at least H1 / V1 byte and H2 / V2 byte) of each channel from the multiplexed data. The pointer processing unit 61-2 serially analyzes the pointer of each channel, detects the state, replaces the pointer, etc. based on the multiplexed data from the pointer extraction unit 61-1.

Further, the RAM control unit 61-3 serially outputs the result of the pointer processing unit 61-2 for each channel as R.
The RA 61 is for generating a control signal for controlling a series of operations for writing / reading to / from the AM 61-4.
M61-4 holds the output data of the pointer processing unit 61-2 for each channel in the area indicated by the channel address from the address generation unit 62-1.

In FIG. 31, 100 'is a mapping setting register group, 101' is a selector section, and the mapping setting register group 100 'is the multiplexed data (ST).
Each channel of M-1 frame) is TU3 / TU2 / T
U12 is used to set which signal size is mapped, and the selector unit 101 'uses the address assigned to each channel by the address generation unit 62-1 to select the corresponding channel from the mapping setting register group 100'. A signal size is selected and mapping information is output serially (multiplexed). These mapping setting register group 100 'and selector section 10
The detailed configuration of 1'will be described later with reference to FIG.

In the TU pointer processing unit 6 constructed as described above, the pointer extraction unit 61-1 and the pointer processing unit 6 are provided.
The information group generated through 1-2 is the address generation unit 6
The RAM control unit 61 is placed at the address of the RAM 61-4 indicated by the RAM address (channel address) generated in 2-1.
It is written according to the write enable signal (detection timing of the reception pointer byte) generated in -3.

Then, in the pointer processing unit 61-2, R
The information group of the previous frame is read from the AM 61-4 according to the read enable signal generated by the RAM control unit 61-3, and the pointer processing is serially performed using the read information group of each channel. FIG. 32 is a block diagram showing a detailed configuration of the above-mentioned address generation unit 62-1. As shown in FIG.
Address counter 15 for UG3, address counter 16 for TUG2, address counter 17 for TU12, AND
Circuit (logical product circuit) 18, 1-input inverting AND circuit 1
9 and an address conversion unit 20.

Here, the address counter for TUG3 (3
The increment counter 15 counts the number (channel number) of the TUG3 (maximum of three multiplexed) in the STM-1 frame (VC4 frame), and the TUG2 address counter (7 Hex counter)
16 is TUG2 multiplexed in the TUG3 frame
It counts the number of channels (maximum of 7 channels are multiplexed), and the TU12 address counter (3
The advance counter) 17 counts the number of channels of the TU 12 (maximum of 3 multiplexed) multiplexed in the TUG2 frame. Each of the address counters 15 to 17 loads an initial value with a frame signal.

In this embodiment, as shown in FIG. 32, the carry-out (C
O) is connected to the carry-in (CI) of the address counter 16 and the carry-out of the address counter 16 is connected to the carry-in of the address counter 17, thereby forming a 63-ary counter. The outputs of 15 to 17 are RAM 61
-4 is used as a RAM address (channel address).

The AND circuit (logical product circuit) 18 is
When the TU12 mode is not set by the TU12 setting signal which will be described later (when the TU12 setting signal is at the L level), the output of the address counter 17 is converted to "0", and the 1-input inversion type AND circuit 19 is used. Is for converting the output of the address counter to "0" only when the TU3 mode is set by the TU3 setting signal described later (when the TU3 setting signal is at the H level).

The address conversion unit 20 includes the counters 15-
A desired addition process is performed on the address output from 17 to generate an address conversion signal that does not cause an empty address in the RAM 14. As a result, in the address generator 62-1, a combination of the counters 15 to 17 that operate according to the TU12 mode setting signal and the TU3 mode setting signal (counter 15 only, counter 15 and counter 16, counters 15 to 17) is used.
And the address for the RAM 14 is changed to, for example, FIG.
By generating the combination as shown in
RAM for 3 / TU2 / TU12 channel address
Share it on 61-4.

Therefore, in the STM-1 frame, frames (VC4 / VC3 / VC2 / VC1) having different signal sizes are included.
No matter which combination of 2) is mixed, one address generation unit 61-4 can flexibly deal with it. In FIG. 33, addresses 00-02 _HEX are TUs.
3 / TU2 / TU12 shared address, address 0
3 to 14 _HEX is a TU2 / TU12 shared address.

Furthermore, the channel address generated as described above is subjected to address conversion in the address conversion unit 20 to obtain an address output in which all empty addresses are compressed (see address space in FIG. 34). , The address line to RAM 61-4 is from 7 bits to 6
Converted to bits. This output is used as the TU channel address (TUAD) for the POH termination processing unit 8 described above.

That is, the POH termination processing unit 8 of this embodiment
Uses the TU address signal serially generated in the address generation unit 62-1 of the TU pointer processing unit 6 in common, and thereby the TU required for the POH byte serial termination processing according to VC3 / VC2 / VC12. It eliminates the need to individually generate address signals.

Therefore, it is not necessary to provide the circuits for generating the TU address signals by the corresponding number of channels, and it is not necessary to perform a special process for identifying each TU channel, so that the circuit scale can be reduced and consumed. It will contribute to the reduction of electric power. Next, FIG. 35 shows SP
FIG. 25 is a block diagram showing the configuration of the pointer processing unit 61-2 focusing on the E first byte (J1 / V5 byte) recognition function portion. The pointer processing unit 61-2 shown in FIG.
It is configured to include an M89 'and an SPE leading byte recognition section 97A.

Here, the SPE first byte recognition unit 97A
Is for recognizing the J1 byte (the head byte of the VC3 signal) or the V5 byte (the head byte of the VC2 / VC12 signal) as the head byte of the SPE. As shown in FIG. Part 98 '
And an AND circuit 99 '. Then, the offset counter unit 97 ′ is triggered by the frame signal to generate a signal shown in FIG.
This is for counting the offset pointer value of the SPE described above with reference to FIG. 10 to search the first byte of the SPE, and the coincidence detection unit 98 'reads the active pointer value from the RAM 89' as the SPE enable signal as the read enable signal. The AND circuit 99 'detects the coincidence between the active pointer value and the offset counter value of the offset counter section 97'.
The SPE enable signal and the coincidence detection result of the coincidence detection unit 98 'are ANDed to generate and output the SPE start byte position (J1 / V5 byte) instruction signal.

That is, this SPE head byte recognition unit 97
A has an offset counter unit 97A for searching the first byte of the SPE, reads the active pointer value from the RAM 89 ', and calculates the logical product of the SPE enable signal and the match detection result of the offset counter value and the active pointer value. , SPE the first byte position is recognized.

Pointer processing unit 6 configured as described above
In 1-2, the RAM 8 is used in accordance with the SPE enable signal.
The held active pointer value is read from 9 ', and the offset counter unit 97' starts counting the offset pointer value of the SPE, triggered by the frame signal. Then, the coincidence detection unit 89 'detects whether or not the active pointer value read from the RAM 89' coincides with the counter value of the offset counter unit 97 '.

Further, the coincidence detection result is ANDed with the SPE enable signal in the AND circuit 99 ', and the ANDed result is generated and output as the J1 / V5 byte instruction signal. Here, when the J1 / V5 byte instruction signal is "1" (H level), it indicates that the data of the time slot of the multiplexed data is J1 / V5 byte. The J1 / V5 byte instruction signal and the SPE enable signal are used for the processing in the TU pointer processing unit 6 described above.

Next, FIG. 36 is a block diagram showing the structure of the TU pointer processing unit 6 focusing on the signal size recognition function portion. The TU pointer processing unit 6 shown in FIG.
Assuming that -1 frame of data is processed,
The above-mentioned mapping setting register group 100 'has three (3
TU3 / TUG3 setting register (TU3 / T)
UG3 # 1 to # 3) 123 and seven for each of these TU3 / TUG3 setting registers 123, for a total of 21 (21 channels) TU2 / TUG2 setting registers (TU2 / TUG2 # 1 to
# 7) 124 and the selector section 1 described above.
01 'is provided with a signal size recognition unit 125A.

Here, the TU3 / TUG3 setting register 1
23 stores information as to whether the TUG3 accommodated (mapped) in the VC4 frame is set to TU3 or TUG3. For example, when the value of the setting register 123 is "1", TU3 is multiplexed in the TUG3 frame, and "0" indicates that TU2 or TU12 is multiplexed in the TUG3 frame.

Also, the TU2 / TUG2 setting register 12
4 stores information on whether TUG2 mapped to TUG3 is set to TU2 or TUG2. For example, when the value of this setting register is "1", TU2 is set in the TUG2 frame. Is multiplexed, and a value of “0” indicates that TU12 is multiplexed in the TUG2 frame.

Further, the signal size recognizing section 125A recognizes the signal size of the corresponding channel based on the setting values stored in the setting registers 123 and 124, and TU3 / TU2 / TU12 for the address generating section 10. A setting signal is generated and output, and here, as shown in FIG. 36, selector circuits 125 to 127, a one-input inversion type AND circuit 128, and an all-input inversion type AND circuit 129.
Also, the function is realized by using the TUG3 address counter 15 and the TUG2 address counter 16 similar to those shown in FIG.

Here, the selector circuit 125 is TU3 / TUG3 corresponding to the channel indicated by the counter value of the TUG3 address counter 15 of the address generator 62-1.
The information in the setting register 123 is selected, and each selector circuit 126 has a TUG2 address counter 16
TU2 / TU corresponding to the channel indicated by the counter value of
The information of the G2 setting register 124 is selected,
The selector circuit 127 uses the TUG3 address counter 1
TU2 / T corresponding to the channel indicated by the counter value of 5
The information in the UG2 setting register 124 is selected.

In the TU pointer processing unit 6 configured as described above, the selector circuit 125 sets the set values (data "# 1 to # 3") of the TU3 / TUG3 setting register 123 according to the counter value of the TUG3 address counter 15. It is selected to generate the TU3 setting signal. Note that this TU setting signal indicates that the channel is TU3 only when it is "1".

Further, depending on the counter value of the TUG2 address counter 16, the TU2 / TUG setting register 124
(For TUG3 # 1, TUG3 # 2, TUG3 # 3)
Data "# 1 to # 7" are selected from the seven registers by the three selector circuits 126, and the three selection signals are selected by the selector circuit 127 according to the counter value of the TUG3 address counter 15.

The logical product of the inverted signal of the TU3 setting signal and the output signal of the selector circuit 127 is the AND circuit 1
At 28, a TU2 set signal is generated. The TU2 setting signal here indicates that the channel is TU2 only when it is "1". Further, the AND circuit 129 calculates the logical product of the inverted signal of the TU3 setting signal and the inverted signal of the output signal of the selector circuit 127, thereby generating the TU12 setting signal. In addition, this TU
Here, the 12 setting signal indicates that the channel is TU12 only when it is "1". Each of the above TU setting signals is used as a mapping setting signal for the processing in the POH termination processing unit 8 described later.

Next, FIG. 37 is a block diagram showing the configuration of the POH termination processing section 8 of the present embodiment. As shown in FIG. 37, the POH termination processing section (serial POH termination processing section) 8 is Timing generation unit 21, J1 / J2 byte termination processing unit 22, B3 / V5 byte termination processing unit 23, C
It has a 2 / V5 byte termination processing section 24 and a G1 / V5 byte termination processing section 25.

Here, the timing generation unit (POH timing signal serial generation unit) 21 is a J1V5TP signal (J1 / V5 byte designation signal) indicating the start position of the TU data, and an SP indicating the position of the payload data of the TU data.
E enable signal (SPEEN), TU signal size (T
U3 / TU2 / TU12) mapping signal for identifying the VC4 data that is multiplexed with TU data,
Received from the TU pointer processing unit 6 respectively, the PO of the TU
The generation of various timing signals necessary for the H termination processing and the phase adjustment are performed.

In other words, the timing generator 21 uses the J1 byte or V5 included in the multiplexed signal (VC4 signal).
Based on the timing signal indicating the position of the byte and the type information (mapping signal) of the multiplexed signal, a POH timing signal for processing in each of the termination processing units 22 to 25 is serially generated. The timing generation unit 21 can serially generate the POH timing signal required for each of the termination processing units 22 to 25 in common to each TU channel.

Further, the J1 / J2 byte termination processing unit 22
Is for serially performing termination processing [detection of LOM, CRC, TIM (TiM)] of J1 byte and J2 byte included in the multiplex signal, and the B3 / V5 byte termination processing unit 23 The included B3 byte and V5 byte BIP termination processing and the above B3 byte and V5 byte BIPPM termination processing are performed serially.

Furthermore, the C2 / V5 byte termination processing unit (U
The NEQ / SLM serial terminating unit) 24 serially terminates the UNEQ of C2 bytes and V5 bytes included in the multiplexed signal, and at the same time, the above C2 bytes and V
The 5-byte SLM termination processing is performed serially, and the G1 / V5-byte termination processing unit (FEBE / FERF
The serial termination processing unit) 25 includes G included in the multiplexed signal.
The 1-byte and V5-byte FEBE termination processing and the G1-byte and V5-byte FEBEPM termination processing are performed serially, respectively, and the G1-byte and V
The termination processing of the 5-byte FERF is performed serially.

Therefore, each of the termination processing units 22 to 25 described above is
38 is basically configured to have a POH termination arithmetic processing unit 26 and a storage unit 27 as shown in FIG.
Here, the POH termination calculation processing unit 26 determines that the TU3 / TU2
Multiplexed signal in which each channel of / TU12 is serially multiplexed (VC4 signal: if TU3, maximum 3 channels, TU
2 for maximum 21 channels, TU12 for maximum 63
POH termination calculation processing is performed on (multiplexed by the number of channels), and in the present embodiment, it is common to each of the above channels.

The storage unit 27 stores the calculation result in the POH termination calculation processing unit 26 for each channel, and the read TU channel address signal supplied from the TU pointer processing unit 6 and the write TU channel address signal, write enable signal (WE
According to N), the reading and writing of the calculation result can be freely controlled.

Then, the termination processing unit 22 shown in FIG.
In Nos. 25 to 25, when the POH termination calculation processing is performed on the VC4 signal, the POH termination calculation processing section 26 performs the POH termination calculation processing by using the storage information about the corresponding channel stored in the storage section 27. , POH obtained
By storing the termination calculation result in the storage area of the corresponding channel of the storage unit 27, the VC4 signal is converted into VC3 / VC.
It is possible to perform the POH termination arithmetic processing as it is without separating each channel of the 2 / VC12 signal.

FIG. 39 shows the POH termination arithmetic processing unit 26 described above.
39 is a block diagram showing the configuration of the storage unit 27.
As shown in FIG. 5, the POH termination arithmetic processing unit 26 includes a serial processing unit 26-1 and a flip-flop (FF) circuit 26-2 with an enable terminal, and the storage unit 27 stores R
RAM data holding unit 27-1 and F configured using AM
An FF data holding unit 27-2 configured by using an F circuit is provided.

Here, in the POH termination calculation processing section 26, the serial processing section 26-1 performs termination processing on the POH byte serially, and for example, J1 / J2.
The byte termination processing unit 22 performs termination processing on the J1 and J2 bytes, and the B3 / V5 byte termination processing unit 23 performs B3, V
Termination processing for 5 bytes, C2 / V5 byte termination processing unit 24 performs termination processing for C2, V5 bytes, G1 /
The V5 byte termination processing section 25 performs termination processing for G1 and V5 bytes, respectively.

Further, the FF circuit (latch section) 26-2 is
During the POH byte termination arithmetic processing in the serial processing unit 26-1, the data (calculation result) for the corresponding channel read from the storage unit 27 and the POH byte data to be processed in the VC4 data are temporarily stored. It is something that is stored (held). Then, this FF circuit 26-
If the data held in the storage unit 2 and the POH byte data to be processed in the VC4 data are latched at 2 at POH timing, the data required for the serial processing unit 26-1 is supplied according to the POH timing. The serial processing unit 26-1 operates only when necessary. That is, the FF circuit 26-2 lowers the operating frequency of the serial processing unit 26-1 to suppress its power consumption.

Further, in the storage unit 27, the RAM data holding unit 27-1 has TU channels (0 to 62 ch).
The data for holding the alarm protection stage number information and the like are stored. For example, as shown in FIGS. 40 (a) to 40 (t),
The RAM read address is used to read the data of the corresponding TU channel for serial processing, and the RAM write address and RAM write enable are used to write the alarm protection stage number information of the serially processed TU channel. There is. In this embodiment, the power consumption is suppressed by inputting the RAM clock only when the RAM data holding unit 27-1 is read and written to reduce the operating frequency.

Further, the FF data holding unit 27-2 has the TU
The alarm bit of the channel (0 to 62 ch) is held by the FF circuit.
As shown in, the FF read address and the FF read timing read the alarm bit of the TU channel that performs serial processing, and the FF write address and the FF write enable detect the alarm bit of the TU channel that performed serial processing. It is supposed to be written.

Hereinafter, the above-mentioned timing generator 21, J1
/ J2 byte termination processing unit 22, B3 / V5 byte termination processing unit 23, C2 / V5 byte termination processing unit 24, G1 / V
Details of the 5-byte termination processing unit 25 will be described item by item. (C2) Description of Timing Generation Unit 21 FIG. 41 is a block diagram showing the configuration of the timing generation unit 21 described above. The timing generation unit 21 shown in FIG.
An SPE count holding unit (RAM) 28, an SPE count value initialization unit 29, an SPE count value addition control unit 30, a timing signal generation processing unit 31, and an FF circuit 32 are provided.

Here, the SPE count value holding unit 28
The SPE count value addition control unit 30 holds the SPE count addition value for each TU channel and is a writable / readable storage unit that can supply the held data for each TU channel to the SPE count value initialization unit 29. , SPE
The count value initialization unit 29 uses the VC3 / VC2 in the VC4.
/ VC12 signal start position (J1 byte / V5 byte position) indicating the J1V5 timing signal, SPE
The count value is initialized.

Further, the SPE count value addition control unit 30
Is for performing addition control of the SPE count value based on the signal from the SPE count value initialization unit 29, and the timing signal generation processing unit 31 includes the count value initialization unit 29.
, A mapping signal (a signal indicating the type of VC signal of the same phase), an SPE enable signal (SPEEN),
Upon receipt of the TU address signal (TUAD), the following various POH timings for the processing in each of the termination processing units 22 to 25 (see FIG. 37) based on the signal from the count value initialization unit 29 and the mapping signal. It is for generating a signal.

J1 timing signal (J1TP): J1
A signal that indicates the position of the byte. B3 timing signal (B3TP): A signal indicating the position of the B3 byte. C2 timing signal (C2TP): a signal indicating the position of the C2 byte. G1 timing signal (G1TP): a signal indicating the position of the G1 byte. V5 timing signal (V5TP): A signal indicating the position of the V5 byte.

.J1J2 timing signal (J1J2T
P): A signal indicating the positions of the J1 and J2 bytes. -C2V5 timing signal (C2V5TP): C2, V
A signal indicating the position of 5 bytes. -G1V5 timing signal (G1V5TP): G1, V
A signal indicating the position of 5 bytes.

J1J2 write enable signal (J1J
2WEN): J1, J2 signal for instructing the data write timing after the byte termination processing. J1J2RAMCLK signal: the operation clock of the RAM in the J1 / J2 byte termination processing unit 22. BIPWEN signal: A signal for instructing the write timing of the BIP2 and BIP8 operation results.

BIPPMWEN signal: a signal for instructing the data write timing after the BIPPM addition processing. BIPPMRAMCLK signal: BIPPM holding RAM 58 in the B3 / V5 byte termination processing unit 23 described later-
1 operation clock. C2V5WEN signal: a signal for instructing the data write timing after the UNEQ, SLM termination processing.

C2V5RAMCLK signal: C described later
Operation clock of the RAM in the 2 / V5 byte termination processing unit 24. G1V5WEN signal: a signal for instructing the data write timing after the FERF termination process. G1V5RAMCLK signal: RAM operation clock in the G1 / V5 byte termination processing unit 25 described later.

Read TU address signal (RTUA
D): A signal for instructing reading of the termination processing result one cycle before of the TU channel on which POH termination processing is performed.・ TU address signal for writing (WTUAD): POH
A signal for instructing the writing of data after the processing of the TU channel that has been terminated. SPE enable signal (SPEEN): input S
A signal in which the phase of the PE enable signal is delayed.

SPE count value write TU address signal (CNTTUAD): a signal designating an address to write the SPE count value of the TU channel after the SPE count value addition control. -SPE count value write enable signal (CNTWE
N): A signal instructing to write the signal after the SPE count value addition control.

FEBEPMRAMCLK: G described later
Operation clock of the FEEBEPM holding RAM 93-1 in the 1 / V5 byte end processing unit 25. The FF circuit 32 delays the phase of the SPE count value before processing (one cycle before) from the SPE count holding unit 28 by one clock to adjust the input timing to the SPE count value initialization unit 29. is there.

In the timing generator 21 configured as described above, information (SPE count value) about the SPE start position (J1 byte, V5 byte) in the multiplexed signal
42 through the SPE count value initialization unit 29 and the SPE count value addition control unit 30.
While the SPE count holding unit 28 holds (reads / writes) for each TU channel at the operation timing as shown in (q), the processing is sequentially performed by each of the termination processing units 22 to 25. Various POH timing signals for the above are serially generated by the timing signal generation processing unit 31 common to each channel. Therefore, the serial processing described above can be realized with an extremely simple configuration.

For this reason, specifically, the timing generating section 21 is, as shown in FIG. 43, an overhead counter (OHCTR) RAM holding section 28 'and a phase shift section 3 as shown in FIG.
2 ', an overhead counter serial processing unit 33 is provided, and as the timing signal generation processing unit 31, a POH timing signal generation unit 34, a POH timing signal shift unit 35, a LOM holding RAM operation control unit 3
6, frame number (FRNO) holding RAM operation control section 37, BIP2 holding RAM operation control section 38, signal label (SL) holding RAM operation control section 39, FE
RF holding RAM operation control unit 40, reception expected value (EXP
1, 2) Holding RAM operation control unit 41, BIPPM holding RAM operation control unit 42, and FEBEPM holding RAM
The operation control unit 43 is provided.

The overhead counter serial processing section 33 corresponds to the SPE count value initialization section 29, SPE count value addition control section 30 and FF circuit 32 in FIG.
The AM holding unit 28 'holds the count value from the overhead counter serial processing unit 33 in the RAM,
It corresponds to the SPE count holding unit 28 in FIG.

FIG. 44 is a block diagram showing the detailed structure of the above-mentioned phase shift unit 32 '. As shown in FIG. 44, the phase shift unit 32' includes each signal [TUDT input from the TU pointer processing unit 6]. (TU data), TU address signal, SPE enable signal, J1V5 timing signal,
In order to delay the phase of the mapping signal (VC3TUG · VC2VC12)] by a required amount, a FF circuit 32 that delays the phase (C1 to C8) of the input signal by one master clock is provided for each of the above input signals. Is configured.

Phase shift unit 3 configured as described above
In 2 ', TU data of VC4 signal, TU address signal indicating TU channel, SPE enable signal indicating position of payload data of TU data, J1V5 timing signal indicating start position of TU data, TU3 / TU2 /
The phase of the mapping signal for identifying the TU 12 is shifted by a required amount in the FF circuit 32 having the corresponding number of stages, and used for serial processing in the overhead counter serial processing unit 33 and POH serial termination processing. .

Specifically, at this time, in the phase shift unit 32 ', the FF circuit 32 having a seven-stage configuration shifts the phase of the TU data by 7 clocks (C1 → C7), whereby the TU address signal (TUDTC7) of the phase C7 is obtained. ) Is generated,
By shifting the phase of the TU address signal by 1 to 8 clocks by the FF circuit 32 of 8 stages, the TU address signals (TUADC 1 to 8) of phases C1 to C8 are shifted.
To generate.

Further, by the FF circuit 32 having a seven-stage configuration, S
By shifting the phase of the PE enable signal by 7 clocks, the SPE enable signal of the phase C7 (SPEE
NC7), and the SPE enable signal (SPEENC3) of the phase C3 is generated by shifting the SPE enable signal by 3 clocks by the FF circuits 32 up to the third stage of the FF circuit 32 of the 7-stage configuration. To do.

Further, the J1V5 timing signal and the mapping signal (VC
By shifting the phase of 3TUG / VC2VC12) by 3 clocks respectively, the J1V5 timing signal (J1V5TPC3) of the phase C3 and the mapping signal (VC
3TUGC3 · VC2VC12C3) is generated. Next, FIG. 45 is a block diagram showing a detailed configuration of the overhead counter RAM holding unit 28 'and the overhead counter serial processing unit 33. As shown in FIG. 45, the overhead counter RAM holding unit 28' is an overhead counter. The overhead counter serial processing unit 33 includes a RAM 28'-1 and an inverting element 28'-2 that inverts the polarity of the input signal.
0 byte control unit (1 input inversion type AND circuit) 33-2,
TU3 detection unit (1-input inverting AND circuit) 33-3, T
U2 detection unit (1-input inversion AND circuit) 33-4, TU
12 detection unit (all input inversion type AND circuit) 33-5, maximum value setting unit 33-6, maximum value detection unit 33-9, count value addition unit 33-12, count value initialization control unit (1 input inversion type) AND circuit) 33-13.

Here, the overhead counter RAM 28 'in the overhead counter RAM holding unit 28'.
-1 holds information about what byte the SPE data byte is, with the J1, V5 byte as the 0th byte.
T of the phase C1 supplied from the above-mentioned phase shift unit 32 '
The U address signal (TUADC1) is the read address, the TU address signal (TUADC2) of the phase C2 is the write address, and the SPE enable signal (SPEEN) of the phase C3.
The signal obtained by inverting C3) by the inverting element 28'-2 is used as the write enable, and the master clock is used as the RAM clock.

Further, in the overhead counter serial processing section 33, the FF circuit 33-1 temporarily holds the information (count value) read from the overhead counter RAM 28'-1, and the 0 byte control section. 33-2 performs control to set the count value to 0 when a J1V5 timing signal (J1V5TPC3) indicating the start position of TU data is input, and POH termination processing is performed based on the signal (OHCTRC3) after this control. Various POH timings for are generated.

Further, the TU3 detecting section 33-3 detects that the TU channel to be processed is TU3, and performs an AND operation with the above VC3TUGC3 and VC2VC12C3 which are inverted (AND circuit). ), The TU2 detection unit 33-4 detects that the TU channel to be processed is TU2. The TU2 detection unit 33-4 calculates the logical product of the inverted version of VC3TUGC3 and VC2VC12C3. AN to take
The function is realized by using the D circuit.

Further, the TU12 detecting section 33-5 detects that the TU channel to be processed is TU12, and is the same as the one obtained by inverting the above VC3TUGC3.
AN that takes the logical product of the inverse of C2VC12C3
The function is realized by using the D circuit. The maximum value setting unit 33-6 selects the maximum value of the count value according to the setting of TU3 / TU2 / TU12. Here, the TU3 detecting unit 33-3 and the TU2 detecting unit 3 are selected.
3-4, a maximum value [TU3: 2FC (he
x), TU2: 1AB (hex), TU12: 08B
(Hex)] is selectively output through an AND circuit 33-7 and an OR circuit (logical sum circuit) 33-8.

Further, the maximum value detection unit 33-9 determines whether the count value after the control by the 0-byte control unit 33-2 matches the maximum value set (selected output) by the maximum value setting unit 33-6. The function is realized by using an EXOR circuit (exclusive OR circuit) 33-10 and an OR circuit 33-11. When the maximum value is detected by the maximum value detecting unit 33-9, it indicates that the SPE data is the last byte, and therefore the next same T
The SPE data of the U channel is J1, V5 bytes which is the head of the TU data.

Further, the count value adding unit 33-12 is set to 0.
+1 the count value after control by the byte control unit 33-2
The count value initialization control unit 33-13
When the maximum value is detected by the maximum value detecting unit 33-9 as described above, the overhead counter RAM 28'-1 because the SPE data to be processed next is J1, V5 bytes which is the head of the TU data. The count value to be held at is controlled to 0 indicating J1 and V5 bytes.

With such a configuration, in the overhead counter serial processing section 33, the overhead (SPE) count value (OHCT) required when the timing signal generation processing section 31 generates various POH timing signals.
RC3) can be generated serially. Next, FIG. 46 is a block diagram showing a detailed configuration of the POH timing signal generator 34 shown in FIG. 43.
The timing signal generator 34 is configured to include the following parts.

Decode circuit (DEC) 34-1: SP
The E count value (OHCTRC3) of 0 is detected (decoded). Decoding circuit (DEC) 34-2: which detects (decodes) 85 of the SPE count value (OHCTRC3). Decoding circuit (DEC) 34-3: Detects (decodes) 170 of the SPE count value (OHCTRC3).

Decode circuit (DEC) 34-4: SP
The E count value (OHCTRC3) of 255 is detected (decoded). Decoding circuit (DEC) 34-5: Detects (decodes) 107 of SPE count value (OHCTRC3). Decoding circuit (DEC) 34-6: which detects (decodes) 35 of the SPE count value (OHCTRC3).

TU3 detecting section (1 input inverting AND circuit) 34-7: This is for detecting that the TU channel to be processed is TU3. TU2 detector (1 input inverting AND circuit) 34-8:
It detects that the TU channel to be processed is TU2. -TU12 detector (all-input inverting AND circuit) 34-
9: Detects that the TU channel to be processed is TU12.

J1 condition detector (AND circuit) 34-1
0: Detects that the TU channel to be processed is the 0th byte of TU3. B3 condition detection unit (AND circuit) 34-11: Detects that the TU channel for processing is the 85th byte of TU3. C2 condition detector (AND circuit) 34-12: Detects that the TU channel for processing is the 170th byte of TU3.

G1 condition detection unit (AND circuit) 34-1
3: Detects that the TU channel to be processed is the 255th byte of TU3. .V5 condition detection unit (1 input inversion type AND circuit) 34-1
4: Detects that the TU channel to be processed is the 0th byte of TU2 / TU12. TU2J2 condition detection unit (AND circuit) 34-15: Detects that the TU channel to be processed is the 107th byte of TU2.

TU12J2 condition detection unit (AND circuit)
34-16: Detects that the TU channel for processing is the 35th byte of TU12. -J2 condition detection unit (OR circuit) 34-17: TU described above
The 2J2 condition detecting units 34-15 and TU12J2 condition detecting unit 34-16 detect that the J2 condition of TU2 / TU12 is detected.

J1 timing signal generator (AND circuit) 34-18: A signal indicating the position of the J1 byte is obtained by taking the logical product of the output signal of the J1 condition detector 34-10 and the SPE enable signal. To generate. B3 timing signal generator (AND circuit) 34-1
9: Output signal of the above B3 condition detection unit 34-11 and SP
By taking the logical product with the E enable signal, a signal indicating the position of the B3 byte is generated.

C2 timing signal generation section (AND circuit) 34-20: A signal indicating the position of the C2 byte is obtained by taking the logical product of the output signal of the C2 condition detection section 34-12 and the SPE enable signal. To generate. -G1 timing signal generator (AND circuit) 34-2
1: SP and the output signal of the above G1 condition detection unit 34-13
By taking the logical product with the E enable signal, a signal indicating the position of the G1 byte is generated.

V5 timing signal generator (AND circuit) 34-22: A signal indicating the position of the V5 byte is obtained by taking the logical product of the output signal of the V5 condition detector 34-14 and the SPE enable signal. To generate. -J2 timing signal generator (AND circuit) 34-2
3: SP and the output signal of the J2 condition detection unit 34-17 described above
A signal indicating the position of the J2 byte is generated by taking the logical product with the E enable signal.

J1J2 timing signal generation section (OR circuit) 34-24: generates a signal indicating the position of the J1 and J2 bytes. B3V5 timing signal generator (OR circuit) 34-2
5: Generates a signal indicating the position of the B3 · V5 byte. -C2V5 timing signal generator (OR circuit) 34-2
6: Generates a signal indicating the position of the C2 · V5 byte.

G1V5 timing signal generation unit (OR circuit) 34-27: generates a signal indicating the position of the G1V5 byte. The timing signal generation units 34-18 to 34 described above are provided.
-23 is configured to take the logical product of the input signal and the SPE enable signal because the detection units 34-10 to 34-1 corresponding to the timing that is not the SPE data of the TU.
This is to prevent the detection condition of each byte from being satisfied (the timing signal is generated at an incorrect timing) in No. 7 so that various timing signals can always be generated at accurate timing.

As a result, in the POH timing signal generation unit 34 described above, various POH timing signals (J1, B3, C2, G1, etc.) necessary for termination processing in each of the termination processing units 22 to 25 (see FIG. 37) described later are performed. A signal indicating the position of each byte such as V5, J2) can be serially generated. Next, FIG. 47 is a block diagram showing a detailed configuration of the POH timing signal shift unit 35 in FIG. 43. As shown in FIG.
5 includes FF circuits 35-1 to 35-8 that delay the phase of the input signal by one master clock, and various POH timing signals generated by the POH timing signal generation unit 34 described above. Is shifted to a phase suitable for POH termination processing in the termination processing units 22 to 25, respectively.

For example, the J1 timing signal (J1TPC
3) shows the phase C by the FF circuit 35-1 having a five-stage configuration.
By delaying 3 by 5 clocks, J1TPC8
Then, the B3 timing signal (B3TPC3) becomes B3TPC8 by delaying the phase C3 by 5 clocks by the FF circuit 35-2 having the five-stage configuration, and becomes C2.
The timing signal (C2TPC3) becomes C2TPC8 by delaying the phase C3 by 5 clocks by the FF circuit 35-3 having the five-stage configuration.

Further, the V5 timing signal (V5TPC
3), J12 timing signal (J12TPC3), B3
The V5 timing signal (B3V5TPC3), the C2V5 timing signal (C2V5TPC3), and the G1V5 timing signal (G1V5TPC3) respectively correspond to F
The phase C3 of the F circuits 35-4 to 35-8 is 2 to
Delayed by 5 clocks, V5TPC5-C
8, J12TPC3 to C8, B3V5TPC3 to C8,
C2V5TPC3 to C8 and G1V5TPC3 to C8.

Next, FIG. 48 is a block diagram showing the detailed structure of the LOM holding RAM operation control unit 36 in FIG. 43. As shown in FIG. 48, the LOM holding RAM operation control unit 36 of this embodiment is , An operation clock mask generation unit (OR circuit) 36-1, an FF circuit 36-2, a clock mask unit (1-input inverting OR circuit) 36-3, and an inverting element 36-4.

Here, the operation clock mask generator 36-
1 is the J12 timing signal (J12) generated by the phase shift in the POH timing signal shift unit 35 described above.
TPC5 to C8), from J12TPC5, the RA for holding LOM in the J1 / J2 byte termination processing unit 22 described later.
M50-1 (see FIG. 61) read address fetch clock mask, J12TPC6 to LOM holding R
A clock mask for fetching the write address of the AM50-1 from the J12TPC7 to the LOM holding RAM50-1
The write clock mask of the write data to is generated respectively.

The FF circuit 36-2 delays the output (clock mask) of the operation clock mask generator 36-1 by one master clock.
The clock mask unit 36-3 masks the master clock using the clock mask from the FF circuit 36-2, and generates clock edges (LOMCK) for reading and writing the LOM holding RAM 50-1. The inverting element 36-4 is a J12TP
The polarity of C8 is inverted to generate a negative write enable signal (XLOMWEN) for the LOM holding RAM 50-1.

As a result, the LOM holding RAM operation control section 36 described above causes the clock edge (LOMCK) and the write enable signal (XLOMW) generated as described above.
EN) can be used to operate the LOM holding RAM 50-1 at an optimum timing. Next, FIG. 49 is a block diagram showing the detailed configuration of the FRNO holding RAM operation control section 37 in FIG. 43. As shown in FIG. 49, the FRNO holding RAM operation control section 37 of the present embodiment.
Similarly to the above-described LOM holding RAM operation control unit 36, an operation clock mask generation unit (OR circuit) 37-1,
FF circuit 37-2, clock mask section (1 input inversion type O
R circuit) 37-3 and an inverting element 37-4.

Here, the operation clock mask generator 37-
1 is the JOH timing signal (J12TPC3) generated by the POH timing signal generation unit 34 and the POH.
Of the J12 timing signals (J12TPC5 to C8) that are phase-shifted and generated by the timing signal shift unit 35, the FRNO holding RAM 51-1 (FIG. 6) in the J1 / J2 byte termination processing unit 22 described later from J12TPC3.
2)) Read address fetching clock mask, J12TPC6 to FRNO holding RAM 51-1
Write address capture clock mask, J12
A write clock mask for writing data from the TPC 7 to the FRNO holding RAM 51-1 is generated.

The FF circuit 37-2 delays the output (clock mask) of the operation clock mask generator 37-1 by one master clock.
The clock mask unit 37-3 masks the master clock using the clock mask from the FF circuit 37-2, and clock edges (FRNOC) for reading and writing the FRNO holding RAM 51-1.
K1), and the inverting element 37-4 is
RAM51 for holding FRNO by inverting the polarity of 2TPC8
-1 negative write enable signal (XFRNOWE
N) is generated.

Thus, the FRNO holding RAM described above
The operation control unit 37 uses the clock edge (FRNOCK) and the write enable signal (XFR) generated as described above.
NOWEN) using the FRNO holding RAM 51-1
To operate at the optimal timing. Next, FIG.
50 is a block diagram showing a detailed configuration of the BIP2 holding RAM operation control unit 38 in FIG. 3, and as shown in FIG. 50, the BIP2 holding RAM operation control unit 38 of the present embodiment also includes the FRNO holding RAM operation control unit described above. Similar to 37, it is configured to include an operation clock mask generation unit (OR circuit) 38-1, an FF circuit 38-2, a clock mask unit (1 input inversion type OR circuit) 38-3, and an inversion element 38-4. There is.

Here, the operation clock mask generator 38-
1 is an SPE enable signal (SPE enable signal generated by being phase-shifted by the POH timing signal shift unit 35 described above).
Among the ENC5 to C8), a BIP2 holding R in the B3 / V5 byte termination processing unit 23 described later from SPEENC5.
AM54-1 (see FIG. 85) read address fetch clock mask, SPEENC6 to BIP2 holding RAM 54-1 write address fetch clock mask, SPEENC7 to BIP2 holding RAM5
The write clock mask of the write data to 4-1 is generated respectively.

Further, the FF circuit 38-2 delays the output (clock mask) of the operation clock mask generator 38-1 by one master clock,
The clock mask unit 38-3 masks the master clock using the clock mask from the FF circuit 38-2, and clock edges (BIPCK) required for reading and writing the BIP2 holding RAM 54-1.
And the inverting element 38-4 is a SPEE
BIP2 holding RAM 54-1 by inverting the polarity of NC8
Negative write enable signal (XBIPWENC
8) is generated.

Thus, the BIP2 holding RAM described above is stored.
The operation control unit 38 uses the clock edge (BIPC
K) and the write enable signal (XBIPWENC8), the BIP2 holding RAM 54-1 can be operated at an optimum timing. Next, FIG.
51 is a block diagram showing a detailed configuration of the SL holding RAM operation control unit 39 in FIG. 51. As shown in FIG. 51, the SL holding RAM operation control unit 39 of the present embodiment also has the above-mentioned BIP.
Similar to the 2 holding RAM operation control unit 38, an operation clock mask generation unit (OR circuit) 39-1, an FF circuit 39-
2, clock mask section (1 input inversion type OR circuit) 39-
3 and an inverting element 39-4.

Here, the operation clock mask generator 39-
1 is a C2V5 timing signal (C2V5 generated by being phase-shifted by the POH timing signal shift unit 35 described above).
Of the V5TPC5 to C8), the C2V5TPC5 capture clock mask of the read address of the SL holding RAM 72-1 (see FIG. 104) in the C2 / V5 byte termination processing unit 24 described later, and the writing of the SL holding RAM 72-1 from the C2V5TPC6. Address capture clock mask, C2V5TPC7 to SL holding RAM7
The write clock mask of the write data to 2-1 is respectively generated.

Further, the FF circuit 39-2 delays the output (clock mask) of the operation clock mask generator 39-1 by one master clock,
The clock mask unit 39-3 masks the master clock using the clock mask from the FF circuit 39-2, and generates clock edges (SLCK) for reading and writing the SL holding RAM 72-1. The inverting element 39-4 is a C2V5TPC
8 is inverted to generate a negative write enable signal (XSLWENC8) for the SL holding RAM 72-1.

As a result, the above-described SL holding RAM operation control section 39 uses the clock edge (SLCK) and write enable signal (XSLWENC8) to perform S
The L holding RAM 72-1 can be operated at an optimum timing. Next, FIG. 52 shows the FER in FIG.
52 is a block diagram showing a detailed configuration of the F holding RAM operation control unit 40. As shown in FIG. 52, the FER of the present embodiment is
The F holding RAM operation control unit 40 also uses the SL holding R described above.
Similar to the AM operation control unit 39, it includes an operation clock mask generation unit (OR circuit) 40-1, an FF circuit 40-2, a clock mask unit (1 input inversion type OR circuit) 40-3, and an inversion element 40-4. Is configured.

Here, the operation clock mask generator 40-
1 is a G1V5 timing signal (G1V5) generated by the phase shift of the POH timing signal shift unit 35 described above.
V5TPC5 to C8), G1V5TPC5 to G1V5TPC5 to the read address of the FERF holding RAM 96-1 (see FIG. 116) in the G1 / V5 byte termination processing unit 25, which will be described later, and G1V5TPC6 to F
A clock mask for fetching the write address of the ERF holding RAM 96-1 and a write clock mask for the write data from the G1V5TPC7 to the FERF holding RAM 96-1 are respectively generated.

Further, the FF circuit 40-2 delays the output (clock mask) of the operation clock mask generator 40-1 by one master clock,
The clock mask unit 40-3 masks the master clock by using the clock mask from the FF circuit 40-2, and clock edges (FERFC) necessary for reading and writing of the FERF holding RAM 96-1.
K1), and the inverting element 40-4 is
RAM9 for holding FERF by reversing the polarity of V5TPC8
6-1 negative write enable signal (XFERFW
ENC8) is generated.

As a result, the above-mentioned FERF holding RAM
The operation control unit 40 uses the clock edge (FERFC
K), write enable signal (XFERFWENC8)
Can be generated and the FERF holding RAM 96-1 can be operated at an optimum timing. Next, FIG. 53 is a block diagram showing a detailed configuration of the expected reception value holding RAM operation control unit 41 in FIG. 43. As shown in FIG. 53, the expected reception value holding RAM operation control unit 4 of the present embodiment is shown.
1 is a reception expected value read request detection unit (OR circuit) 41
-1, EXP1 expected value read operation clock mask generation unit (1 input inverting AND circuit) 41-2, EXP2 expected value read operation clock mask generation unit (AND circuit) 4
1-3, EXP1 Expected Value Setting Access Operation Clock Mask Generator (1 Input Inverted AND Circuit) 41-4, EXP
2 Expectation value setting access operation clock mask generator (AN
D circuit) 41-5, EXP1 clock mask generator (O
R circuit) 41-6, EXP2 clock mask generator (O
R circuit) 41-7, FF circuits 41-8, 41-9, EX
P1 clock mask section (1 input inverting OR circuit) 41-
10, EXP2 clock mask unit (1 input inversion type OR circuit) 41-11, EXP1 write enable generation unit (1
An input inversion type NAND circuit) 41-12 and an EXP2 write enable generation unit (NAND circuit) 41-13 are included.

Here, the reception expected value read request detection unit 4
Reference numeral 1-1 is for detecting the read timing of the expected reception value of the path trace data of J1 and J2 bytes and the read expected value of the signal label of C2 and V5 bytes.
1 Expected Value Read Operation Clock Mask Generator 41-2
If the most significant bit of the read address of the reception expected value of REXP ADC5 (see FIG. 70) described later is “0”, the EXP1 holding RAM 48-1 (see FIG. 70) reads out the reception expected value from the EXP1 holding RAM. RAM48
A read-out address of -1 is taken in to generate a clock mask.

The EXP2 expected value read operation clock mask generator 41-3 reads the expected reception value from the EP2 holding RAM 48-2 if the most significant bit of the read address of the expected reception value of the REXPADC5 is "1". Therefore, the read address of the EXP2 holding RAM 48-2 is fetched, and a clock mask is generated. The EXP1 expected value setting access operation clock mask generation section 41-4 receives from the software (microcomputer 10: see FIG. 29) side. If the most significant bit of MEXPAD of the read / write address on the software side is “0” when the expected value is set or the setting contents are read,
A clock mask for the EXP1 holding RAM 48-1 is generated so that reading / writing can be performed to the EXP1 holding RAM 48-1.

Further, the EXP2 expected value setting access operation clock mask generator 41-5 sets the most significant bit of MEXPAD to "1" when the expected received value is set or the setting contents are read from the software side. Then,
The clock mask of the EXP2 holding RAM 48-2 is generated so that the reading / writing can be performed to the EXP2 holding RAM 48-2.

Further, the EXP1 clock mask generator 41
-6 is a logical sum of the clock mask signals generated by the EXP1 expected value read operation clock mask generation unit 41-2 and the EXP1 expected value setting access operation clock mask generation unit 41-4 described above. The clock mask generation unit 41-7 takes the logical sum of the clock mask signals generated by the EXP2 expected value read operation clock mask generation unit 41-3 and the EXP2 expected value setting access operation clock mask generation unit 41-5. It is a thing.

Further, the FF circuit 41-8 has the above-mentioned EX
The output of the P1 clock mask generation unit 41-6 (EXP1 clock mask) is delayed by one master clock, and the FF circuit 41-9 outputs the output of the EXP2 clock mask generation unit 41-7 (EXP2 clock mask). ) Is delayed by one master clock.

Also, the EXP1 clock mask section 41-1
0 masks the master clock using the output (EXP1 clock mask) of the FF circuit 41-8, and E
The data stored in the XP1 holding RAM 48-1 (EX
P1) is used to generate a clock edge (EXP1CK) necessary for reading / writing, and the EXP2 clock mask unit 41-11 uses the output (EXP2 clock mask) of the FF circuit 41-9 to mask the master clock. The clock edge (EXP2CK) necessary for reading / writing the data (EXP2) held in the EXP2 holding RAM 48-2 is generated.

Further, the EXP1 write enable generation unit 41-12 writes data to the EXP1 holding RAM 48-1 if the most significant bit of MEXPAD is "0" when the expected reception value is written from the software side. RAM for holding EXP1 so that data can be written
The write enable (XEXP1WEN) of 48-1 is generated, and the EXP2 write enable generation unit 41-13 sets the most significant bit of MEXPAD to "1" when the expected reception value is written from the software side. If so, the EXP2 holding RAM is set so that the data is written to the EXP2 holding RAM 48-2.
The write enable (XEXP2WEN) 48-2 is generated.

As a result, the RA for holding the above-mentioned expected reception value is held.
The M operation control unit 41 uses the clock edges (EXP
1CK, EXP2CK), write enable (XEXP
1WEN, XEXP2WEN) to generate EX
RAM 48-1 for holding P1 and RAM 48 for holding EXP2
-2 can be operated at optimum timing.

FIG. 54 is a block diagram showing the detailed arrangement of the BIPPM holding RAM operation control unit 42 in FIG. 43. As shown in FIG. 54, the BIPPM of this embodiment is the same.
The holding RAM operation control unit 42 is, for example, S shown in FIG.
Similar to the L holding RAM operation control unit 39, an operation clock mask generation unit (OR circuit) 42-1 and an FF circuit 42-
2, clock mask unit (1 input inversion type OR circuit) 42-
3 and the inverting element 42-4.

Here, the operation clock mask generator 42-
1 is a B3V5 timing signal (B3V5T) generated by being phase-shifted by the POH timing signal shift unit 35.
Of PC5 to C8), B3V5TPC5 to B3V5TPC6 to BIPP from B3V5TPC5 to the read address of the BIPPM holding RAM 58-1 (see FIG. 87) in the B3 / V5 byte termination processing unit 23 described later.
A clock mask for fetching the write address of the M holding RAM 58-1 and a write clock mask for the write data from the B3V5TPC7 to the BIPPM holding RAM 58-1 are generated, and the BIPPM is counted from the BIPPM software notification request signal from the software side. A value read address fetching clock mask is generated.

The FF circuit 42-2 delays the output (clock mask) of the operation clock mask generator 42-1 by one master clock.
The clock mask unit 42-3 masks the master clock using the clock mask from the FF circuit 42-2, and clock edges (BIPPM) required for reading and writing of the BIPPM holding RAM 58-1.
CK), and the inverting element 42-4 is
RA for BIPPM retention by reversing the polarity of 3V5TPC8
M58-1 negative write enable signal (XBIP
PMWEN) is generated.

As a result, the RA for holding the BIPPM described above is obtained.
The M operation control unit 42 uses the clock edge (BIPPMCK) and the write enable signal (X
BIPPM holding RAM using BIPPMWEN)
It is possible to operate 58-1 at an optimum timing. Next, FIG. 55 is a block diagram showing a detailed configuration of the FEBEPM holding RAM operation control unit 43 in FIG.
As shown in FIG. 55, the FEBEPM holding RAM operation control unit 43 of the present embodiment also has the operation clock mask generation unit (OR circuit) 43-1 and FF, similarly to the BIPPM holding RAM operation control unit 42 described above. The circuit 43-2, the clock mask section (1-input inverting OR circuit) 43-3, and the inverting element 43-4 are provided.

The operation clock mask generator 43-
1 is a G1V5 timing signal (G1V5T) generated by being phase-shifted by the POH timing signal shift unit 35.
Of PC5 to C8), G1V5TPC5 to G1V5TPC6 to FE, which is a clock mask for fetching the read address of the FEBEPM holding RAM 93-1 (see FIG. 114) in the G1 / V5 byte termination processing unit 25 described later.
Capture clock mask of write address of BEPM holding RAM 93-1 from G1V5TPC7 to FEBE
The write clock mask of the write data to the PM holding RAM 93-1 is generated, and the FE is received from the FEBEPM software notification request signal from the software side.
The BEPM count value read address fetching clock mask is generated.

Further, the FF circuit 43-2 delays the output (clock mask) of the operation clock mask generation section 43-1 by one master clock,
The clock mask unit 43-3 masks the master clock by using the clock mask from the FF circuit 43-2, and the clock edges (FEBE) necessary for reading and writing of the FEBEPM holding RAM 93-1.
PMCK), and the inverting element 43-4
Reverses the polarity of G1V5TPC8 and writes the negative write enable signal (X
FEBEPMWEN).

As a result, the above-mentioned R for holding the FEBEPM is held.
The AM operation control unit 43 can operate the FEEBEPM holding RAM 93-1 at the optimum timing by using the clock edge (FEBEPMCK) and the write enable signal (XFEBEPMWEN) generated as described above. The overall operation of the timing generation section 21 will be briefly described below. First, the phase shift section 32 '.
56 (a) to 56 (h), TU data (here, J1 byte of VC3), TUAD, SPEEN, J1V5TP, VC3T.
Assuming that UG and VC2VC12 are respectively input, in the overhead counter serial processing unit 33, each unit operates at the timings shown in FIGS. 57 (a) to 57 (p).

Then, in the timing signal generation processing section 31, the POH timing signal generation section 34 operates as shown in FIG.
(A) to FIG. 58 (t), each part operates to generate various POH timing signals serially, and the LOM holding RAM operation control part 36, for example, FIG.
9 (a) to FIG. 59 (f), each unit operates at the timings shown in FIG. 9 (f) to clock edge (LOMC
K) and a write enable signal (XLOMWEN). The circled numbers (FIG. 45-, FIG. 45-, etc.) shown in FIGS. 57 to 59 correspond to the signals of the portions indicated by the circled numbers in the corresponding drawings.

As described above, according to the POH termination processing unit 8 of the present embodiment, the timing generation unit 21 causes various P Ps required for the POH termination processing in each of the termination processing units 22 to 25.
Since the OH timing signal can be serially generated in common to each TU channel, it is not necessary to provide circuits for generating the POH timing signal for the corresponding number of TU channels, thereby reducing the circuit scale and power consumption. It can be reduced significantly.

(C3) J1 / J2 byte end processing unit 22
FIG. 60 shows the J1 / J2 byte termination processing unit 22 shown in FIG.
62 is a block diagram showing a detailed configuration of the J1 / J2 byte termination processing unit 2 of the present embodiment, as shown in FIG.
2, the POH termination arithmetic processing unit 26 shown in FIG.
J1 and J2 byte serial termination processing unit 26 that serially terminates J1 byte and J2 byte included in the signal
In addition to being configured as A, the storage unit 27 shown in FIG. 38 stores the calculation result in the J1, J2 byte serial termination processing unit 26A for each TU channel, and
It is configured as a storage unit 27A capable of supplying storage information to the 1, J2 byte serial termination processing unit 26A.

The J1 and J2 byte serial termination processing section 26A is composed of a multi-frame pattern serial detection section 44 and a multi-frame number serial control section 4.
5, the LOM serial detection unit 46, the CRC serial detection unit 47, the expected reception value holding unit 48, and the TIM serial detection unit 49, the storage unit 27A, the LOM holding unit 50, the frame number (FRNO) holding unit 51. , And an alarm bit holding unit 52.

Here, in the J1 and J2 byte serial termination processing section 26A, the multi-frame pattern serial detection section 44 performs serial detection of the J1 and J2 byte multi-frame patterns, and the multi-frame number serial control section. The (multi-frame pattern number serial control unit) 45 serially controls the number of multi-frames of J1 and J2 bytes, and the LOM serial detection unit 46 serially detects the LOM of J1 and J2 bytes. It is a thing.

Also, the CRC serial detection unit 47
The CRC of 1 and J2 bytes is detected serially, and the expected reception value holding unit 48 holds the expected reception value of the path trace signal written / read by the maintainer from the software side. The serial detection unit 49 serially detects the TIM of the J1 and J2 bytes based on the expected reception value held in the expected reception value holding unit 48.

Further, in the storage unit 27A, the LOM holding unit 50 has the multi-frame pattern serial detection unit 4
The processing result (calculation result) in 4 can be held for each TU channel, and the storage information held one cycle (one frame) before can be supplied to the multi-frame pattern serial detection unit 44. 51 indicates the processing result in the multi-frame number serial control unit 45 as T
The storage information held for each U channel can be supplied to the multi-frame number serial control unit 45 and the expected reception value holding unit 48 while being held one cycle (one frame) earlier. , LOM serial detector 46, CRC serial detector 47 and TI
The processing result in the M serial detection unit 48 is held for each TU channel, and the storage information held one cycle (one frame) before is stored in the LOM serial detection unit 46, the CRC serial detection unit 47, and the TIM serial detection unit 48. It can be supplied.

That is, the above-mentioned storage unit 27A includes the multi-frame pattern serial detection unit 44, the multi-frame number serial control unit 45, and the LOM serial detection unit 4.
6, the calculation results of the CRC serial detector 47 and the TIM serial detector 49 are stored for each TU channel, and the multi-frame pattern serial detector 44, the multi-frame number serial controller 45, L
OM serial detector 46, CRC serial detector 47,
It is configured to supply stored information to the expected reception value holding unit 48 and the TIM serial detection unit 49.

As a result, in the J1 / J2 byte termination processing unit 22 described above, J1 included in the VC3-POH 235 is used.
Byte termination and VC2-POH236, VC12
-Termination processing of J2 bytes included in POH237 (included in the multiplexed signal of a lower group than the multiplexed signal including J1 bytes) is serially performed by the J1 and J2 byte serial termination processing unit 26A common to each channel. , LOM, CR
Various alarm information such as C, TIM, etc. can be stored in one J1, J
It can be obtained by the 2-byte serial termination processing unit 26A.

Details of each of the above parts will be described below. FIG. 61
Is a block diagram showing the detailed configurations of the multi-frame pattern serial detection unit 44 and the LOM holding unit 50 described above. As shown in FIG. 61, the multi-frame pattern serial detection unit 44 includes an FF circuit 44-1 with an enable.
(Corresponding to the FF circuit 26-2 shown in FIG. 39), 44-
2, 44-3, zero continuous count addition unit 44-4, zero continuous count reset unit (1 input inverting AND circuit) 4
4-5, decode circuits (DEC) 44-6 to 44-8,
Multi-frame head bit detection information reset unit (1 input inversion AND circuit) 44-9, multi-frame head bit detection information set unit (OR circuit) 44-10, frame number correction detection unit (AND circuit) 44-11, multi The frame pattern detecting unit (AND circuit) 44-12 is provided, and the LOM holding unit 50 is an LOM holding R.
It is configured with AM50-1.

Here, the LOM holding RAM 50-1 of the LOM holding unit 50 has the information necessary for the processing result of the multi-frame pattern serial detection unit 44, that is, the LOM, CRC, and TIM alarm detection performed by the J1 and J2 bytes. For holding the TU address signal (TUADC6) supplied from the phase shift unit 32 '(see FIG. 44) of the timing generation unit 21 as the read address and TUADC7.
Is used as the write address, and the LOM of the timing generation unit 21
XLOMWENC8 supplied from the holding RAM operation control unit 36 (see FIG. 48) is write enable, LOMC
K is used as a RAM clock.

Incidentally, this LOM holding RAM 50-1
In this embodiment, 21 bits of data are held, for example, as shown below. However,
The data to be stored does not have to be arranged in the following order. -Bit numbers 3-0: MSB bit "0" consecutive number information of J1 and J2 bytes-Bit number 4: Multiframe head bit detection information-Bit numbers 7-5: LOM protection stage number information-Bit numbers 14-8: CRC -7 Operation result information-bit number 15: 1 CRC mismatch detection information before multi-frame-bit number 16: 2 CRC mismatch detection information before multi-frame-bit number 17: expected received value mismatch detection information-bit numbers 20-18 In the multi-frame pattern serial detector 44, the FF circuit 44-1 of the multi-frame pattern serial detector 44 has a timing signal (J12TPC7: POH timing shown in FIG. 47) indicating the positions of the J1 and J2 bytes. (Generated by the signal shift unit 35), the LOM holding RAM 50-1 Of the read data (RLOMDTC
The data of the 4th to 0th bits in 7) is held, and the FF circuit 44-2 receives the VC4 data (TUDTTC7) with the above timing signal (J12TPC7).
To J1 and J2 byte data of MSB bit, and the FF circuit 44-3 holds the LOM alarm bit (RLOMC7) which is the processing result one frame before by the timing signal (J12TPC7). It is a thing.

Further, the zero continuous count adding unit 44-4
Is for incrementing "0" consecutive number information (count value) indicating how many times the MSB bits of the J1 and J2 bytes are consecutive "0". Note that this information is 4-bit information here, and if the count value "15" is incremented by 1, the count value is returned to "0". This is because a multi-frame consists of 16 bytes of J1 and J2 bytes [CRC byte (1 byte) and 15 bytes of trace data byte: see FIG. 12], and only the CRC byte has MSB bit “1”. Since all MSB bits of other trace data bytes are "0", J
The MSB bit sequence of the 1, J2 byte is "1000 0000 000
This is because it is sufficient to detect that it is 0 0000 ".

Further, the zero continuous count reset unit 44
-5 is for resetting the above "0" consecutive number information to "0" when the data "1" indicating that the CRC byte at the beginning of the multiframe is detected by the FF circuit 44-2 is held. Then, the data (“0” consecutive number information) after this processing is 0 in the LOM holding RAM 50-1 as described above.
It is designed to be written in the third bit.

Further, the decoding circuit (“0” detection section) 44
-6 is for detecting that the information on the number of consecutive "0" s after processing is "0" (decoding "0") and indicating the head position of the multi-frame pattern. The 14 "detection unit) 44-7 detects that the" 0 "consecutive number information after processing is" 14 "(decodes" 14 "), and the J1 and J2 bytes to be processed are included in the trace data. This is for indicating that it is the 14th byte, and the decoding circuit (“15” detection unit) 44-8 detects that the “0” consecutive count information after processing is “15” (“15”). J1 and J2 for decoding and processing
This is for indicating that the byte is the 15th byte in the trace data.

Further, the multi-frame head bit detection information reset unit 44-9 resets the head bit detection information of the preceding multi-frame pattern when the head position of the multi-frame pattern is detected. Bit detection information setting unit 44-10
Is when the "1" is held in the FF circuit 44-2 and when the information "0" consecutive times after the start bit is detected is "0".
If not, the leading bit of the current multiframe is detected.

Further, the frame number correction detection section 44-
11 indicates the multi-frame head bit detection information (F) when the multi-frame pattern out-of-sync alarm (LOM) is generated (when RLOMC7 is at the H level).
By detecting that the output information of the F circuit 44-1) and the "0" consecutive number information after processing (output information of the decoding circuit 44-7) are "14", M of J1 and J2 bytes is detected.
A sequence number of SB bits "10000000 0000 000" is detected, and a frame number correction request signal (FRNOSETC8) is generated so that the J1 and J2 bytes of the next frame can be processed as the 15th byte of the trace data byte.

Furthermore, the multi-frame pattern detection unit 4
4-12 is multi-frame head bit detection information (FF
By detecting that the output information of the circuit 44-1) and the "0" consecutive number information after processing (output information of the decoding circuit 44-8) are "15", the MSBs of the J1 and J2 bytes are detected.
A bit sequence "1000 0000 0000 0000" is detected to detect a multi-frame pattern (MFPATDETC8).

With the above-mentioned configuration, the multi-frame pattern serial detection section 44 has the LOM holding RAM 50-
While sequentially reading the "0" consecutive count information and the multi-frame head bit detection information from 1 to the previous frame, J
MSB bit sequence of 1, J2 byte "1000 0000 0000
By detecting "0000", it is possible to serially detect a multi-frame pattern of J1 and J2 bytes (path trace data) common to all TU channels.

Next, FIG. 62 is a block diagram showing the detailed structure of the above-mentioned multi-frame number serial control unit 45 and FRNO holding unit 51. As shown in FIG. 62, the multi-frame number serial control unit 45 is enabled. FF circuit (corresponding to FF circuit 26-2 shown in FIG. 39) 45-1, FF circuits 45-2 and 45-3, frame number control unit 45-4 and decoding circuit (DE
C) Comprised of 45-5 and 45-6, FRNO
The holding unit 51 includes a FRNO holding RAM 51-1.

Here, the FRNO holding RAM 51-1 of the FRNO holding unit 51 holds information (hereinafter referred to as frame number information) indicating which byte of the trace multi-frame the J1 and J2 bytes are. In the embodiment, for example, as shown in FIG. 63, frame number information of 4 bits (bit numbers 3 to 0) can be held.

The FRNO holding RAM 51-
1 is a TU address signal (TUAD) supplied from the phase shifter 32 '(see FIG. 44) of the timing generator 21.
C4) is a read address and TUADC7 is a write address, and the FRNO holding RAM of the timing generation unit 21
XFRN supplied from the operation control unit 37 (see FIG. 49)
Write enable for OWENC8 and RA for FRNOCK
It operates as an M clock and, for example, as shown in FIG.
At the detection timing of the J1 byte of TU3 and the J2 byte of TU2 / TU12, the number of the next J1 / J2 byte is read out, and the J1 byte of TU3, TU2 /
At the detection timing of J2 byte of TU12, the next J1 /
The byte number of the J2 byte is written.

The relationship between the frame number information and the trace multiframe is the frame number information "0".
Is CRC byte, frame number information "1" to "1"
5 "indicates the 1st to 15th bytes of the trace data byte, and each frame number information" 0 "to" 15 "
Is the FRNO in the correspondence relationship shown in FIG.
It is held in the holding RAM 51-1.

On the other hand, in the multi-frame number serial control unit 45, the FF circuit 45-1 has a timing signal indicating the position of the J1 and J2 bytes (J12TPC5: generated by the POH timing signal shift unit 35 shown in FIG. 47). Then, the 3rd to 0th bit data (the frame number information) of the read data from the FRNO holding RAM 51-1 is held.

The FF circuit 45-2 delays the phase of the frame number information held by the FF circuit 45-1 by one master clock.
The circuit 45-3 further delays the frame number information held by the FF circuit 45-2 by one master clock, and the frame number control unit 45
-4 is for adding +1 to the count value of the frame number information held in the FF circuit 45-3.

The frame number control unit 45-
4 is a frame number correction request signal (FRNO) supplied from the multi-frame pattern detection unit 44-11 of the multi-frame pattern serial detection unit 44 shown in FIG.
When SETC8) is "1", the count value of the frame number information is updated to "15".

Further, the decoding circuit (“0” detection section) 4
In 5-5, the count value of the frame number information is “0”
Signal indicating that the J1 and J2 bytes to be processed are CRC bytes (CRCTPC
8) is generated, and the decoding circuit (“15” detection unit) 45-6 detects that the count value of the frame number information is “15” and performs the processing J1,
A signal (FRNO15TPC8) indicating that the J2 byte is the 15th byte of the trace data byte, that is, the last byte of the multi-frame pattern is generated.

With the above configuration, in the multi-frame number serial control unit 45, the FRNO holding RAM 51
The frame number information of the previous frame is sequentially read from -1, and the frame number information for the current multi-frame is updated based on the frame number information to serially control the multi-frame number common to each TU channel. Can be done.

Next, FIG. 66 is a block diagram showing a detailed structure of the LOM serial detection unit 46 in FIG. 60. As shown in FIG. 66, the LOM serial detection unit 46 of the present embodiment has the enable FF circuit 46. -1,46-2,
LOM protection stage number adding unit 46-3, decoding circuit (DE
C) 46-4, 46-5, addition condition detection unit (exclusive NOR circuit) 46-6, LOM detection 7-stage detection unit (AND
Circuit) 46-7, LOM release three-stage detection unit (AND circuit)
46-8, state transition occurrence detector (OR circuit) 46-9,
LOM protection stage number information reset unit (1 input inverting AND circuit) 46-10, state transition unit (exclusive OR circuit) 46
-11 and a bypass control section (selector) 46-12.

Here, the FF circuit 46-1 is connected to J1, J2
Timing signal (J12TPC7:
(Supplied from the POH timing signal shift unit 35 shown in FIG. 47), and the LOM holding RAM 50- shown in FIG.
7 out of the read data from 1 (RLOMDTC7)
The FF circuit 46-2 holds the fifth bit data (LOM protection stage number information). The FF circuit 46-2 holds the LOM alarm bit (RLOMC7), which is the processing result of the previous frame, with the timing signal (J12TPC7). It is a thing.

Further, the LOM protection stage number addition unit 46-3 is
The count value of the LOM protection stage number information read from the LOM holding RAM 50-1 is incremented by 1, and the decoding circuit (“6” detection unit) 46-4 determines that the count value of the read LOM protection stage number information is The decode circuit (“2” detection unit) 46-5 detects that the count value of the read LOM protection stage number information is “2”.

Furthermore, the addition condition detecting unit 46-6 is
A multi-frame pattern was detected while M was generated, and a multi-frame pattern was not detected while LOM was not generated (when RLOMC7 is "0") (MFPA).
TDETC8 detects "0"), and L
The OM detection seven-stage detection unit 46-7 includes a decoding circuit 46-4.
In addition, when the addition condition is detected continuously for 6 multiframes in a state where it is not a multiframe pattern, and when the addition condition is generated for the current multiframe as well, it is detected that the addition condition is generated continuously for 7 multiframes and LOM detection is performed. Is to do.

Further, the LOM release third stage detecting section 46-8 is
While the LOM is occurring, the decoding circuit 46-5 detects the addition condition for two consecutive multi-frames, and when the addition condition is generated for the current multi-frame, it is detected that the addition condition is consecutively generated for three multi-frames. Then, the LOM cancellation is performed, and the state transition occurrence detection unit 46-9
The LOM detection seven-stage detection unit 46-7 and the LOM cancellation three-stage detection unit 46-8 detect that a condition for LOM detection or cancellation has occurred.

Furthermore, the LOM protection stage number information reset unit 4
6-10 when the addition condition is not detected by the addition condition detection unit 46-6 described above, and when the state transition occurrence detection unit 46-
When the state transition occurrence is detected in 9, the count value of the LOM protection stage number information is reset to “0”,
The state transition unit 46-11 includes a state transition occurrence detection unit 46-9.
When the occurrence of the state transition is detected in, the polarity of the alarm bit of the LOM is inverted, and the state transition between LOM occurrence and LOM non-occurrence is performed.

The bypass control section 46-12 has J1, J2
LOM at 15th byte of byte trace data
The above-described LOM protection stage number information reset unit 46-
While writing the processing result of No. 10 to the LOM holding RAM 50-1 and writing the processing result of the state transition unit 46-11 to the alarm bit holding unit 52, when it is other than the 15th byte, the LOM holding RAM 50-1 and the alarm bit The information read from the holding unit 52 is directly written in the LOM holding RAM 50-1 and the alarm bit holding unit 52.

With the above-mentioned configuration, the LOM serial detection unit 46 indicates the LOM protection stage number information of the previous frame from the LOM holding RAM 50-1 and the alarm bit holding unit 52, and the LOM alarm bit (whether LOM is occurring / not occurring). (State information) is sequentially read, and LOM update processing for the current multiframe is performed based on these pieces of information to serially LOM common to all TU channels.
Can be detected.

Next, FIG. 67 is a block diagram showing the detailed structure of the CRC serial detection unit 47 in FIG. 60. As shown in FIG. 67, the CRC serial detection unit 47 of this embodiment is provided with an enable FF circuit 47. -1 to 47-3,
CRC calculation result reset unit (AND circuit) 47-4, C
RC data insertion part (80 hex insertion part) 47-5, CR
C calculation unit 47-6, mismatch detection unit 47-7, protection stage control unit 47-8, CRC error detection three-stage detection unit (1 input inverting AND circuit) 47-9, CRC error cancellation three-stage detection unit (1 Input inversion NOR circuit) 47-10, state transition occurrence detection unit (OR circuit) 47-11, state transition unit (exclusive OR circuit) 47-12, and bypass control unit (selector)
47-13.

Here, the FF circuit 47-1 is connected to J1 and J2.
Timing signal (J12TPC7:
(Supplied from the POH timing signal shift unit 35 shown in FIG. 47), and the LOM holding RAM 50- shown in FIG.
1 of the read data from 1 (RLOMDTC7)
6th to 8th bit data (CRC-7 operation result information, 1
The CRC mismatch detection information before the multi-frame and the CRC mismatch detection information before the two multi-frames are held.

Further, the FF circuit 47-2 receives the TU data (TUDTC) with the timing signal (J12TPC7).
7) holds J1 and J2 byte data, and the FF circuit 47-3 uses the timing signal (J12
TPC7) holds the CRC alarm bit (RCRCC7) which is the processing result of the previous frame.
The RC operation result reset unit 47-4 performs processing J
R for holding LOM when 1,2 bytes are CRC bytes
CR of previous multi-frame read from AM50-1
The C calculation result is reset.

Further, the CRC data insertion unit 47-5 is
The CRC byte data is rewritten to 80 hex, and the CRC calculation unit 47-6 sets the CRC byte data to 80 hex by the CRC data insertion unit 47-5 and sets the trace data 1 to 15 bytes to the generation polynomial X ^7.
CRC-7 calculation is performed by + X ³ +1 and the calculation result is written in the LOM holding RAM 50-1.

The mismatch detection unit 47-7 detects the mismatch between the CRC calculation result of the previous multi-frame and the CRC value of the 2nd to 8th bits of the CRC byte, and the protection stage control unit 47-8. The output signal of the non-coincidence detection unit 47-7 is used as the 15th bit data of the LOM holding RAM 50-1, and the 15th bit data read from the LOM holding RAM 50-1 is transferred to the 16th bit. Is.

Further, the CRC error detection three-stage detection unit 47
-9 indicates a mismatch detection unit 47-when a CRC error has not occurred.
7, the CRC mismatch detection information one frame before and the CRC mismatch detection information two frames before are all CRC.
When the mismatch is detected, it is detected that the CRC match has occurred in three consecutive multi-frames.
While the CRC error is occurring, the C error cancellation three-stage detection unit 47-10 detects that the detection result by the mismatch detection unit 47-7, the CRC mismatch detection information of one frame before, and the CRC mismatch detection information of two frames before are all CRC matched. If detected, C
The CRC error is canceled by detecting that the RC match has occurred continuously for three multiframes.

Further, the state transition occurrence detecting section 47-11 is
The CRC error detection three-stage detection unit 47-9 and the CRC error cancellation three-stage detection unit 47-10 detect that a CRC error is detected or canceled, and the state transition unit 47-12 detects this state. When a state transition occurrence is detected by the transition occurrence detecting unit 47-11, the polarity of the CRC error alarm bit is inverted to indicate that a CRC error is occurring ⇔ C
The state transition is performed while the RC error is not occurring.

The bypass control section 47-13 has J1, J2
In order to update the CRC error at the CRC byte of the byte, only when processing the CRC byte,
The processing result of the protection stage control unit 47-8 is stored in the LOM holding RAM.
50-1 while writing the processing result of the state transition unit 47-12 to the alarm bit holding unit 52,
RAM 50 for holding LOM when it is not a CRC byte
-1 and the information read from the alarm bit holding unit 52 is directly written to the LOM holding RAM 50-1 and the alarm bit holding unit 52.

With the above-described configuration, the CRC serial detection unit 47 receives the CRC-7 of the previous frame from the LOM holding RAM 50-1 and the alarm bit holding unit 52, respectively.
Computation result information, CRC mismatch detection information one multiframe before, CRC mismatch detection information two multiframes before, C
RC alarm bits (status information indicating whether or not a CRC error is occurring / not occurring) are sequentially read out, and a CRC calculation (update of the CRC error) for the current multiframe is performed based on each of these pieces of information, thereby making it common to all TU channels. The CRC can be detected serially with.

By the way, the CRC serial detecting section 47 shown in FIG. 67 is, for example, as shown in FIG. 68, the above-mentioned protection step controlling section 47-8 and CRC error detecting three-step detecting section 47-.
9, CRC error cancellation three-stage detection unit 47-10 and state transition occurrence detection unit 47-11, instead of CRC protection stage number addition unit 47-14, decoding circuit 47-15, addition condition detection unit (exclusive OR circuit ) 47-16, detection / cancellation three-stage detection unit (AND circuit) 47-17 and protection stage number reset unit (one-input inversion AND circuit) 47-18.

However, in this case, the LOM holding RAM
The CRC mismatch detection information of one multi-frame before and the CRC mismatch detection information of two multi-frames held in 50-1 are used as the CRC protection stage number information indicating how many times the CRC match / mismatch successively occurs. . Where CR
The C protection stage number adding unit 47-14 is used for the LOM holding RAM 5
The number of CRC protection stages read from 0-1 is incremented by 1, and the decoding circuit (“2” detection unit) 47-15
Is for detecting that the CRC protection stage number information is "2", and the addition condition detecting unit 47-16 detects that the mismatch detection unit 47-7 has detected a match while the CRC error is occurring and the CRC error. The non-matching detection unit 47-7 detects that the non-matching is detected during the non-occurrence.

The detection / cancellation three-stage detection section 47-17 uses the CR
C error detection / release condition detection
The protection stage number reset unit 47-18 resets the CRC protection stage number information. As a result, the above-mentioned C
The RC serial detector 47 can also detect the CRC serially, as in the case shown in FIG.

Next, FIG. 69 is a block diagram showing a detailed structure of the TIM serial detecting section 49 in FIG. 60. As shown in FIG. 69, the TIM serial detecting section 49 of the present embodiment includes an enable FF circuit 49. -1 to 49-4,
Mismatch detection unit 49-5, Mismatch detection display unit (OR circuit)
49-6, Mismatch detection display reset unit (1 input inversion type A
ND circuit) 49-7, addition condition detection unit (exclusive OR circuit) 49-8, TIM protection stage number addition unit 49-9, decoding circuits 49-10, 49-11, TIM detection 7 stage detection unit (AND circuit) ) 49-12, TIM release three-stage detector (A
ND circuit) 49-13, state transition occurrence detection unit (OR circuit) 49-14, TIM protection stage number information reset unit (1 input inversion AND circuit) 49-15, state transition unit (exclusive OR circuit) 49- 16 and a bypass control section (selector) 49-17.

Here, the FF circuit 49-1 has J1, J2
Timing signal (J12TPC7:
In the POH timing signal shift unit 35 shown in FIG. 47), the 20th to 17th bit data (reception expected value mismatch detection information, TIM protection) of the read data (RLOMDTC7) from the LOM holding RAM 50-1 is received. FF circuit 49-2 for holding the stage number information).
Is to hold J1 and J2 byte data from the TU data (TUDTC7) with the timing signal (J12TPC7).

Further, the FF circuit 49-3 performs processing with the timing signal (J12TPC7) J1, J2.
The FF circuit 49-4 holds the byte expected reception value (REXPDTC7: 7 bits), and the FF circuit 49-4 holds the TIM alarm bit (RTIMC7) which is the processing result of the previous frame with the timing signal (J12TPC7). Is.

Further, the inconsistency detecting section 49-5 detects inconsistency between 7 bits of the above-mentioned expected reception value and 2 to 8 bits of J1 and J2 bytes. The mismatch detection unit 49-5 generates a signal indicating that a mismatch between the reception trace data of the current multiframe and the expected reception value is detected. Here, the exclusive OR circuit 49-5A is used. The function is realized by the OR circuit 49-5B.

Also, the mismatch detection / display reset unit 49-7
Is a CRC byte which is the start position of the multi-frame, a CRC byte mismatch detection display which does not need to be compared with the expected reception value, and the LOM holding RAM 50-1.
This is for resetting the mismatch detection display of the previous multi-frame read out by the addition condition detection unit 49-8.
Indicates that a reception value mismatch is detected while TIM, which is a TIM detection condition, is not generated, and T that is a TIM cancellation condition.
This is to detect that the reception value match is detected during the IM occurrence.

Further, the TIM protection stage number addition unit 49-9
Indicates that the count value of the TIM protection stage number information is incremented by 1, and the decoding circuit (“6” detection unit) 49-10 detects that the count value of the read TIM protection stage number information is “6”. The decoding circuit (“2” detection unit) 49-11 detects that the count value of the read TIM protection stage number information is “2”.

Also, the TIM detection 7th stage detection section 49-12
When the decoding circuit 49-10 detects the addition condition for 6 multiframes in succession, and the addition condition also occurs in the current multiframe, it detects that the addition condition has occurred for 7 multiframes in succession. TIM detection is performed by the TIM release third stage detection unit 49-13.
While the TIM is being generated, the above-mentioned decoding circuit 49-11
When an addition condition is continuously detected in 2 multiframes and an addition condition occurs in the current multiframe, 3
The TIM is released by detecting that an addition condition is generated continuously in multiple frames.

Further, the state transition occurrence detecting section 49-14
Is the TIM detection 7-stage detection unit 49-12 and the TIM described above.
The cancellation three-stage detection unit 49-13 detects that TIM detection or cancellation has occurred, and the addition condition detection unit 49-8 detects no addition condition in the TIM protection stage number information reset unit 49-15. Time and when the state transition occurrence detection unit 49-14 detects the occurrence of a state transition,
The count value of the protection stage number information is reset to "0".

The state transition section 49-16 inverts the polarity of the alarm bit of the TIM when the state transition occurrence detection section 49-14 detects the occurrence of the state transition, and
The bypass control unit 49-17 performs a state transition between the occurrence of M and the absence of TIM, and the bypass control unit 49-17 updates the TIM at the 15th byte of the trace data of J1 and J2 bytes. The processing result of the TIM protection stage number information reset unit 49-15 is written into the LOM holding RAM 50-1 only when performing the processing of
The processing result of the state transition unit 49-16 is written to the alarm bit holding unit 52, and when the data other than the 15th byte is written, LO
The information read from the M holding RAM 50-1 and the alarm bit holding unit 52 is the LOM holding RAM 50-
1 and the alarm bit holding unit 52.

With the above-described structure, the TIM serial detection unit 49 of this embodiment has the LOM holding RAM 50-1,
From the alarm bit holding unit 52, the T
The IM protection stage number information and the TIM alarm bit (status information of TIM occurring / not occurring) are sequentially read out, and the TIM protection stage number information for the current multiframe is updated on the basis of each of these information to thereby update each TU channel. The TIM can be commonly and serially detected.

Next, FIG. 70 is a block diagram showing the detailed structure of the expected reception value holding unit 48 in FIG.
As shown in FIG.
First reception expected value (EXP1) holding RAM 48-1, second reception expected value (EXP2) holding RAM 48-2, signal label (SL) reception expected value MSB bit holding unit (F
F circuit) 48-3 to 48-5, MSB bit software notification selection unit 48-6, reception expected value software notification selection unit (selector) 48-7, SL reception expected value read address control unit (1 input inversion type AND circuit) ) 48-8, FF circuit 48-
9, 48-10, decoding circuits 48-11 to 48-1
3, an MSB bit selection unit 48-14 and an expected reception value selection unit (selector) 48-15.

Here, the EXP1 holding RAM 48-1
Holds an expected reception value of the signal label of TU channel = 0 to 62 ch and an expected reception value of the 1st to 7th bytes of the trace data when the STM-1 frame is considered as the reception multiplexed signal. Write enable for XEXP1WEN supplied from the RAM operation control unit 41 for holding expected reception value of the generation unit 21 (see FIG. 53), E
The XP1CK operates as a RAM clock, and the expected SL reception value [EXP1: signal label (SL), path trace data (TR) in units of 7 bits is displayed in a corresponding address (MEXPAD to be described later) area, for example, as shown in FIG.
C)] is sequentially written.

The EXP2 holding RAM 48-2 is
TU channel = 0 to 62 ch trace data 8 to
It holds the reception expectation value of the 15th byte, and similarly operates by using XEXP2WEN supplied from the reception expectation value holding RAM operation control unit 41 of the timing generation unit 21 as the write enable and EXP2CK as the RAM clock, and corresponding. In the address (MEXPAD) area, for example, as shown in FIG. 72, the SL reception expected value (EXP) is increased by 7 bits.
2: TRC) are sequentially written.

At this time, the RAM address (M
The relationship between the (EXPAD), the frame number, and the TU channel is as shown in FIG. 75 in this embodiment. That is, the expected reception value holding unit 48 of this embodiment generally has a maximum of 512 addresses in the RAM according to its specifications, and therefore 1024 necessary for holding all the expected reception values is required.
In order to obtain the address, two RAMs for holding the expected reception value are prepared in this way. Then, in the present embodiment, for example, as shown in FIGS.
The MSB bit of the address contents (address bits) of -1, 48-2 controls reading (writing) of the RAMs 48-1, 48-2 (see FIG. 73 for operation timing) (access switching). . It should be noted that if there is a RAM having a capacity capable of holding all the expected reception values, it is needless to say that one RAM can be used without preparing two RAMs as described above.

Further, the SL reception expected value MSB bit holding unit 48-3 holds the MSB bit of the SL reception expected value of TU channel = 0ch, and the SL reception expected value MSB bit holding unit 48-4 is TU channel = 1
It holds the MSB bit of the SL reception expected value of ch, and the SL reception expected value MSB bit holding unit 48-5
It holds the MSB bit of the SL reception expected value of TU channel = 2ch.

That is, the expected reception value holding unit 48 needs 8 bits for the SL reception expected value when the input multiplexed signal is TU3, but as described above, the EXP1 holding RAM 48-1 having the 7-bit configuration lacks bits. Therefore, each SL reception expected value MSB bit holding unit 48-3 to 48-
In FIG. 5, the expected reception value of the 8th bit is held for the expected reception value of TU3. In addition, the above E
RAM for holding XP1 48-1, RAM for holding EXP2 RAM4
8-2, SL reception expected value MSB bit holding unit 48-3 to
The setting of the expected reception value to 48-5 and the reading of the setting contents are performed from the software side.

Further, the MSB bit software notification selection unit 48
-6 is for selecting when the software reads the setting contents of the SL reception expected value of TU channels = 0 to 2 ch, and here, AND circuits 48-6A to 48-.
6C and the OR circuit 46-6D, the function is realized, and the reception expected value software notification selection unit 48-7 reads out the setting content of the reception expected value set by the software, and the EXP1 holding RAM 48-1. , EXP2 holding RAM
48-2, M of the address signal (MEXPAD) indicating the write / read address by software.
The SB bit is used to select the read data on the RAM side that has been correctly read.

Further, the SL reception expected value read address control unit 48-8, when reading the SL reception expected value for performing the SLM process, has a timing signal (C2V5TPC5: FIG. 47) indicating the position of the C2, V5 bytes.
The frame number information (FRNODTC5) read from the FRNO holding unit 51 (FRNO holding RAM 51-1: see FIG. 62) is masked by the POH timing signal shift unit 35 shown in FIG. It controls to turn on.

10 bits of 4 bits which performed this control and 6 bits of the TU address signal (TUADC5)
10-bit expected receive value read address (REXPAD
C5) is created. Further, when the SL reception expected value is read by this control, the upper 4 bits of the 10-bit reception expected value read address become “0000”,
The SL reception expected value is read by 10 bits of TUAD 6 bits indicating the TU channel to be processed.

The FF circuit 48-9 delays the phase of the 10-bit expected reception value read address by one clock with the master clock.
Is to delay the phase of the 10-bit received expected value read address by one clock with the master clock. Further, a decoding circuit (“0” detection unit) 48-11
Is for detecting that the 10-bit reception expected value read address is "0", and the decoding circuit ("1"
The detection unit) 48-12 detects that the 10-bit reception expected value read address is "1", and the decoding circuit ("2" detection unit) 48-13 detects the 10-bit reception expected value read address. Is "2".

Further, the MSB bit selection unit 48-14 is
TU channel = 0 to 2ch is selected to read the setting content of the SL reception expected value. Here, AND is selected.
Circuits 48-14A to 48-14C and OR circuit 48-1
The function is realized by using 4D, and the reception expected value selection unit 48-15 uses the EXP1 holding RAM 48 with 9 bits of the reception expected value read address of 10 bits.
-1, the expected reception value is read from the RAM 48-2 for holding EXP2, and the expected reception value read by the MSB bit of the 10-bit expected reception value read address is selected. The 7-bit output signal of 15 is the expected value of the path trace data reception (REX
PDTC 7), and the TIM serial detection unit 4 described above
9 is notified as the trace data reception expected value, and an 8-bit signal obtained by adding the output signal of the MSB bit selection unit 48-14 to the output signal 7 bits is the SL reception expected value (REX.
As PSLC7), C2 / V5 described later in FIG.
The SLM detection unit 73 of the byte termination processing unit 24 is notified.

With the above configuration, the expected reception value holding unit 48 of this embodiment has the TIM serial detection unit 49, C2 /
The V5 byte termination processing unit 24, various expected reception values required for processing on the software side can be serially held and supplied for each TU channel. Next, FIG. 77 is a block diagram showing a detailed configuration of the alarm bit holding unit 52 in FIG. 60. As shown in FIG. 77, the alarm bit holding unit 52 of the present embodiment has the TIM alarm bit holding unit 5
2-1, CRC alarm bit holding unit 52-2, LOM
Alarm bit holding unit 52-3, alarm bit write address control unit (1 input inversion type OR circuit) 52-4,
Write enable generator [decode circuit (DEC)] 5
2-5, alarm bit read address control unit (1 input inversion type OR circuit) 52-6, read select generation unit (DEC) 52-7, TIM select unit (selector) 5
2-8, CRC select unit (selector) 52-9, LO
M selection unit (selector) 52-10, line switching information read selection generation unit (DEC) 52-11, line switching information selection unit (selector) 52-12, software notification read selection generation unit (DEC) 52-13 and software It is provided with a notification selection unit (selector) 52-14.

Here, the TIM alarm bit holding unit 52
-1 holds the TIM alarm bits of TU channels = 0 to 62 channels by the 63 FF circuits 52A, and the CRC alarm bit holding unit 52-2 is
TU channel = 0 to 6 by 63 FF circuits 52B
The 2ch CRC alarm bit is held, and the LOM alarm bit holding section 52-3 holds the LOM alarm bit by the 63 FF circuits 52C.

Further, the alarm bit write address control unit 52-4 performs processing when the alarm bit write timing (J12TPC8) is "1".
Output the contents of the channel (TUADC8), J12T
When the PC8 is "0", the output signal is controlled to 63 ("111111" in binary display). Further, the write enable generator 52-5 outputs the output signal of the alarm bit write address controller 52-4 to 0.
In the case of ~ 62, a write enable signal for each alarm bit holding FF circuit 52A to 52C for 0 to 62ch is generated, and WTIMC8, WCRCC8, WLOM which is an alarm signal after processing of TIM, CRC, LOM.
It is supplied to the FF circuits 52A to 52C which hold the alarm bit of the TU channel which has been subjected to the processing of C8. When the output signal of the alarm bit write address controller 52-4 is 63, the write enable is not generated because it is not the alarm bit write timing.

Further, the alarm bit read address control unit 52-6 performs the processing when the alarm bit read timing (J12TPC7) is "1".
Output the contents of channel (TUADC7), and J12T
When PC7 = "0", the output signal is controlled to 63 ("111111" in binary display), and the read select generation unit 52-7 outputs the output signal of the alarm bit read address control unit 52-6. When it is 0 to 62, a read select signal for reading an alarm bit of 0 to 62 ch is generated, where the output signal of the alarm bit read address control unit 52-6 is 6.
When it is 3, the read select signal is not generated because it is not the read timing of the alarm bit.

Further, the TIM select section 52-8 reads the alarm bit of the TIM of the TU channel to be processed by the read select signal generated by the read select generation section 52-7, and the CRC select section 52-8. Reference numeral 52-9 is a read select signal generated by the read select generation section 52-7, and is for reading the alarm bit of the CRC of the TU channel to be processed. The LOM select section 52-10 is for the read select generation. The read select signal generated by the unit 52-7 is used to read the alarm bit of the LOM of the TU channel to be processed.

The line switching information read select generation unit 52-11 generates a read selection signal for TU channels = 0 to 62 ch. The line switching information select unit 52-12 uses this line switching information read select signal. The read select signal generated by the generation unit 52-11 is for reading the alarm bit of TIM, and the software notification read select generation unit 52-13 is for generating the read selection signal of TU channel = 0 to 62 ch. The software notification select unit 52-14 reads the TIM alarm bit by the read select signal generated by the software notification read select generation unit 52-13 and notifies the software of the TIM alarm.

With the above configuration, the alarm bit holding unit 52 of the present embodiment can hold various alarm information such as TIM, CRC, LOM, etc. in common for each TU channel, and generate a TIM alarm serially. it can. The following is a brief description of the overall operation of the J1 / J2 byte termination processing unit 22 configured as described above.
First, in the phase shift unit 32 ', TU data (here, J1 byte of VC3), TUAD, SPEEN, at the timings shown in FIGS. 78 (a) to 78 (h), for example.
Assuming that J1V5TP, VC3TUG, and VC2VC12 are input, the multi-frame pattern serial detection unit 44 and the LOM holding unit 50 shown in FIG.
However, each unit operates according to the timings shown in FIGS. 79 (a) to 79 (l).

Then, at this time, the multi-frame number serial detection unit 45 and the FRNO holding unit 5 shown in FIG.
1, the LOM serial detector 46 shown in FIG. 66 and FIG.
In the CRC serial detector 47 shown in FIG.
Each section operates according to the timings shown in (a) to (n) of FIG. 80, and the TIM serial detection section 49 shown in FIG.
And the expected reception value holding unit 48 shown in FIG.
81 (a) to 81 (k) are operated according to the timings shown in FIG. 81 to generate the SL expected reception value required for the processing in the C2 / V5 byte termination processing unit 24.

As a result, in the alarm bit holding unit 52 shown in FIG. 82, each unit operates in accordance with the timings shown in, for example, FIGS. 82 (a) to 82 (n), and the TIM alarm bit is set for each TU channel. Will be serially generated. As described above, according to the POH termination processing section 8 of the present embodiment, the J1 byte termination processing and the J2 byte termination processing are serially performed by the J1 / J2 byte termination processing section 22 common to each TU channel. Since the multi-frame pattern detection of the multiplexed signal is performed by one J1 / J2 byte termination processing unit 22, a circuit for terminating the J1 byte and a circuit for terminating the J2 byte are respectively provided for the corresponding TU channels. There is no need to provide it.

Accordingly, the circuit (device) of the present POH termination processing unit 8 is greatly reduced in size and the power consumption is greatly reduced.
At this time, specifically, in the J1 / J2 byte termination processing unit 22, various alarm information such as LOM, CRC, and TIM can be serially obtained in common for each TU channel, so that a circuit for LOM detection is provided. , CRC detection circuit, TIM detection circuit, etc. do not need to be separately prepared, and the device scale can be further reduced and the power consumption can be further reduced.

(C4) B3 / V5 byte end processing unit 23
Description of FIG. 83 is a block diagram showing the configuration of the B3 / V5 byte termination processing unit 23 described above with reference to FIG.
As shown in FIG. 5, the B3 / V5 byte termination processing unit 23 of the present embodiment uses the BIP2 error serial detection unit 53,
2 holding unit 54, BIP8 error serial detection unit 55, B
IPPM count value initialization control unit 56, BIPPM serial processing unit 57, BIPPM holding unit 58, and PMRAM
The address control section 59 is provided.

Here, the BIP2 error serial detection unit (BIP2 serial operation processing unit) 53 is set to the B one cycle before.
The BIP2 error is detected by serially performing the BIP2 operation on VC2 and VC12 in the multiplexed signal based on the IP2 error, and the BIP2 holding unit 54 outputs the BIP2 operation result by the BIP2 error serial detection unit 53 to the TU channel. BIP2 while holding each
The stored information (BIP2 calculation result of one cycle before) is supplied to the error serial detection unit 53.

The BIP8 error serial detector (B
The IP8 serial arithmetic processing unit) 55 serially performs the BIP8 arithmetic operation on the VC3 data to detect a BIP8 error. The BIPPM count value initialization control unit 56 responds to the PM reset signal from the software side with the BIPPM. Control for initializing the count value of BIPPM serial processing unit 57.
Output of error serial detection unit 53 and BIP8 error serial detection unit 55 (BIP2 error, BIP8 error)
To select the BI based on the selected BIP error signal.
The PPM addition operation is performed serially.

In other words, this BIPPM serial processing unit 5
Reference numeral 7 denotes a BIP2 error serial detection unit 53 and a BIP8 error serial detection unit 55 as shown in FIG.
BIP for selecting the BIP error signal output from
The error selecting section 57A and this BIP error selecting section 57A
It has a BIPPM serial adder 57B that serially performs addition operation of BIPPM based on the BIP error signal selected in.

Further, the BIPPM holding unit 58 is
The calculation result (BIPPM) in the PM serial processing unit 57 is stored for each TU channel, and the stored information (BIPPM of one cycle before is stored in the BIPPM serial processing unit 57.
M) is supplied to the PMRAM address control unit 59 in response to the PM reset signal from the software side.
RAM address for the IPPM holding unit 58, G1 described later
/ V5 byte end processing unit 25 FEBEPM holding unit 93
A RAM address for (see FIGS. 110 and 114) is generated.

That is, in the B3 / V5 byte end processing unit 23 described above, the POH end operation processing unit 26 shown in FIG.
The B3 byte and the V5 byte BIP included in the C4 signal are arithmetically processed, and the B3 byte and the V5 byte BIPPM are terminated serially, respectively.
The storage unit 27 shown in FIG. 8 stores the calculation result in the B3, V5 byte serial termination processing unit 26B for each TU channel, and the B3, V5 byte serial termination processing unit 2
6B is configured as a storage unit 27B capable of supplying stored information to 6B.

As a result, the B3 / B5 byte termination processing unit 23 described above can serially detect the BIP error that should normally be detected by the POH termination processing for each TU channel having a different signal size, in common for each channel. . Therefore, specifically, the above-mentioned units are configured as follows. FIG. 85 is a block diagram showing the detailed configurations of the BIP error serial detection unit 53 and the BIP2 holding unit 54.
As shown in FIG. 85, the BIP error serial detection unit 53 includes FF circuits with enable 53-1 and 53-2,
BIP2 operation value reset unit (1 input inversion type AND circuit)
53-3, odd bit BIP2 operation unit (exclusive OR circuit) 53-4, even bit BIP2 operation unit (exclusive OR circuit) 53-5, BIP2 operation comparison unit 53-6 and B
An IP2 error detection unit (AND circuit) 53-7 is provided, and the BIP2 holding unit 54 is a RA for holding BIP2.
It is configured with M54-1.

First, the BIP of the BIP2 holding unit 54
2 holding RAM 54-1 is BIP performed with V5 bytes
The operation result of the two operations is held, the TU address signal (TUADC6) supplied from the phase shift unit 32 '(see FIG. 44) of the timing generation unit 21 is used as the read address, and the TUADC7 is used as the write address. BIP2 holding RAM operation control unit 38 (see FIG.
XBIP2WENC8 supplied from (see 0) is used as a write enable and BIP2CK is used as a RAM clock.

Incidentally, this BIP2 holding RAM 54-1
Here, 2 bits of data are held here, and the BIP2 operation result of the odd number bit is stored in the storage area of the bit number "1", and the BIP2 operation result of the even number bit is stored in the storage area of the bit number "0".
The IP2 calculation processing result is held. On the other hand, in the BIP2 error serial detection unit 53, the FF circuit 53-1
The BIP2 holding RAM 54-1 is a timing signal (SPEENC7) indicating the position of the payload data of the TU.
The FF circuit 53-2 receives the VC4 data (T) with the timing signal (SPEENC7).
The UDTC7) holds the payload data, and this signal is output as SPEDTC8.

Also, the BIP2 calculated value reset unit 53-3
Is a V5 byte timing signal (V5TPC8), which is the start position of the BIP2 calculation range.
The BIP2 operation processing result read from M54-1 is masked to reset the operation value in the previous BIP2 operation range.
-4 is an odd bit BIP2 operation processing result read from the BIP2 holding RAM 54-1 and the FF circuit 53-
The exclusive OR (EXOR) is taken with respect to the 1st, 3rd, 5th and 7th bits of the payload data held in 2, and the result is written in the 1st bit of the BIP2 holding RAM 54-1.

Further, the even bit BIP2 operation unit 53-
5 is an even-bit BIP2 operation processing result read from the BIP2 holding RAM 54-1 and the FF circuit 53-2.
The exclusive OR (EXOR) is taken with the 2nd, 4th, 6th, and 8th bits of the payload data held in step S1, and the result is written in the 0th bit of the BIP2 holding RAM 54-1.

Also, the BIP2 operation comparing section 53-6 is
The BIP2 operation processing result read from the IP2 holding RAM 54-1 is compared with the first and second bits of the payload data held in the FF circuit 53-2, and "1" is output when they do not match. , Here, this figure 85
As shown in, the function is realized by using the exclusive OR circuit 53-6A and the OR gate 53-6B.

Furthermore, the BIP2 error detection unit 53-7
Outputs the output of this BIP2 operation comparison unit 53-6 to BIP2.
Although it is output as an error, since the BIP2 operation comparing section 53-6 always performs 2-bit comparison, the BIP2 operation comparing section 53-6 outputs an invalid comparison result at a timing other than V5 byte. Will be done.
Therefore, the BIP2 error detection unit 53-7 receives the correct BIP with the V5 byte timing signal (V5TPC8).
The two-operation comparison result is extracted and output.

With the above configuration, the BIP2 of this embodiment is
In the error serial detection unit 53, the BIP2 holding RAM
The BIP2 error of the previous frame is sequentially read from 54-1 and B for the current frame is read based on the read information.
By performing the IP2 calculation and updating the BIP2 error information, it is possible to detect the BIP2 error serially for each TU channel.

Next, FIG. 86 is a block diagram showing the detailed structure of the BIP8 error serial detector 55 shown in FIG.
As shown in FIG. 86, the BIP8 error serial detection unit 55 of the present embodiment has BIP8 operation value storage units (FF circuits) 55-1 to 55-3 and BIP8 operation result storage unit (F
F circuit) 55-4 to 55-6, decode circuit (DEC)
55-7 to 55-9, BIP calculation value selection unit (selector)
55-10, BIP8 operation value reset unit (1-input inversion AND circuit) 55-11, BIP operation unit (exclusive OR circuit) 55-12, BIP8 operation value write enable generation unit (AND circuit) 55-13 BIP8 operation result write enable generation unit (AND circuit) 55-14, BIP
8 calculation result selection unit (selector) 55-15, BIP8 calculation comparison unit 55-16 and BIP8 error detection unit (AND
Circuit) 55-17.

Here, the BIP8 calculated value holding unit 55-1
Is B for each payload data of TU channel = 0ch
The IP8 calculation result is held, and the BIP8 calculation value holding unit 55-2 holds the BIP8 calculation result for each payload data of TU channel = 1ch.
The BIP8 calculated value holding unit 55-3 has the TU channel = 2.
It holds the BIP8 operation result for each payload data of ch.

Also, the BIP8 operation result holding unit 55-4
Holds the BIP8 operation result from the J1 byte of TU channel = 0ch to the J1 byte of the next frame. The BIP8 operation result holding unit 55-5 stores the BIP8 operation result holding unit 55-5 from the J1 byte of TU channel = 1ch to the J1 byte of the next frame. BIP8 operation results up to
The P8 calculation result storage unit 55-6 has a TU channel = 2c.
BI from the J1 byte of h to the J1 byte of the next frame
It holds the P8 operation result.

Further, the decoding circuit (“0” detection section) 5
5-7 are TU channels (TUADC) for processing.
8) is for detecting that it is "0", and the decode circuit ("1" detection unit) 55-8 performs TU processing.
It is for detecting that the channel (TUADC8) is "1", and the decoding circuit ("2" detection unit) 55-
Reference numeral 9 detects that the TU channel (TUADC8) for processing is "2".

Also, the BIP calculated value selection unit 55-10 is
BIP8 of each BIP8 calculated value holding unit 55-1 to 55-3
The calculation value is selected according to the detection signals from the above decoding circuits 55-7 to 55-9, and the BIP8 calculation value reset unit 55-11 uses the timing of the J1 byte (the start position of the BIP8 calculation range) ( J1TUPC8),
The BIP8 calculated value read from the BIP8 calculated value holding units 55-1 to 55-3 is masked to reset the calculation result in the previous BIP8 calculated range.

Further, the BIP operation unit 55-12 is an SP which is the BIP8 operation value and payload data after the reset control by the BIP8 operation value reset unit 55-11 described above.
The BIP8 operation is performed by bitwise exclusive OR (EXOR) with EDTC8. The BIP8 operation value write enable generation unit 55-13 calculates the BIP8 operation after the BIP8 operation by the BIP operation unit 55-12. A signal (write enable signal) for writing the value in the BIP8 calculated value holding units 55-1 to 55-3 is generated.

Further, the BIP8 operation result write enable generation unit 55-14 sets the BI at the timing (J1TUPC8) of the J1 byte indicating the start position of the BIP8 operation range.
BI held in the P8 calculated value holding units 55-1 to 55-3
The P8 calculation value is stored in the BIP8 calculation result storage units 55-4 to 55-
6 to generate a signal (write enable signal) to be written into the memory cell 6.

Furthermore, the BIP8 operation result selection unit 55-1
Reference numeral 5 is for selecting the BIP8 operation result in accordance with the detection signals from the decoding circuits 55-7 to 55-9,
The BIP8 operation comparison unit 55-16 detects a mismatch between the BIP8 operation result after selection by the BIP8 operation result selection unit 55-15 and the payload data, and here, the exclusive OR circuit 55-16A and OR. Circuit 55-
The function is realized using 16B.

Also, the BIP8 error detection unit 55-17
Outputs the output of this BIP8 operation comparison unit 55-16 to BIP8.
8 error (BIP8ERRC8) is output, but the BIP8 operation comparison unit 55-16 always outputs 8
Since the bits are compared, the BIP2 operation comparison unit 5
5-16 outputs an invalid comparison result at a timing other than the B3 byte. Therefore, the BIP8 error detection unit 55-17 extracts only the correct BIP8 operation comparison result with the B3 byte timing signal (B3TPC8) and outputs it.

With the above configuration, the BIP8 of this embodiment is
The error serial detection unit 55 always accurately and accurately
Error information can be detected and output. Next, FIG.
7 is a BIPPM serial processing unit 57 and B shown in FIG.
FIG. 87 is a block diagram showing a detailed configuration of the IPPM holding unit 58, and as shown in FIG. 87, the BIPPM serial processing unit 57.
Is an FF circuit with enable 57-1, an error count value initialization control unit (1 input inversion AND circuit) 57-2,
BIP error detector (OR circuit) 57-3 and BIPP
The MIP adder 57-4 is provided, and the BIPPM holding unit 58 is provided with a BIPPM holding RAM 58-1.

First, B of the BIPPM holding unit 58
The IPPM holding RAM 58-1 holds the BIP error count value and the BIPPM count value notified to software, and uses the address signal (RPMADC6) as a read address on the count surface and the address signal (WPMADC).
7) is the write address of the count surface, and the timing signal (XBIPPMWE) supplied from the BIP holding RAM operation control unit 42 (see FIG. 54) of the timing generation unit 21.
NC8) write enable, address signal (BIPP
MRAD) is the read address of the notification side, R for holding BIP
The clock supplied from the AM operation control unit 42 (BIPP
MCK) operates as a RAM clock. Note that each of the above address signals (RPMADC6,
WPMADC7, BIPPMRAD) is P
It is supplied from the MRAM address controller 59.

Thus, the RA for holding the BIPPM described above
In M58-1, for example, as shown in FIG. 89, the PM count value of BIP2 / 8 is read at the detection timing of B3 byte of TU3 and V5 byte of TU2 / TU12, and a read request (μ− COM Rea
In step d), the PM software of BIP2 / 8 is notified to the software, while the B3 byte of TU3 and the V of TU2 / TU12.
The updated value of the PM count value of BIP2 / 8 is written at the detection timing of 5 bytes.

By the way, the BIPPM counts the number of BIP errors generated between the PM reset signals, and notifies the counted value to the next PM reset signal in a soft manner between the PM reset signals. It is necessary to count the error and notify the count value, and to hold the count value of the error and hold the count value to notify.

Therefore, as shown in FIG. 91, the BIPPM holding RAM 58-1 of this embodiment has a lower surface [address 0 (00 _HEX ) to 63 (3F _HEX )] and an upper surface [address 64 (40 _HEX ) -127 (7F _HEX )]
And a counting surface for performing BIP error counting and a notification surface for notifying the count value of BIPPM (PM result holding surface).

The role of each surface is such that the count surface and the notification surface alternate each time the PM reset signal is input. In the present embodiment, for example, FIG.
0, as shown in FIG. 92, such a face exchange is performed by switching the polarity of the MSB bit (PM) of the RAM address. As a result, the BIPPM holding RAM 58-1 holds data of 13 bits, for example, as shown in FIG. 88, and holds the BIP error count value in the bit numbers 12 to 0 on the count side, and on the notification side. Bit number of 12 to 0
The BIPPM count value is held at.

With the above configuration, the BIPP of this embodiment is
In the M serial processing unit 57, the BIPPM holding RAM 5
8-1 sequentially reads the BIPPM of the previous frame, and based on the read information, BIPP for the current frame
By updating M, BIPPM is detected serially in common for each TU channel, and BIPPM holding RAM 5
It can be held in 8-1 and notified to the software side.

Next, FIG. 93 is a block diagram showing a detailed structure of the PMRAM address control unit 59 shown in FIG. 83. As shown in FIG. 93, the PMRAM address control unit 59 of the present embodiment has a count surface holding unit. (FF with enable
Circuit) 59-1, inverting element 59-2 and FF circuit 59-
3 to 59-6. Here, the count surface holding unit 59-1 is the RA for BIPPM holding described above.
A signal (PM count address signal) indicating which of the upper surface and the lower surface of M58-1 is used as the count surface is generated, and the output signal is generated every time the PM reset signal is input. By taking in the signal whose polarity is inverted by the inverting element 59-2, the roles of the lower surface and the upper surface can be switched.

For example, when the output signal of the count surface holding unit 59-1 is "0" and the lower surface is used as the count surface and the upper surface is used as the notification surface, when the PM reset signal is input, the inverting element In "59-2", the polarity of the output signal of the count surface holding unit 59-1 is inverted, and "1" is taken into the count surface holding unit 59-1. As a result, after PM reset, the output signal of the count surface holding unit 59-1 becomes "1", the lower surface is used as the notification surface, and the upper surface is used as the count surface, and the surfaces are exchanged.

Further, the FF circuit 59-3 delays the phase of the PM count address signal generated by the count surface holding unit 59-1 by one master clock, and this output (RPMADC6) is a BIPPM holding R.
AM58-1 and FEBEPM holding RAM 93 described later
It is designed to be used as the read address of the count surface (see FIGS. 110 and 114).

Further, the FF circuit 59-4 is provided with the above FF.
The phase of the PM count address signal from the circuit 59-3 is further delayed by one master clock, and this output (RPMADC7) is the R for BIPPM holding.
It is adapted to be used as a write address for the count surface of the AM 58-1 and the RAM 93 for holding the FEEBEPM.

Further, the FF circuit 59-5 includes an inverting element 59
BIPPM notification address generated through -2 [7 bits including the address signal (MBIPPMRAD: 6 bits) indicating the TU channel for BIPPM reading supplied from the software side and the output signal (1 bit) of the inverting element 59-2] Of the signal] is delayed by one master clock. This output (BIPPM notification address) is used as the read address of the notification surface of the BIPPM holding RAM 58-1.

Further, the FF circuit 59-6 includes the inverting element 5
9-2 FEBEPM notification address generated through [TEE for reading FEBEPM supplied from software side
Address signal indicating the U channel (FEBEPMRA
D: 6 bits) and the output signal (1 bit) of the inverting element 59-2] (7 bit signal) is delayed by one master clock. This output (FEB
EPM notification address) is the FEBEPM holding RAM 93
Is used as the read address of the notification surface of the.

With the above configuration, the PMRA of this embodiment is
The M address control unit 59 uses the BIPPM holding RAM 58.
-1, The count surface and the notification surface of the FEEBEPM holding RAM 93 are switched at an optimum timing to always provide an accurate B
It becomes possible to notify the software side of IPPM and FEEBEPM. Next, FIG. 94 is a block diagram showing the detailed configuration of the BIPPM count value initialization control unit 56 shown in FIG. 83. As shown in FIG. 94, the BIPPM of this embodiment is
The count value initialization control unit 56 uses the FF circuits 56-1 and 5-5.
6-2, 56-8, timing control unit (1 input inversion type O
R circuit) 56-3, read / write signal generation unit [decode circuit (DEC)] 56-4, write enable generation unit (OR circuit) 56-5, BIPPM count value initialization request signal holding unit (FF circuit) 56- 6 and a BIPPM count value initialization request signal selection unit (selector) 56-7.

Here, the FF circuits 56-1 and 56-2 are
The phase of the PM reset signal is delayed by one master clock, respectively.
By delaying the phase of the PM reset signal in 6-1 and 56-2, the above-mentioned PMRAM address control unit 59
Surface switching control by PM reset signal and book B
The timing is adjusted to the BIPPM count value initialization control in the IPPM count value initialization control unit 56.

Also, the timing control unit 56-3 determines that the BI
The timing of the PPM count value initialization request signal is controlled. For example, when the signal (B3V5TPC7) indicating the timing of performing the BIPPM process is "1", the content of the TU channel (TUADC7) to be processed is output, and When the timing signal (B3V5TPC7) is "0", the output signal is 63 (binary display "1111").
11 ").

Further, the read / write signal generator 56-4
Is a read select signal of the BIPPM count value initialization request signal of 0 to 62 ch corresponding to when the output signal of the timing control unit 56-3 is 0 to 62 (supplied to the BIPPM count value initialization request signal selection unit 56-7. Be done)
And a BIPPM count value initialization request signal holding unit 56-
And a write enable signal for 6 are generated.
When the output signal of the timing control unit 56-3 is 63, it is not the timing to perform the BIPPM process, so the read select signal and the write enable signal are not generated.

Also, the write enable generator 56-5
When the PM reset signal is input through the FF circuit 56-2, all of the write enable signals of channels 0 to 62 are set to "1", while when the PM reset signal is not input, the read / write signal generation unit 56-4 The output signal is output as it is, and the BIPPM count value initialization request signal holding unit 56-6 holds the BIPPM count value initialization request signal of TU channel = 0 to 62 ch. FF circuit 56-
The function is realized using 6A.

In the BIPPM count value initialization request signal holding unit 56-6, for example, the FF circuit 56-
The PM reset signal from 2 sets the write enable of all channels to "1", and the FF circuits 56- of all channels.
The data of 6A becomes "1". That is, "1" is written in the FF circuit 56-6A simultaneously for all channels by the PM reset signal.

When the B3 and V5 timing signals (B3V5TPC7) are input after PM reset, the above timing control section 56-3 and read / write signal generation section 56-
4 and the write enable generation unit 56-5 sets the write enable signal of the channel for processing the BIPPM count value to "1". At this time, PM
Since the reset signal is not input, the FF circuit 56-
The input data of 6A becomes "0", "0" is written in the FF circuit 56-6A of the channel for processing, and the first B3V5 timing signal (B3V5T
The PC7) releases the BIPPM count value initialization request signal.

That is, the first B3V5 after PM reset
Only at the timing, the BIP error count value read from the count surface is initialized. Further, the BIPPM count value initialization request signal selection unit 56-7 is configured to read / write signal generation unit 56-4.
The BIPPM count initialization request signal of 0 to 62 channels is selectively read according to the output signal of FF circuit 56-8. The FF circuit 56-8 outputs the phase of the output signal of the BIPPM count value initialization request signal selection unit 56-7. Is delayed by one master clock, and the BIPPM serial processing unit 5
This is to match the phase in which the reset process in 7 is performed.

With the above configuration, the BIPP of this embodiment is
The M count value initialization control unit 56 always resets the BIPPM count value reset signal (BIPPMCTRRSTC) at the optimum timing based on the PM reset signal, the TU address signal, and the B3V5 timing signal.
Since 8) is generated and supplied to the BIPPM serial processing unit 57, the BIPPM serial processing unit 57 can always be operated accurately.

Hereinafter, the book B3 / V constructed as described above
The overall operation of the 5-byte termination processing unit 23 will be briefly described. First, for example, TU data (V5 bytes), TU at the timings shown in FIGS. 95 (a) to 95 (f).
Assuming that AD, SPEEN, and J1V5TP are input, the BIP2 error serial detection unit 53 and the BIP2 holding unit 54 shown in FIG. 85 operate according to the timings shown in FIGS. 96 (a) to 96 (o). To do.

At this time, PMRA shown in FIG.
The M address control unit 59 and the BIPPM count value initialization control unit 56 shown in FIG. 94 are, for example, shown in FIGS.
(Q) [or each part operates according to the timings shown in FIG. 99 (a) to FIG. 99 (o)].
The BIPPM serial processing unit 57 and the BIPPM holding unit 58 shown in FIG. 7 operate in accordance with the timings shown in, for example, FIGS. 97 (a) to 97 (n), and the BIPPM processing of each TU channel is serially performed.

As described above, according to the POH termination processing unit 8 of the present embodiment, the BIP termination (calculation) processing for the B3 byte and the BIP termination processing for the V5 byte are the B3 / V5 byte termination common to each channel. Since serial processing can be performed by the processing unit 23, it is not necessary to provide circuits for BIP termination processing for B3 bytes and V5 bytes respectively for the corresponding number of channels, and further reduction of the device scale and reduction of power consumption are achieved. be able to.

Specifically, in the B3 / V5 byte termination processing section 23, normally, P for each channel having a different signal size is set.
BIP error to be detected by OH termination processing (BIP error
8 error, BIP2 error) are commonly detected in each channel. Therefore, for example, a circuit for BIP8 error detection,
It is not necessary to provide BIP2 error detection circuits for each corresponding number of channels.
Power consumption can be significantly reduced.

The B3 / V5 byte termination processing unit 23 (see FIG. 84) described above, for example, as shown in FIG.
BIP2 serial operation processing units 53A, 53B, BIP8
Serial arithmetic processing unit 55, BIPPM serial addition unit for TU3 (first BIPPM serial addition unit) 57C, TU
BIPPM serial adder for 2 / TU12 (second BIP
PM serial adder) 57D, 57E, BIP for TU3
PM holding unit (first storage unit) 58A, BIPPM holding unit for TU2 / TU12 (second storage unit) 58B, 58C and B
With the IPPM selection unit 57F, the BIP8 serial terminating process and the BIP2 serial terminating process are performed respectively to perform BI.
After obtaining the P error signal (BIPPM) independently, each B
The IPPM may be selectively output.

Thus, B3 / V shown in FIG. 100 is obtained.
In the 5-byte termination processing unit 23, the BIPPM has a simple structure.
Can be obtained serially, and it is very effective when there is no particular need to make the BIPPM holding units 58A to 58C holding BIPPM common to all signal sizes. This will greatly contribute to versatility.

(C5) C2 / V5 byte end processing unit 24
Description of FIG. 101 is a block diagram showing the configuration of the C2 / V5 byte termination processing unit 24 described above with reference to FIG.
As shown in 01, the C2 / V5 byte termination processing unit 24 of the present embodiment includes the UNEQ detection unit 71, the SL holding unit 72,
The SLM detecting unit 73 and the alarm bit holding unit 74 are provided.

Here, the UNEQ detector 71 serially detects that the C2 byte and V5 byte (signal label: SL) contained in the multiplexed signal (VC4 data) are in UNEQ display. SL holder (U
The NEQ data holding unit) 72 is the UNEQ detection unit 71.
Each detection result in is stored for each channel,
The stored information is supplied to the UNEQ detector 71.

Further, the SLM detection section 73 causes a mismatch (S2) between the C2 byte and the V5 byte included in the VC4 data.
LM) is for serially detecting that it is being detected, and an alarm bit holding unit (SLM data holding unit) 74
Stores (holds) each detection result of the SLM detection unit 73 for each channel and supplies the stored information to the SLM detection unit 73.

That is, in the C2 / V5 byte end processing unit 24, the POH end operation processing unit 26 shown in FIG.
UNE of C2 byte and V5 byte included in C4 data
UNEQ serial termination processing unit 26C that performs Q termination processing serially, SLM serial termination processing unit 2 that performs termination processing of the C2 byte and V5 byte SLM described above serially
6D, the storage unit 27 shown in FIG.
A storage unit 27C, SLM capable of storing the calculation result in the EQ serial termination processing unit 26C for each channel and supplying storage information to the UNEQ serial termination processing unit 26C.
The calculation result in the serial termination processing unit 26D is stored for each channel, and the SLM serial termination processing unit 26 is also stored.
It is configured as a storage unit 27D capable of supplying storage information to D.

As a result, in the C2 / V5 byte termination processing unit 24, the UNEQ display and the SLM which should normally be detected by the POH termination processing for each TU channel having a different signal size are serially detected for each channel. You can Therefore, specifically, the UNEQ detecting unit 71 described above, for example, as shown in FIG. 102, C2UNEQ display serial detecting unit 75 that serially detects whether or not the C2 byte is in UNEQ display, and V5 byte is in UNEQ display. V5UNEQ display serial detection section 76 for serially detecting whether or not the UNEQ display selection section 77 selects the UNEQ display detection signal output from each of these detection sections 75, 76.
Based on the UNEQ display detection signal selected by the display selection unit 77, a UNEQ serial detection unit 78 that serially performs UNEQ detection of C2 bytes and V5 bytes is configured.

On the other hand, the SLM detection unit 73 described above is
For example, as shown in FIG. 103, a C2 mismatch serial detection unit 81 that serially detects that the C2 byte has detected a mismatch, a V5 mismatch serial detection unit 82 that serially detects that the V5 byte has detected a mismatch, A mismatch selection section 8 for selecting a mismatch detection signal output from each of these detection sections 81 and 82.
3. Based on the mismatch detection signal selected by the mismatch selection section 83, the SLM serial detection section 84 for serially detecting the C2 byte and V5 byte SLMs is provided.

The details of the above-mentioned UNEQ detector 71, SL holder 72, SLM detector 73, and alarm bit holder 74 will be described below. FIG. 104 is a block diagram showing the detailed configurations of the UNEQ detection unit 71 and the SL holding unit 72. As shown in FIG.
Are FF circuits with enable 71-1 to 71-3, UN
EQ protection stage number addition unit 71-4, decoding circuit (DEC)
71-5 to 71-7, release stage number selection unit (selector) 71
-8, SL range control unit (AND circuit) 71-9, UNE
Q display detection unit (NOR circuit) 71-10, addition condition detection unit (exclusive OR circuit) 71-11, UNEQ detection four-stage detection unit (1 input inverting AND circuit) 71-12, UNE
Q release stage number detection unit (AND circuit) 71-13, state transition occurrence detection unit (OR circuit) 71-14, UNEQ protection stage number information reset unit (1 input inversion AND circuit) 71-15
And a state transition unit (exclusive OR circuit) 71-16, and the SL holding unit 72 includes the SL holding RAM 7
2-1 is provided.

[0370] Here, the SL holding RA of the SL holding unit 72
The M72-1 holds the protection stage number information of UNEQ and SLM, and the phase shift unit 3 of the timing generation unit 21.
The TU address signal (TUADC6) supplied from 2 '(see FIG. 44) is the read address and the TUADC7 is the write address, and the X is supplied from the SL holding RAM operation control unit 39 (see FIG. 51) of the timing generation unit 21.
SLWENC8 is write enable, SLCK is RAM
It works as a clock.

The SL holding RAM 72-1 is
In the present embodiment, 6-bit data is held, and the UNEQ protection stage number information is stored in the storage regions of bit numbers 2 to 0, and the SLM protection stage number information is stored in the storage regions of bit numbers 5 to 3, respectively. . Further, in the UNEQ detection unit 71, the FF circuit 71-1 uses the timing signal (C2V5TPC7) indicating the position of the C2 and V5 bytes to read the 2nd to 0th bits of the read data from the SL holding RAM 72-1 ( The FF circuit 71-2 holds the UNEQ protection stage number information), and the FF circuit 71-2 receives the VC4 data (TUDT) with the timing signal (C2V5TPC7).
C7) to C2 and V5 bytes of data are held, and the FF circuit 71-3 uses the timing signal (C2).
UNEQ which is the processing result of the previous frame in V5TPC7)
It holds the alarm bit.

Also, the UNEQ protection stage number addition unit 71-4
Is the UNEQ read from the SL holding RAM 72-1.
The count value of the protection stage number information is incremented by 1, and the decode circuit (“3” detection unit) 71-5 reads the read U
It detects that the count value of the NEQ protection stage number information is "3", and the decoding circuit ("4" detection unit) 7
1-6 is for detecting that the count value of the read UNEQ protection stage number information is "4", and the decoding circuit ("5" detection unit) 71-7 is for reading the UN
It is detected that the count value of the EQ protection stage number information is "5".

Further, the release stage number selection unit 71-8 is set to UN
The number of EQ cancellation stages is 6 for TU3 and 5 for TU2 / TU12
Since it is different from the stage, the output signal of the decode circuit 71-7 is selected by the C2 byte timing signal for performing UNEQ detection in TU3, and the SL range control unit 71-9 is
In the C2 byte of TU3, all 8 bits are the signal label, whereas in the V5 byte of TU2 / TU12 it is 5
Since the 7th bit is the signal label and the SL range is different, control is not performed when the data held in the FF circuit 71-2 is the C2 byte, and 1-4 when the data is the V5 byte.
The control is performed so that the eighth bit is masked and replaced with "0".

Further, the UNEQ display detector 71-10 is
This is to detect that all 8 bits of the signal after being controlled by the SL range control unit 71-9 are "0", and the addition condition detection unit 71-11 detects that the UNEQ display has not been detected while the UNEQ is being generated. , Or UNEQ while UNEQ is not occurring
UNEQ is used to detect that display has been detected.
The four-stage detection unit 71-12 detects that the decoding circuit 71-5 has detected an addition condition for three consecutive frames while the UNEQ is not detected, and when the addition condition is also detected in the current frame, The UNEQ is detected by recognizing that the addition condition is detected for four consecutive frames.

Further, the UNEQ release stage number detection unit 71-1
3 detects that the addition condition is continuously detected for 4 frames or 5 frames from the output signals of the decoding circuits 71-6 and 71-7 selected by the canceling stage number selection unit 71-8, and further detects the addition to the current frame. When the addition condition is detected, the UNEQ is canceled by recognizing that the addition condition is detected continuously for 5 or 6 frames.

Further, the state transition occurrence detecting section 71-14 is
It is to detect that a condition for detecting or canceling UNEQ has occurred, and the UNEQ protection stage number information reset unit 71-
15 indicates that the count value of the UNEQ protection stage number information is “0” when the addition condition detecting unit 71-11 does not detect the addition condition and when the state transition occurrence detecting unit 71-14 detects the state transition occurrence. The output signal (count value) is written in the SL holding RAM 72-1.

Further, the state transition unit 71-16 inverts the polarity of the UNEQ alarm bit when the state transition occurrence detection unit 71-14 detects the occurrence of the state transition, and
A signal (WUNEQC8) indicating a state transition between EQ being generated and UNEQ not being generated is generated, and this signal is written in the alarm bit holding unit 74.

With the above configuration, the UNEQ of this embodiment is
The detection unit 71 sequentially reads out the UNEQ of the previous frame from the SL holding RAM 72-1 and updates the UNEQ for the current frame based on the read information, thereby serially detecting the UNEQ and UNEQ common to each TU channel. The software side of can be notified. Next, FIG. 105 is a block diagram showing a detailed configuration of the SLM detection unit 73 shown in FIG. 101. As shown in FIG.
The SLM detection unit 73 of the present embodiment is an FF with enable.
Circuits 73-1 to 73-4, SLM protection stage number adding unit 73-
5, decode circuit (DEC) 73-6, 73-7, SL
Range control unit (AND circuit) 73-8, mismatch detection unit 73
-9, addition condition detection unit (exclusive OR circuit) 73-1
0, SLM detection 7-stage detection unit (AND circuit) 73-11
SLM cancellation three-stage detection unit (AND circuit) 73-12, state transition occurrence detection unit (OR circuit) 73-13, SLM protection stage number information reset unit (OR circuit) 73-14 and state transition unit (exclusive OR circuit) ) 73-15.

In this case, the FF circuit 73-1 has C2, V5
Timing signal (C2V5TPC) indicating the position of the byte
In 7), the 5th to 3rd bits of the read data from the SL holding RAM 72-1 (SLM protection stage number information:
The FF circuit 73 holds the RSLDTC 7).
-2 is V in the timing signal (C2V5TPC7)
It holds data of C2 and V5 bytes from C4 data (TUDTC7).

The FF circuit 73-3 holds the reception expectation value (REXPSLC7) of the signal label read from the reception expectation value holding unit 48 (see FIGS. 60 and 70) described above with the timing signal (C2V5TPC7). The FF circuit 73-4 holds the SLM detection processing result data (RSLMC7) of the previous frame with the timing signal (C2V5TPC7).

Further, the SLM protection stage number addition unit 73-5
Is for incrementing the count value of the SLM protection stage number information read from the SL holding RAM 72-1 by 1. The decoding circuit (“6” detection unit) 73-6 is for the read SLM.
The decoding circuit (“2” detection unit) 73-7 detects that the count value of the protection stage number information is “6”.
Detects that the count value of the read SLM protection stage number information is "2".

Also, the SL range control unit 73-8 uses the TU3
In the C2 byte of, all 8 bits are the signal label, whereas in the V5 byte of TU2 / TU12, the 5th to 7th bits are the signal label and the range of SL is different.
When the data held in the F circuit 73-3 is the C2 byte, no control is performed, and when the data is the V5 byte, the 1st to 4th and 8th bits are masked and replaced with "0".

Further, the mismatch detection section 73-9 detects the mismatch between the 8-bit received data after undergoing the mask control in the SL range control section 73-8 and the SL reception expected value, and the addition is performed. The condition detection unit 73-10 determines when the SL reception value and the reception expected value match during SLM occurrence, S
The addition condition is detected when the SL reception value and the reception expected value do not match while the LM is not occurring.

Further, the SLM detection 7th stage detector 73-11
Detects that the decoding circuit 73-6 has continuously detected the addition condition for 6 frames while the SLM is not detected, and when the addition condition is also detected for the current frame, the addition condition is continuously detected for 7 frames. Recognizing that it was detected, S
The LM is detected, and the SLM cancellation three-stage detection unit 73
-12 detects that the decoding circuit 73-7 detects the addition condition for two consecutive frames during the SLM detection, and further detects the addition condition in the current frame,
The SLM is canceled by recognizing that the addition condition is detected for three consecutive frames.

Further, the state transition occurrence detecting section 73-13
Detects that a condition for detecting or canceling the SLM has occurred, and the SLM protection stage number information reset unit 73-
14 indicates that the count value of the SLM protection stage number information is "0" when the addition condition detecting unit 73-10 does not detect the addition condition and when the state transition occurrence detecting unit 73-13 detects the occurrence of the state transition. The state transition unit 73-15 inverts the polarity of the SLM alarm bit when the state transition occurrence detection unit 73-13 detects the occurrence of the state transition, and the SLM occurrence ⇔ SLM. This output signal (WSLMC
8) is written in the alarm bit holding unit 74.

Therefore, the above-mentioned alarm bit holding unit 7
Reference numeral 4 denotes a UNEQ alarm bit holding unit 74-1 and an SLM alarm bit holding unit 7 as shown in FIG.
4-2, alarm bit write address control unit (1 input inversion type OR circuit) 74-3, write enable generation unit [decode circuit (DEC)] 74-4, alarm bit read address control unit (1 input inversion type OR circuit) ) 74
-5, read select generator [decode circuit (DE
C)] 74-6, UNEQ select section (selector) 74
-7, SLM select unit (selector) 74-8, line switching information read select generation unit [decode circuit (DE
C)] 74-9, UNEQ line switching information selection unit (selector) 74-10, SLM line switching information selection unit (selector) 74-11, software notification read select generation unit (selector) 74-12, UNEQ software notification selection Section (selector) 74-13 and SLM software notification selection section (selector) 74-14.

Here, the UNEQ alarm bit holding unit 7
4-1 holds UNEQ alarm bits of TU channels = 0 to 62 ch in 63 FF circuits 74-1A, and the SLM alarm bit holding unit 74-2 is
63 FF circuits 74-2A hold the SLM alarm bits of TU channel = 0 to 62 channels.

The alarm bit write address control section 74-3 outputs the contents of the TU channel (TUADC8) to be processed when the timing signal (C2V5TPC8) indicating the alarm bit write timing is "1". The timing signal (C2V5T
When the PC 8) is "0", the output signal is controlled to 63 ("111111" in binary display).

Further, the write enable generator 74-4
Is the alarm bit write address controller 74 described above.
-3 output signals 0-62, 0-62ch alarm bit holding FF circuits 74-1A, 74-2A write enable signals are generated to generate UNEQ, S
Alarm signals after LM processing (WUNEQC8, WSL
MC8) is written in the FF circuits 74-1A and 74-2A holding the alarm bit of the processed TU channel. When the output signal of the alarm bit write address controller 74-3 is 63, the write enable signal is not generated because it is not the alarm bit write timing.

Further, the alarm bit read address control section 74-5 outputs the contents of the TU channel (TUADC7) to be processed when the timing signal (C2V5TPC7) indicating the read timing of the alarm bit is "1". The timing signal (C2V5T
When the PC 7) is "0", the output signal is controlled to 63 ("111111" in binary display).

Further, the read select generator 74-6
Is the alarm bit read address control unit 74-
When the output signal of 5 is 0 to 62, a read select signal for reading an alarm bit of 0 to 62 ch is generated. When the output signal of the alarm bit read address controller 74-5 is 63, this read select signal is not generated because it is not the alarm bit read timing.

Further, the UNEQ select section 74-7 receives the read select signal generated by the read select generating section 74-6, and the UNEQ of the TU channel to be processed.
Of the read select generating unit 74-6.
The TU that performs processing with the read select signal generated in
The alarm bit of the SLM of the channel is read out.

Further, the line switching information read select generating unit 74-9 generates a read select signal for TU channels = 0 to 62ch, and the UNEQ line switching information selecting unit 74-10 uses this line switching information. The UNEQ alarm is read by the read select signal generated by the read select generation unit 74-9, and the SLM line switching information select unit 74-11 is also generated by the line switching information read select generation unit 74-9. The SLM alarm is read by the read select signal.

Further, the software notification read select generation section 7
Numeral 4-12 is for generating a read select signal for TU channel = 0 to 62ch, and UNEQ software notification select section 74-13 is for the read select signal generated by this software notification read select generation section 74-12. Then, the UNEQ alarm is read out and the UNEQ alarm is notified to the software side. The SLM software notification select section 74-14 uses the read select signal similarly generated by the software notification read select generation section 74-12 to output the SLM alarm. Is read out and the SLM alarm is notified to the software side.

With the configuration described above, the SLM detection unit 73 of this embodiment sequentially reads the SLM alarm bits of the previous frame from the alarm bit holding unit 74, and updates the SLM alarm for the current frame based on the read information. By performing the above, it is possible to serially detect the SLM and notify the SLM on the software side in common for each TU channel.

Hereinafter, the book B3 / V configured as described above
The overall operation of the 5-byte termination processing unit 23 will be briefly described. For example, TU data (C2 bytes) and TUA at the timings shown in FIGS. 107 (a) to 107 (f).
Assuming that D (“0”), SPEEN, and J1V5TP are input, the UNEQ detection unit 71, the SL holding unit 72 shown in FIG. 104, and the SLM detection unit 7 shown in FIG. 105.
The alarm bit holding unit 74 shown in FIG. 3 and FIG. 106 respectively corresponds to FIGS. 107 (g) to 107 (z) and 107 (α).
Each part operates according to the timing as shown in, and each TU
Channel UNEQ termination processing (UNEQ display detection, U
NEQ software notification), SLM termination processing (SLM detection, S
LM software notification) is performed serially.

As described above, according to the POH termination processing unit 8 of this embodiment, the UNEQ termination processing for the C2 byte and the UNEQ termination processing for the V5 byte are performed by the C2 / V5 byte termination processing unit 24 common to each channel. (UNE
It can be serially performed by the Q serial termination processing unit).
It is not necessary to provide the circuits for EQ termination processing respectively for the corresponding number of channels, and in this case as well, it is possible to further reduce the device scale and reduce power consumption.

Specifically, in the C2 / V5 byte termination processing unit 24, the UNEQ display that should normally be performed by the POH termination processing for each channel of different signal size is
Since the NEQ detector 71 performs the same for each channel, it is not necessary to provide the circuits for performing the UNEQ display for the corresponding number of channels, and the scale of the apparatus and the power consumption can be significantly reduced.

Further, according to the POH termination processing unit 8 of the present embodiment, the C2 / V5 byte termination processing unit 24 (SLM serial) common to each channel is also used for the SLM termination processing for C2 bytes and the SLM termination processing for V5 bytes. Because it can be done serially by the termination processing unit),
It is possible to further reduce the device scale and reduce power consumption.

More specifically, in the C2 / V5 byte termination processing section 24, the SLM detection, which should normally be performed by the POH termination processing for each channel having a different signal size, is performed in common for each channel, so a circuit for SLM detection is provided. It is not necessary to provide the corresponding number of channels for each, and the size of the device and the power consumption can be significantly reduced.

The C2 / V5 byte termination processing unit 24 (see FIG. 102) described above may be used as a C2UNEQ display serial detection unit 75A, V5UN as shown in FIG.
EQ display serial detector 76A, 76B, UN for TU3
EQ serial detection unit (first UNEQ serial detection unit) 7
8A, UNE2 / TU12 UNEQ serial detection unit (second UNEQ serial detection unit) 78B, 78C, TU3 UNEQ data holding unit (first storage unit) 72A, TU2 /
UNE12 UNEQ data holding unit (second storage unit) 78
B, 78C and UNEQ data selection section 77A, C2 byte UNEQ display processing, V5 byte UN
The EQ display processing may be performed independently and serially, and then each UNEQ display may be selectively output.

As a result, the C2 / V shown in FIG. 108 is obtained.
In the 5-byte termination processing unit 24, the UNEQ display can be serially performed with a simple configuration, and it is not necessary to commonly use the UNEQ data holding units 72A to 72C for holding the UNEQ display for all signal sizes. It is extremely effective in some cases, and greatly contributes to the flexibility and versatility of equipment construction.

Further, the C2 / V5 byte termination processing unit 24 (see FIG. 103) described above, for example, as shown in FIG. 109, the C2 mismatch serial detection unit 81A, the V5 mismatch serial detection unit 82A, 82B, and the TU3 SLM serial. Detection unit (first SLM serial detection unit) 84A, T
U2 / TU12 SLM serial detection unit (second SLM serial detection unit) 84B, 84C, TU3 SLM data holding unit (first storage unit) 84A, TU2 / TU12 SL
M data holding unit (second storage unit) 74B, 74C and SL
The M data selection unit 83A is provided, and the SLM detection process for the C2 byte and the SLM detection process for the V5 byte are independently performed serially, and then each SL is detected.
You may make it selectively output M data.

As a result, the C2 / V shown in FIG. 109 is obtained.
The 5-byte end processing unit 24 can serially perform SLM detection with a simple configuration, and it is not necessary to commonly use the SLM data holding units 74A to 74C that hold SLM data for all signal sizes. It is extremely effective in some cases, and greatly contributes to the flexibility and versatility of equipment construction.

(C6) G1 / V5 byte end processing unit 25
Description of FIG. 110 is a block diagram showing the configuration of the G1 / V5 byte termination processing unit 25 described above with reference to FIG.
As shown in FIG. 10, the G1 / V5 byte termination processing unit 25 of the present embodiment includes the FEBE detection unit 91, the FEBEPM serial processing unit 92, the FEBEPM holding unit 93, and the FEBEP.
The M count value initialization control unit 94, the FERF serial processing unit 95, the FERF holding unit 96, and the alarm bit holding unit 97 are provided.

Here, the FEBE detection unit 91 serially performs FEBE detection of G1 byte and V5 byte included in the multiplexed signal (VC4 data).
The EPM serial processing unit 92 uses the FEBE detection unit 91.
Based on the FEBE detection signal from, the addition operation with respect to the count value of FEEBEPM is serially performed.

Further, the FEBEPM holding unit 93 is
The addition result (count value) in the EPM serial processing unit 92 is stored for each channel, and the FEBEP
The stored information is supplied to the M serial processing unit 92, and the FEBEPM count value initialization control unit 94 uses the P
FEBEPM serial processing unit 9 in response to the M reset signal
The result of addition in 2 is initialized.

Further, the FERF serial processing section 95 is
FE of G1 byte and V5 byte included in VC4 data
The terminating process of RF is performed serially.
The F holding unit (FERF data holding unit) 96 uses this FER.
The F-serial processing unit 95 stores (holds) each processing result (FERF) for each channel and supplies the stored information to the FERF serial processing unit 95. The alarm bit holding unit (FERF data holding unit) ) 9
Similarly, 7 stores (holds) each processing result (FERF alarm bit) in the FERF serial processing unit 95 for each channel and supplies the stored information to the FERF serial processing unit 95.

That is, in the G1 / V5 byte termination processing unit 25, the POH termination calculation processing unit 26 shown in FIG.
FEB of G1 byte and V5 byte included in C4 data
FEB for serially terminating E and FEEBEPM
E serial termination processing unit 26E, the above G1 byte and V5
FERF that serially terminates the FERF of the bite
38 is configured as the serial termination processing unit 26F, and the storage unit 27 illustrated in FIG. 38 stores the calculation result of the FEBE serial termination processing unit 26E for each channel and
The storage unit 27E capable of supplying storage information to the BE serial termination processing unit 26E and the calculation result in the FERF serial termination processing unit 26F are stored for each channel, and the FER
It is configured as a storage unit 27F capable of supplying storage information to the F serial termination processing unit 26F.

As a result, in the above-mentioned G1 / V5 byte termination processing unit 25, the FEBE, which should normally be detected by the POH termination processing for each TU channel having a different signal size,
FEBEPM and FERF can be serially detected for each channel in common. Therefore, specifically, the FEBE detection unit 91 described above, for example, as shown in FIG. 111, the G1FEBE serial detection unit 98 for serially performing the FEBE detection of the G1 byte and the F5 byte of the F5 byte.
The V5FEBE serial detection unit 99 that performs EBE detection serially and the FEBE selection unit 10 that selects the FEBE detection signal output from each of these detection units 98 and 99.
FEBEPM serial processing unit 9
2 includes a FEBEPM serial addition unit 101 that serially performs addition operation of FEBEPM based on the FEBE detection signal selected by the FEBE selection unit 100.

On the other hand, the FERF serial processing unit 95 described above serially detects that the G1 byte indicates FERF, as shown in FIG. 112, for example.
FERF display serial detection unit 102, V5 byte is FE
V5FE that serially detects that RF is displayed
RF display serial detector 103, each of these detectors 10
FERF display detection / selection unit 104 for selecting the FERF display detection signal output from the FERFs 2 and 103.
Based on the FERF display detection signal selected by the display detection / selection unit 104, the G1 byte and V5 byte FERs described above are selected.
FERF serial detection unit 10 that performs F detection serially
It is configured to have 6.

Hereinafter, the above-mentioned FEBE detection unit 91, FEB
EPM serial processing unit 92, FEBEPM holding unit 93,
Details of the FEBEPM count value initialization control unit 94, the FERF serial processing unit 95, the FERF holding unit 96, and the alarm bit holding unit 97 will be described. 113 is F
FIG. 113 is a block diagram showing a detailed configuration of the EBE detection unit 91, and as shown in FIG. 113, the FEBE detection unit 9 of the present embodiment.
1 is an FF circuit 91-1 with enable, G1 byte F
It is configured to include an EBE detection unit 91-2 and a selector 91-3 as the FEBE selection unit 100 shown in FIG.

In this case, the FF circuit 91-1 has G1, V5
Timing signal (G1V5T
PC7) to G1, V from VC4 data (TUDTC7)
The G1 byte FEBE detection unit 91-2 holds the 5th byte to the 1st to 4th bits of data, and the G1 byte FEBE detection unit 91-2 stores the upper 4 bits of the G1, V5 byte data held by the FF circuit 91-1.
It detects that the content of the bit is 1-8.

The selector 91-3 selects the FEBE in the G1 byte and the FEBE in the V5 byte with the V5 byte timing signal (V5TPC8).
With this output signal (FEBE), the performance monitor (P
M) Processing is performed. In addition, FEB
As for the range of E, in the G1 byte, the contents of the upper 4 bits are FE
It is a BE code (see FIG. 19), and the content of the code is 1 to
When it is 8, FEBE is detected. Also, in the V5 byte, the third bit is the FEBE code (see FIG. 21),
When it is "1", FEBE is detected.

With the above configuration, the FEBE of this embodiment
In the detection unit 91, for example, FIGS.
At the timing as shown in (f), TU data (G1 byte), TUAD (“0”), SPEEN, J1V5TP
Assuming that each is input, FIG. 120 (g)-
Each part operates according to the timing as shown in FIG. 120 (m), and FEBE in G1 byte [see FIG. 120 (j)] and FEBE in V5 byte [see FIG. 120 (k)].
By selectively outputting and, FEBE is serially shared by each channel and the FEBEPM serial processing unit 92
Supply to.

Next, FIG. 114 is a block diagram showing the detailed structure of the above-mentioned FEBEPM serial processing unit 92 and FEBEPM holding unit 93. As shown in FIG. 114, first, the FEBEPM serial processing unit 92 is enabled with F
F circuit 92-1 and FEBE count value initialization control unit (1
Input inversion type AND circuit) 92-2 and FEBEPM adder 92-3.
3 is provided with a FEBEPM holding RAM 93-1.

Here, the FEB of the FEBEPM holding unit 93
The EPM holding RAM 93-1 holds the FEBE error count value and the FEBEPM count value notified to the software, but the FEEBEPM counts the number of FEBEs generated between PM reset signals as in the BIPPM. , In order to notify the count value to the software during the next PM reset signal,
It is necessary to count the error and notify the count value between the reset signals, and to hold the count value of the error and hold the count value to notify.

Therefore, the FEBEPM holding RAM 93-1 of this embodiment also has a lower surface [address 0 (00 _HEX )].
~ 63 (3F _HEX )] and upper side [Address 64 (40
_HEX ) -127 (7F _HEX )], and has two surfaces, FEBE counting, counting surface and FEBE
The role is shared with the notification surface (PM result holding surface) for notifying the PM count value. In this case, too,
By switching the polarity of the MSB bit (PM) of the RAM address, such surface replacement is performed.

Further, this FEBEPM holding RAM 93
-1, RPMADC6 is the read address of the count side, WPMADC7 is the write address of the count side, X
FEBEPMWENC8 (see FIG. 55) is write enable, FEBEPMRAD is the read address of the notification surface,
The FEBEPMCK (see FIG. 55) operates as a RAM clock.

Then, the FEBEPM holding RAM 9
In the present embodiment, 3-1 holds 13-bit data, holds the FEBE count value on the count side,
On the notification side, the FEBEPM count value is held. on the other hand,
In the FEBEPM serial processing unit 92, the FF circuit 9
2-1 is a timing signal (G1V5TPC7) indicating the timing of G1 and V5 bytes, which reads the FEBE count value from the count surface of the FEBEPM holding RAM 93-1 and holds the 12th to 0th bit data. And the FEBE count value initialization control unit 9
2-2 is for resetting the FEBE count value read when the first FEBEPM serial processing after PM reset is performed.

Further, the FEBEPM adder 92-3 is
FE after control of the EBE count value initialization control unit 92-2
+1 when the BE count value is FEBE detected
This output signal is the RAM for holding the FEBEPM.
93-1 is written on the count surface. When FEBE is not detected, the FEBEPM addition unit 92-3 does not perform the addition process, and the FEBE count value after the control of the FEBE count value initialization control unit 92-2 is output as it is.

With the above configuration, the FEBE of this embodiment
In the PM serial processing unit 92, the FEBE detection unit 91
Similarly to, the TU data (G1 byte), TU at the timings shown in FIGS. 120 (a) to 120 (f), for example.
Assuming that AD (“0”), SPEEN, and J1V5TP are input, FIG. 120 (n) to FIG.
Each part operates according to the timing as shown in (x).

That is, the FEBEPM serial processing unit 9
2 sequentially reads the FEBEPM (count value) of the previous frame from the FEBEPPM holding unit 93, and based on the read information, the FEBEPM for the current frame.
The FEBE termination processing and the FEBERPM software side notification are performed serially in common for each TU channel by performing the update processing.

Next, FIG. 115 is a block diagram showing the detailed structure of the FEBE count value initialization control unit 94.
As shown in FIG. 15, the FEBE count value initialization control unit 94 of the present embodiment uses the FF circuits 94-1, 94-2, 94.
-8, Timing control unit (1 input inversion type OR circuit) 94
-3, read / write signal generator [decode circuit (DE
C)] 94-4, Write Enable Generation Unit (OR Circuit)
94-5, FEEBEPM count value initialization request signal holding unit 94-6 and FEEBEPM count value initialization request signal selection unit (selector) 94-7.

The FF circuit 94-1 delays the phase of the PM reset signal (FEBEPM count value initialization request signal) by one master clock, and the FF circuit 94-2 delays the phase of the FF circuit 94-2. The phase of the PM reset signal delayed by -1 is further delayed by one master clock.

Further, the timing control unit 94-3 has the FE
Timing control of the BEPM count value initialization request signal is performed. For example, when the timing signal (G1V5TPC7) indicating the timing of performing the FEBEPM processing is "1", the TU channel (TUAD) that performs the processing is executed.
The contents of C7) are output and the timing signal (G1V5
When the TPC 7) is "0", the output signal is controlled to 63 ("111111" in binary display).

Further, the read / write signal generator 94-4
Indicates that the output signal of the timing control unit 94-3 is 0 to
At the time of 62, the read select signal and the write enable signal for the corresponding FEBEPM count value initialization request signal of 0 to 62 channels are generated. The output signal of the timing control unit 94-3 is 0 to
In the case of 62, since it is not the timing for performing the FEEBEPM processing, the read select signal and the write write enable signal are not generated.

The write enable generator 94-5
When the PM reset signal which is the output signal of the FF circuit 94-2 is input (when the PM reset signal is "1"), the write enable signals of channels 0 to 62 are all set to "1" while the PM reset signal is set to "1". When the reset signal is not input, the output signal of the read / write signal generation unit 94-4 is output as it is.

Further, the FEBEPM count value initialization request signal holding unit 94-6 has 63 FF circuits 94-6A.
TU channel = 0-62ch FEBEPM
The count value initialization request signal is held, and the PM reset signal from the FF circuit 94-2 sets the write enable signals of all channels to "1", and at the same time, the input data to the FF circuits 94-6A of all channels becomes "1". It becomes 1 ", and the FEBEPM count value initialization request signal is set simultaneously for all channels.

If a G1V5 byte timing signal (G1V5TPC7) is input after PM reset,
Timing control unit 94-3, read / write signal generation unit 9
4-4, the write enable signal of the channel that processes the FEBEPM count value becomes "1" by the processing in the write enable generation unit 94-5, but since the PM reset signal is not input at this time, the FF circuit 94 -2, the input data becomes "0", and the FF circuit 9
"0" is written in 4-6A.

In other words, the FEBEPM count value initialization request signal holding unit 94-6 releases the FEBEPM count value initialization request signal at the first timing of G1 and V5 bytes after PM reset.
FEBEPM only at the first G1 and V5 timing
FE read from the count surface of the holding RAM 93-1
The BE count value can be initialized.

Further, the FEBEPM count value initialization request signal selection unit 94-7 is the read / write signal generation unit 94.
-4 output signal 0 to 0 held in the FF circuit 94-6A
The 62ch FEBEPM count value initialization request signal is read out, and the FF circuit 94-8 uses the FEBE
The phase of the output signal of the PM count value initialization request signal selection unit 94-7 is delayed by one master clock,
It matches the phase of the reset process.

The FEBE of this embodiment having the above configuration
The PM count value initialization control unit 94 is shown in FIG.
TU data (G1 byte), TUAD (“0”), SPEEN, J at the timing shown in FIG.
Assuming that each of 1V5TP is input, FIG.
1 (a) to 121 (q), the respective parts operate in accordance with the respective timings, and based on the PM reset signal, the TU address signal, and the G1V5 timing signal, the FEBEPM count value initialization is always performed at the optimum timing. Since the reset signal (FEBEPMCTRSTRC8) is generated and supplied to the FEEBEPM serial processing unit 92, the FEEBEPM serial processing unit 92 can always be operated accurately.

As described above, according to the POH termination processing unit 8 of this embodiment, FEBE and FE for the G1 byte are set.
The BEPM termination processing and the FEBE and FEBEPM termination processing for V5 bytes are common to all channels.
Since the 1 / V5 byte termination processing unit 25 can perform the serial operation, the device scale can be further reduced in this case as well.
Low power consumption can be achieved.

Specifically, in the G1 / V5 byte termination processing section 25, FEBE and FEB which should normally be performed by POH termination processing for each channel having a different signal size.
The terminating process of the EPM is performed by the FEBE detection unit 91, the FEBEP
Since the M serial processing unit 92 is commonly used for each channel, it is not necessary to provide circuits for FEBE and FEBEPM termination processing respectively for the corresponding number of channels, and the size and power consumption of the device are greatly reduced. can do.

Next, FIG. 116 is a block diagram showing the detailed structure of the above-mentioned FERF serial processing unit 95 and FERF holding unit 96. As shown in FIG. 116, the FERF serial processing unit 95 includes the enable FF circuit 95. -1-
95-3, FERF protection stage number addition unit 95-4, decoding circuit (DEC) 95-5, FERF selection unit (selector)
95-6, addition condition detection unit (exclusive OR circuit) 95-
7, FERF detection cancellation 10-stage detection unit (AND circuit) 95
-8, FERF protection stage number information reset unit (1-input inverting AND circuit) 95-9 and state transition unit (exclusive OR circuit) 95-10, and FERF holding unit 9
6 is provided with a FERF holding RAM 96-1.

Here, the FERF holding RAM 96-1 of the FERF holding unit 96 holds the FERF protection stage number information, and the TU address signal (TUADC6) is a read address, the TUADC7 is a write address, and the XFER is XFER.
FWENC8 (generated by the FERF holding RAM operation control unit 40 shown in FIG. 52) is write-enabled, F
The ERFCK (see FIG. 52) operates as a RAM clock. The RA for holding the FERF
In the present embodiment, M96-1 is 4-bit data (F
The ERF protection stage number information) is retained.

On the other hand, in the FERF serial processing unit 95, the FF circuit 95-1 uses the timing signal (G1V5TPC7) indicating the position of the G1 and V5 bytes to read data from the FERF holding RAM 96-1 (FERF protection stage number information). And holds the FF circuit 95-2.
Is the timing signal (G1V5TPC7), and VC
It holds the 5th and 8th bits of G1 and V5 byte data from 4 data (TUDTC7).
The circuit 95-3 uses the timing signal (G1V5TPC).
In 7), the processing result (FERF alarm bit: FERFC7) of the FERF of the previous frame supplied from the alarm bit holding unit 97 is held.

Further, the FERF protection stage number addition unit 95-4
Is the FE read from the RAM 96-1 for holding the FERF.
The count value of the RF protection stage number information is incremented by 1,
The decoding circuit (“9” detection unit) 95-5 detects that the count value of the read FERF protection stage number information is “9”, and the FERF selection unit 95-6 is T
The FERF bit at the time of U3 processing and the FERF bit at the time of TU2 / TU12 processing are selected.

Here, in the G1 byte of TU3, the fifth bit is the FERF bit (see FIG. 19), and in the V5 byte of TU2 / TU12, the least significant bit (8th bit) is the FERF bit. 21 (see FIG. 21), the V5 byte timing signal (V5TPC8) causes 8 when the FERF detection is performed on the V5 byte.
The bit signal is selected as the FERF bit.

Further, the addition condition detection unit 95-7 is FE
When the FERF bit is “0” during RF generation,
It is to detect when the FERF bit is “1” while F is not generated, and the FERF detection canceling stage 10 detection unit 95-8
Detects that the above-mentioned decoding circuit 95-5 has continuously detected the addition condition for 9 frames, and further detects the addition condition for the current frame as well, so that the addition condition has been detected continuously for 10 frames. Recognizing that, FERF
Is detected or canceled.

The FERF protection stage number information reset unit 9
5-9, when the addition condition is not detected by the addition condition detection unit 95-7, and when the FERF detection cancellation 10-stage detection unit 95 is used.
When the condition of detection or cancellation is detected in -8, the count value of the FERF protection stage number information is reset to 0, and the state transition unit 95-10 detects the occurrence of the state transition and the FERF alarm bit of the FERF alarm bit. Reverse the polarity,
The state transition is performed while FERF is being generated and FERF is not being generated.

With the above configuration, the FERF of this embodiment is
In this case as well, the serial processing unit 95, for example, in FIG.
(A) to TU at the timings shown in FIG. 122 (f)
Data (G1 byte), TUAD (“0”), SPEE
Assuming that N and J1V5TP are input respectively,
Each part operates according to the timings shown in FIGS. 122 (g) to 122 (s).

That is, the FERF serial processing unit 95
Is an FERF holding unit 96 (FERF holding RAM 96-
1), sequentially reading the processing result (FERF protection stage number information, FERF alarm bit) of the previous frame from the alarm bit holding unit 97, and performing the FERF update processing (state transition processing) for the current frame based on the read information Thus, the FERF termination process is performed serially for each TU channel.

Next, FIG. 117 is a block diagram showing the detailed structure of the alarm bit holding unit 97 described above.
As shown in, the alarm bit holding unit 97 of the present embodiment.
Is an FERF alarm bit holding unit 97-1, an alarm bit write address control unit (1 input inversion type OR circuit) 97-2, a write enable generation unit [decode circuit (DEC)] 97-3, an alarm bit read address control unit. (1 input inversion type OR circuit) 97-4, read select generation unit [decode circuit (DEC)] 97-5, F
ERF select unit (selector) 97-6, software notification read select generation unit [decode circuit (DEC)] 97-
7 and FERF software notification selection unit (selector) 97
It is configured with -8.

Here, the FERF alarm bit holding unit 9
7-1 holds FERF alarm bits of TU channels = 0 to 62 channels by 63 FF circuits 97-1A, and the alarm bit write address control section 97-2 indicates the alarm bit write timing. When the timing signal (G1V5TPC8) is "1", the content of the TU channel (TUADC8) for processing is output, and the timing signal (G1V5TPC8) is output.
When 8) is "0", the output signal is 63 ("1" in binary display).
11111 ″).

Also, the write enable generator 97-3
This alarm bit write address controller 97-
When the output signal of 2 is 0-62, F for 0-62ch
Generate a write enable signal to the F circuit 97-1A,
The alarm signal (WFERFC8) after the FERF processing is written in the processed TU channel FF circuit 97-1A. When the output signal of the alarm bit write address control unit 97-2 is 63, the write enable signal is not generated because it is not the alarm bit write timing.

Further, the alarm bit read address controller 97-4 outputs the contents of the TU channel (TUADC7) to be processed when the alarm bit read timing signal (G1V5TPC7) is "1",
When the timing signal (G1V5TPC7) is "0", the output signal is controlled to 63 ("111111" in binary display).

Further, the read select generation section 97-5 is
When the output signal of the alarm bit read address controller 97-4 is 0 to 62, a read select signal for reading an alarm bit of 0 to 62 ch is generated. When the output signal of the alarm bit read address controller 97-4 is 63, the read select signal is not generated because it is not the alarm bit read timing.

Further, the FERF select section 97-6 is
With the read select signal generated by this read select generation unit 97-5, the FER of the TU channel to be processed
The alarm notification bit of F is read, and the software notification read select generation unit 97-7 determines that TU channel = 0.
The FERF soft notification select unit 97-8 is a read select signal generated by the soft notification read select generation unit 97-7.
The ERF alarm bit is read and software is notified of the FERF alarm.

With the above configuration, the alarm bit holding unit 97 of this embodiment holds the FERF alarm bit in common for all channels and selectively outputs it.
Soft notification of FERF alarm can be performed serially. As described above, according to the POH termination processing unit 8 of this embodiment, the G1 / V5 byte termination processing unit 25 common to each channel performs the FERF termination processing for the G1 byte and the FERF termination processing for the V5 byte. Since the operations can be performed serially, the device scale can be further reduced and the power consumption can be further reduced.

Specifically, in the G1 / V5 byte termination processing unit 25, the FERF termination processing, which should normally be performed by the POH termination processing for each channel having a different signal size, is common to each channel in the FERF serial processing unit 95. Since it is performed, it is not necessary to provide the circuits for the FERF termination processing for the corresponding number of channels, respectively, and it is possible to significantly reduce the scale of the device and the power consumption.

By the way, the above-mentioned G1 / V5 byte termination processing section 25 (see FIG. 111), as shown in FIG. 118, for example, G1FEBE serial detection section 98A, V5FEB.
E serial detectors 99A, 99B, FEBEP for TU3
M serial adder (first FEBEPM serial adder)
101A, FEBEPM serial addition unit for TU2 / TU12 (second FEBEPM serial addition unit) 93B, 79
3, FEBEPM holding unit for TU3 (first storage unit) 93
A, FE2 / FE12 FEBEPM holding units (second storage units) 93B and 93C, and FEBE selecting unit 77A are provided to independently perform G1 byte FEBE and FEBEPM termination processing, and V5 byte FEBE and FEBEPM termination processing. And then serially, then each FEB
The EPM may be selectively output to the software side.

As a result, G1 / V shown in FIG. 118 is obtained.
The 5-byte end processing unit 25 can perform the end processing of FEBE and FEEBEPM serially with a simple configuration, and the FEEBEPM holding unit 9 that holds the FEEBEPM.
This is very effective when it is not particularly necessary to make 3A to 93C common to all signal sizes, which greatly contributes to flexibility in equipment construction and versatility.

Further, the above-mentioned G1 / V5 byte termination processing unit 25 (see FIG. 112), the G1FERF display serial detection unit 102A, V5F, as shown in FIG. 119, for example.
ERF display serial detector 103A, 103B, TU3
FERF serial detector (first FERF serial detector) 106A, TU2 / TU12 FERF serial detector (second SLM serial detector) 106B, 106
The FERF data data holding unit (first storage unit) 96A for C and TU3, the FERF data data holding unit (second storage unit) 96B and 96C for TU2 / TU12, and the FERF data selection unit 104A are provided for the F for G1 byte.
After performing the ERF termination processing and the FERUF termination processing for V5 bytes independently and serially,
The ERF data may be selectively output to the software side.

As a result, G1 / V shown in FIG. 119 is obtained.
In the 5-byte termination processing unit 25, the FERF termination processing can be serially performed with a simple configuration, and it is particularly necessary to make the FERF data holding units 96A to 96C that hold FERF data common to all signal sizes. It is very effective when it is not available, and contributes greatly to the flexibility and versatility of equipment construction.

As described above, according to the POH termination processing unit 8 of this embodiment, the POH termination processing can be performed as it is without separating the multiplexed signal transmitted by the SDH transmission system for each channel. Therefore, it is not necessary to provide circuits for POH termination processing for the number of channels multiplexed in the multiplexed signal, and the device (circuit) scale and power consumption of this device can be greatly reduced.

(D) Others In the above embodiment, the TU is set in the transmission terminal station device 306.
Although the pointer processing unit 6 and the POH termination processing unit 8 are provided as a pointer / POH termination processing device, the present invention is not limited to this, and only the POH termination processing unit 8 is provided and dedicated to the POH termination processing. It may be configured as a device.

[0459]

As described above in detail, according to the POH termination processing device of the present invention, the multiplexed signal transmitted by the SDH transmission system is not separated for each channel but is serialized PO.
Since the H-terminal arithmetic processing can be performed by the POH-terminal arithmetic processing unit common to each channel, it is not necessary to provide circuits for the POH-termination arithmetic processing for the number of channels multiplexed in the multiplexed signal. Therefore, the device (circuit) scale, power consumption, etc. of the present POH termination processing device can be significantly reduced (claims 1 to 24).

At this time, the storage information corresponding to each channel required for the POH end arithmetic processing and the POH byte data to be processed in the multiplexed signal are PO at a desired timing.
By supplying the HOH terminal processing unit to the POH terminal processing unit, the POH terminal processing unit can be operated only when necessary, so that the power consumption of the POH terminal processing device can be further significantly reduced. 3 ).

By the way, in the above-mentioned POH termination arithmetic processing section, the J1 byte termination processing and the J2 byte termination processing are serially performed by the J1 and J2 byte serial termination processing sections common to each channel, and the multi-signal multiplexing is performed. Since the frame pattern detection is performed by one J1 and J2 byte serial termination processing unit, a circuit for performing the termination processing for the J1 byte and a circuit for performing the termination processing for the J2 byte are respectively provided.
It is not necessary to provide the corresponding number of channels. Therefore, it greatly contributes to a significant reduction in the device scale and power consumption of the POH termination processing device (claim 4 ).

At this time, specifically, if the POH termination arithmetic processing section is configured as a J1 or J2 byte serial termination processing section, various types of LOM, CRC, TIM, etc. can be obtained by the J1 and J2 byte serial termination processing section. Since alarm information is serially obtained for each channel, LO
It is not necessary to separately prepare a circuit for M detection, a circuit for CRC detection, a circuit for TIM detection, etc., and it is possible to further reduce the device scale and reduce power consumption (claim 5 ).

Further, the above POH termination arithmetic processing unit is
If configured as a 3, V5 byte serial termination processing unit,
BIP termination (calculation) processing for B3 bytes and BIP termination processing for V5 bytes are common to each channel.
Since it can be serially performed by the 3, V5 byte serial termination processing unit, B for B3 byte and V5 byte can be performed.
It is not necessary to provide the circuits for IP termination processing respectively for the corresponding number of channels, and it is possible to further reduce the device scale and reduce power consumption (claim 6 ).

Specifically, in this B3, V5 byte serial termination processing section, a BIP error (B
(IP8 error, BIP2 error) is commonly detected for each channel. For example, it is not necessary to provide a circuit for BIP8 error detection and a circuit for BIP2 error detection each corresponding to the number of channels, and further, the device scale ， Power consumption can be significantly reduced (Claims)
7 ).

Note that the B3, V5 byte serial termination processing unit performs a BIP error (BIPPM) by the BIP8 serial termination processing and the BIP2 serial termination processing, respectively.
BIP error can be serially detected with a simple configuration by independently outputting and then outputting each BIPPM. Therefore, it is very effective when there is no particular need to share the storage unit for holding the BIPPM with all signal sizes, which greatly contributes to the flexibility and versatility in constructing the device ( Claim 8 ).

Furthermore, the above POH termination arithmetic processing unit is
If configured as a NEQ serial termination processing unit, this UN
The UNEQ termination processing for C2 bytes and the UNEQ termination processing for V5 bytes can be serially performed in common for each channel by the EQ serial termination processing unit. Therefore, a circuit for UNEQ termination processing for C2 bytes and V5 bytes is provided. It is not necessary to provide the corresponding number of channels, respectively, and in this case as well, further reduction of the device scale and reduction of power consumption can be achieved (claim 9 ).

Specifically, in this UNEQ serial termination processing section, normally, the POH for each channel of a different signal size is used.
Since the UNEQ display that should be performed by termination processing is performed in common for each channel, it is not necessary to provide circuits for performing UNEQ display for each corresponding number of channels, and the size and power consumption of this device are greatly reduced. It is possible (claim 10 ).

Note that this UNEQ serial termination processing unit has a C2 byte UNEQ display processing and a V5 byte UNE display processing.
If the EQ display processing is performed independently and serially, and then each UNEQ display is selectively output, the UNEQ display can be performed serially with a simple configuration. Therefore, it is very effective in the case where it is not particularly necessary to make the storage unit for holding the UNEQ display common to all signal sizes, which greatly contributes to the flexibility and versatility in constructing the device. (claim 1 1).

Also, the above POH termination arithmetic processing unit is SL
If configured as an M serial termination processing unit, this SLM serial termination processing unit enables the SLM for the C2 byte.
Since the termination processing and the SLM termination processing for the V5 byte can be performed serially in common for each channel,
Also in this case, it is possible to further reduce the device scale and reduce the power consumption (claim 12 ).

Specifically, in this SLM serial termination processing unit, SLM detection, which should normally be performed by POH termination processing for channels of different signal sizes, is performed in common for each channel. ,
There is no need to provide a corresponding number of channels, further, the apparatus size, power consumption can be greatly reduced (claim 1 3).

This SLM serial termination processing unit is
C2 byte SLM detection processing and V5 byte SLM detection processing are performed independently and serially.
If the LM is selectively output, the SLM has a simple configuration.
Detection can be done serially. Therefore, the SLM
This is very effective when there is no particular need to make the storage unit for holding the same for all signal sizes, which greatly contributes to the flexibility and versatility in device construction (claim 1). 4 ).

Further, the above POH termination arithmetic processing unit is
If configured as an EBE serial termination processing unit, this FE
Since the BE serial termination processing unit can perform the FEBE and FEEBEPM termination processing for the G1 byte and the FEBE and FEEBEPM termination processing for the V5 byte in common for each channel, the device scale is further increased in this case as well. Can be reduced and power consumption can be reduced (Claim 15 ).

Specifically, in this FEBE serial termination processing unit, normally, the POH for each channel of a different signal size is used.
FEBE and FEBEPM to be performed by termination processing
Since the termination processing of is common to each channel,
Circuits for termination processing of E and FEBEPM,
It is not necessary to provide the corresponding number of channels, and it is possible to significantly reduce the scale of the device and power consumption (claim 16 ).

The FEBE serial termination processing unit detects the FEBE for the G1 byte and performs FEBE.
The PM addition operation, the FEBE detection for V5 bytes, and the FEEBEPM addition operation are independently performed serially, and then each FEBEPM is selectively output, so that FEBE and FEBEPM detection can be performed with a simple configuration. Can be done at. Therefore, FEBE
This is very effective when there is no particular need to make the storage unit for holding the PM common to all signal sizes, which greatly contributes to the flexibility and versatility in constructing the device (Claims). 17 ).

Further, the above POH termination arithmetic processing unit is
If configured as an ERF serial termination processing unit, this FE
Since the RF serial termination processing unit can serially perform the FERF termination processing for the G1 byte and the FERF termination processing for the V5 byte in common for each channel, also in this case, further reduction of the device scale,
Low power consumption can be achieved (claim 18 ).

Specifically, in this FERF serial termination processing section, normally, the POH for each channel having a different signal size is used.
Since the FERF termination processing to be performed by the termination processing is performed in common for each channel, it is not necessary to provide the circuits for the FERF termination processing respectively for the corresponding number of channels, and further, the scale of the device and the power consumption are significantly increased. It can be reduced (Claim 19 ).

The FERF serial termination processing unit detects and displays the FERF for the G1 byte.
If FERF detection / display processing for V5 bytes is independently performed serially and then each FERF is selectively output, FERF display can be performed serially with a simple configuration and the FERF is retained. This is very effective when there is no particular need to use a common storage unit, which greatly contributes to flexibility and versatility in device construction (claim 20 ).

Further, according to the POH termination processing device of the present invention, by providing the POH timing signal serial generation section, the POH timing signal necessary for the POH termination calculation processing section is serially generated in common for each channel. Therefore, it is not necessary to provide circuits for generating POH timing signals for the corresponding number of channels, respectively, and it is possible to significantly reduce the device scale and power consumption (claim 1 ).

Specifically, in this POH timing signal serial generator, the start position of the SPE (J1
Byte, V5 byte) information is sequentially initialized, added, and updated while holding the information for each channel in the storage unit, so that various types of data necessary for the processing in the POH termination arithmetic processing unit can be obtained. Since the POH timing signal is serially generated for each channel, the above processing can be realized with an extremely simple configuration (claim 21).

Further, according to the POH termination processing apparatus of the present invention, by providing the address creating unit for creating the address information for identifying each channel of the multiplex signal, the address for the above storage unit is provided. Since the information can be generated by the address generation unit common to each channel, it is not necessary to provide circuits for generating the address information for the corresponding number of channels, respectively.
There is no need to perform special processing for identifying each channel in the POH termination calculation processing section. Therefore, the scale of the device and the power consumption can be reduced significantly (claim 2 ).

Further, according to the POH termination processing device of the present invention, the termination processing for the J1 and J2 bytes for detecting the multi-frame pattern of the multiplexed signal, the B3 and V5 bytes for obtaining the BIP (BIPPM) from the multiplexed signal. C to get termination, UNEQ, SLM for
2, V5 byte termination processing, FEBE (FEBE
The termination processing for the G1 and V5 bytes for obtaining PM) and the termination processing for the G1 and V5 bytes for obtaining the FERF can be performed serially in common for each channel. circuit, corresponding there is no need to provide a few minutes channel, it is possible to reduce apparatus size of the apparatus, the power consumption greatly in (claim 2 2).

Further, according to the pointer / POH termination processing device of the present invention, both the pointer processing and the POH termination processing for the multiplexed signal transmitted by the SDH transmission system are performed.
Since the multiplexed signals can be serially performed without being separated for each channel, the device can be realized with a minimum scale and a minimum power consumption (claim 2).
5 , 26 ).

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram for explaining a hierarchy structure in the SDH transmission system.

FIG. 3 is a diagram showing an STM-1 frame format in the SDH transmission system.

FIG. 4 is a diagram for explaining an accommodation position of a VC 4 accommodated in an STM-1 frame.

FIG. 5 is a diagram showing a frame format of TU3 in the SDH transmission system.

FIG. 6 is a diagram for explaining an accommodation position of a VC3 accommodated in a TU3 frame.

FIG. 7 is a diagram showing a frame format of TU2 in the SDH transmission system.

FIG. 8 is a diagram for explaining an accommodation position of a VC 3 accommodated in a TU2 frame.

FIG. 9: Frame of TU12 in SDH transmission system
It is a figure which shows a format.

FIG. 10 is a diagram for explaining a housing position of a VC 3 housed in a TU12 frame.

FIG. 11 is a diagram for explaining a mismatch alarm detection method in the SDH transmission method.

FIG. 12 is a diagram showing a format of J1 and J2 bytes (path trace signal) in the SDH transmission system.

FIG. 13 is a diagram for explaining CRC calculation processing in the SDH transmission method.

FIG. 14 is a diagram showing a format of a B3 byte in the SDH transmission system.

15A and 15B are diagrams for explaining BIP8 arithmetic processing in the SDH transmission method.

FIG. 16 is a diagram for explaining BIP8 arithmetic processing in the SDH transmission system.

FIG. 17 is a diagram showing a C2 byte format in the SDH transmission system.

FIG. 18 is a diagram for explaining a value (mapping code) set in the C2 byte in the SDH transmission method.

FIG. 19 is a diagram showing a G1 byte format in the SDH transmission system.

FIG. 20 is a diagram for explaining a value (FEBE code) set in the G1 byte in the SDH transmission method.

FIG. 21 is a diagram showing a V5 byte format in the SDH transmission system.

22A and 22B are diagrams for explaining BIP2 arithmetic processing in the SDH transmission method.

FIG. 23 is a diagram for explaining BIP2 arithmetic processing in the SDH transmission system.

FIG. 24 is a diagram for explaining a value (FEBE code) set in the V5 byte in the SDH transmission method.

FIG. 25 is a diagram for explaining a value (mapping code) set in the V5 byte in the SDH transmission method.

26A to 26F are time charts for explaining the performance monitor (BIPPM) processing in the SDH transmission method.

27A to 27G are time charts for explaining a performance monitor (FEBEPM) process in the SDH transmission system.

FIG. 28 is a block diagram showing an example of an SDH transmission network.

FIG. 29 is a block diagram showing a configuration of a main part of a transmission terminal station device to which a POH termination processing device as one embodiment of the present invention is applied.

FIG. 30 is a diagram showing a TU pointer processing unit and P in the present embodiment.
It is a block diagram which shows the structure of the transmission terminal station apparatus which paid its attention to the OH termination processing part.

FIG. 31 is a block diagram showing configurations of a TU pointer serial processing unit and a TU pointer timing generation unit according to the present embodiment.

FIG. 32 is a block diagram showing a detailed configuration of an address generation unit according to the present embodiment.

FIG. 33 is a diagram showing an example of an address conversion table for explaining the operation of the address generation unit of the present embodiment.

FIG. 34 is a diagram for explaining the operation of the address conversion unit of this embodiment.

FIG. 35 is a top byte (J1 / V5) of the SPE of the present embodiment.
FIG. 3 is a block diagram showing a configuration of a pointer processing unit focusing on a (byte) recognition function portion.

FIG. 36 is a block diagram showing a configuration of a TU pointer processing unit focusing on a signal size recognition function portion of the present embodiment.

FIG. 37 is a block diagram showing a configuration of a POH termination processing unit of this embodiment.

FIG. 38 is a block diagram showing the basic configuration of each termination processing unit of the present embodiment.

FIG. 39 is a block diagram showing the basic configuration of each termination processing unit of the present embodiment.

40 (a) to (t) are time charts for explaining the basic operation of each termination processing unit of the present embodiment.

FIG. 41 is a block diagram showing a configuration of a timing generation section according to the present embodiment.

42A to 42Q are time charts for explaining the operation of the timing generation section of the present embodiment.

FIG. 43 is a block diagram showing a detailed configuration of a timing generation section of the present embodiment.

FIG. 44 is a block diagram showing a detailed configuration of a phase shift unit of the present embodiment.

FIG. 45 is a block diagram showing a detailed configuration of an overhead counter RAM holding unit and an overhead counter serial processing unit of the present embodiment.

FIG. 46 is a block diagram showing a detailed configuration of a POH timing signal generator of the present embodiment.

FIG. 47 is a block diagram showing a detailed configuration of a POH timing signal shift unit according to the present embodiment.

FIG. 48 is a block diagram showing a detailed configuration of a LOM holding RAM operation control unit of the present embodiment.

FIG. 49 is a block diagram showing a detailed configuration of a FRNO holding RAM operation control unit of the present embodiment.

FIG. 50 is a block diagram showing a detailed configuration of a BIP2 holding RAM operation control unit of the present embodiment.

FIG. 51 is a block diagram showing a detailed configuration of a SL holding RAM operation control unit of the present embodiment.

FIG. 52 is a block diagram showing a detailed configuration of a FERF holding RAM operation control unit of the present embodiment.

FIG. 53 is a block diagram showing a detailed configuration of a reception expected value holding RAM operation control unit of the present embodiment.

FIG. 54 is a block diagram showing a detailed configuration of a BIPPM holding RAM operation control unit of the present embodiment.

FIG. 55 is a block diagram showing a detailed configuration of a FEBEPM holding RAM operation control unit of the present embodiment.

56A to 56H are time charts for explaining the operation of the timing generation unit of the present embodiment.

57A to 57P are time charts for explaining the operation of the timing generation section of the present embodiment.

58 (a) to (t) are time charts for explaining the operation of the timing generation unit of the present embodiment.

59A to 59F are time charts for explaining the operation of the timing generation section of the present embodiment.

FIG. 60 is a block diagram showing the configuration of a J1 / J2 byte termination processing unit according to the present embodiment.

FIG. 61 is a block diagram showing a detailed configuration of a multi-frame pattern serial detection unit and an LOM holding unit of this embodiment.

FIG. 62 is a block diagram showing a detailed configuration of a multi-frame number serial control unit and a FRNO holding unit of this embodiment.

FIG. 63 is a diagram showing a format example of a FRNO holding RAM of the present embodiment.

FIG. 64 is a diagram for explaining the operation timing of the FRNO holding RAM of the present embodiment.

FIG. 65 is a diagram showing an example of the relationship between the information in the FRNO holding RAM of the present embodiment and the frame number.

FIG. 66 is a block diagram showing a detailed configuration of a LOM serial detection unit of the present embodiment.

FIG. 67 is a block diagram showing a detailed configuration of a CRC serial detection unit of the present embodiment.

FIG. 68 is a block diagram showing another detailed configuration of the CRC serial detection unit of the present embodiment.

FIG. 69 is a block diagram showing another detailed configuration of the TIM serial detection unit of the present embodiment.

FIG. 70 is a block diagram showing a detailed configuration of a reception expected value holding unit of this embodiment.

FIG. 71 is a diagram showing an example of a data format of the EXP1 holding RAM of the present embodiment.

FIG. 72 is a diagram showing an example of a data format of the EXP2 holding RAM of the present embodiment.

FIG. 73 is a diagram for explaining the operation timing of the expected reception value holding unit of the present embodiment.

FIG. 74 is a RA for holding EXP1 and EXP2 of the present embodiment
It is a figure which shows the address content example of M.

[FIG. 75] RA for holding EXP1 and EXP2 of the present embodiment
It is a figure which shows an example of the relationship of the address of M, a frame number, and a TU channel.

FIG. 76 is a RA for holding EXP1 and EXP2 of the present embodiment
It is a figure for demonstrating switching control of M.

77 is a block diagram showing a detailed configuration of an alarm bit holding unit of the present embodiment. FIG.

78A to 78H are J1 of the present embodiment, respectively.
9 is a time chart for explaining the operation of the / J2 byte termination processing unit.

79 (a) to (l) are J1 of the present embodiment, respectively.
9 is a time chart for explaining the operation of the / J2 byte termination processing unit.

80 (a) to (n) are J1 of the present embodiment, respectively.
9 is a time chart for explaining the operation of the / J2 byte termination processing unit.

81 (a) to (k) are J1 of the present embodiment, respectively.
9 is a time chart for explaining the operation of the / J2 byte termination processing unit.

82 (a) to (n) are J1 of the present embodiment, respectively.
9 is a time chart for explaining the operation of the / J2 byte termination processing unit.

FIG. 83 is a block diagram showing a configuration of a B3 / V5 byte termination processing unit according to the present embodiment.

FIG. 84 is a block diagram showing a configuration of a B3 / V5 byte termination processing unit according to the present embodiment.

FIG. 85 is a block diagram showing detailed configurations of a BIP error serial detection unit and a BIP2 holding unit according to the present embodiment.

[Fig. 86] Fig. 86 is a block diagram illustrating a detailed configuration of a BIP8 error serial detection unit according to the present embodiment.

FIG. 87 is a block diagram showing a detailed configuration of a BIPPM serial processing unit and a BIPPM holding unit of this embodiment.

88 is a diagram showing an example of a data format of the BIPPM holding RAM of this embodiment. FIG.

FIG. 89 is a diagram for explaining the operation timing of the BIPPM holding RAM of the present embodiment.

FIG. 90 is a diagram showing an example of address contents of the BIPPM holding RAM of the present embodiment.

FIG. 91 is a RA for holding EXP1 and EXP2 of the present embodiment.
It is a figure for demonstrating switching control of M.

FIG. 92 is a RA for holding EXP1 and EXP2 of the present embodiment
It is a figure for demonstrating switching control of M.

FIG. 93 is a block diagram showing a detailed configuration of a PMRAM address control unit of this embodiment.

FIG. 94 is a block diagram showing a detailed configuration of a BIPPM count value initialization control unit according to the present embodiment.

95A to 95F are B3 of the present embodiment, respectively.
7 is a time chart for explaining the operation of the / V5 byte termination processing unit.

96 (a) to (o) are B3 of the present embodiment, respectively.
7 is a time chart for explaining the operation of the / V5 byte termination processing unit.

97 (a) to (n) are B3 of the present embodiment, respectively.
7 is a time chart for explaining the operation of the / V5 byte termination processing unit.

98 (a) to (q) are B3 of the present embodiment, respectively.
7 is a time chart for explaining the operation of the / V5 byte termination processing unit.

99 (a) to (o) are B3 of the present embodiment, respectively.
7 is a time chart for explaining the operation of the / V5 byte termination processing unit.

100 is a block diagram showing another configuration of the B3 / V5 byte termination processing unit of the present embodiment. FIG.

101 is a block diagram showing a configuration of a C2 / V5 byte termination processing unit of the present embodiment. FIG.

102 is a block diagram showing a configuration of a C2 / V5 byte termination processing unit of the present embodiment. FIG.

103 is a block diagram showing a configuration of a C2 / V5 byte termination processing unit of the present embodiment. FIG.

FIG. 104 is a block diagram showing a detailed configuration of a UNEQ serial detection unit of the present embodiment.

FIG. 105 is a block diagram showing a detailed configuration of an SLM serial detection unit of the present embodiment.

FIG. 106 is a block diagram showing a detailed configuration of an alarm bit holding unit according to the present embodiment.

107 (a) to (z) and (α) are time charts for explaining the operation of the C2 / V5 byte termination processing unit of the present embodiment.

FIG. 108 is a block diagram showing another configuration of the C2 / V5 byte termination processing unit of the present embodiment.

FIG. 109 is a block diagram showing another configuration of the C2 / V5 byte termination processing unit of the present embodiment.

110 is a block diagram showing a configuration of a G1 / V5 byte termination processing unit according to the present embodiment. FIG.

FIG. 111 is a block diagram showing a configuration of a G1 / V5 byte termination processing unit according to the present embodiment.

FIG. 112 is a block diagram showing a configuration of a G1 / V5 byte termination processing unit according to the present embodiment.

FIG. 113 is a block diagram showing a detailed configuration of an FEBE detection unit of this embodiment.

FIG. 114 is a block diagram showing a detailed configuration of a FEBEPM serial processing unit and a FEBEPM holding unit according to the present embodiment.

FIG. 115 is a block diagram showing a detailed configuration of a FEBEPM count value initialization control unit according to the present embodiment.

FIG. 116 is a block diagram showing a detailed configuration of a FERF serial processing unit and a FERF holding unit according to the present embodiment.

FIG. 117 is a block diagram showing a detailed configuration of a FERF alarm bit holding unit according to the present embodiment.

FIG. 118 is a block diagram showing another configuration of a G1 / V5 byte termination processing unit of the present embodiment.

FIG. 119 is a block diagram showing another configuration of the G1 / V5 byte termination processing unit of the present embodiment.

120 (a) to (x) are G of the present embodiment, respectively.
7 is a time chart for explaining the operation of the 1 / V5 byte termination processing unit.

121A to 121Q are G of the present embodiment.
7 is a time chart for explaining the operation of the 1 / V5 byte termination processing unit.

122 (a) to (s) are G of the present embodiment, respectively.
7 is a time chart for explaining the operation of the 1 / V5 byte termination processing unit.

[Explanation of symbols]

1, 26 POH termination processing unit 2, 27, 27A to 27F Storage unit 3A Working system 3B Standby system 4 SOH termination processing unit 5 AU pointer processing unit 6 TU pointer processing unit 7 ES unit 8 POH termination processing unit (POH termination processing Device) 9 Path switch alarm insertion unit 10 Microcomputer (μ-COM) 11 Cross-connect device (XC) 15 TUG3 address counter 16 TUG2 address counter 17 TU12 address counter 18, 19, 99 ', 128, 129 AND circuit (AND circuit) 20 Address conversion unit 21 Timing generation unit 22 J1 / J2 byte termination processing unit 23 B3 / V5 byte termination processing unit 24 C2 / V5 byte termination processing unit (UNEQ / SLM)
Serial termination processing unit) 25 G1 / V5 byte termination processing unit (FEBE / FER)
F serial termination processing unit) 26A J1, J2 bytes serial termination processing unit 26B B3, V5 bytes serial termination processing unit 26C UNEQ serial termination processing unit 26D SLM serial termination processing unit 26E FEBE serial termination processing unit 26F FERF serial termination processing unit 26- 1 serial processing units 26-2, 32, 33-1, 35-1 to 35-8, 36
-2 to 40-2, 41-8, 41-9, 42-2, 43
-2, 44-1 to 44-3, 45-1 to 45-3, 46
-1,46-2,46-4,46-5,47-1 to 47
-3,48-9,48-10,49-1 to 49-4,5
2A to 52C, 53-1, 53-2, 56-1, 56-
2, 56-6A, 56-8, 57-1, 59-3 to 59
-6, 71-1 to 71-3, 73-1 to 73-4, 91
-1,92-1, 94-1, 94-2, 94-8, 95
-1 to 95-3 FF (flip-flop) circuit 27-1 RAM data holding unit 27-2 FF data holding unit 28 SPE count holding unit 28 'Overhead counter (OHCTR) RAM holding unit 28'-1 Overhead counter RAM 28' -2, 36-4 to 40-4, 42-4, 43-
4, 59-2 Inversion element 29 SPE count value initialization unit 30 SPE count value addition control unit 31 Timing signal generation processing unit 32 'Phase shift unit 33 Overhead counter serial processing unit 33-20 Byte control unit (1 input inversion type) AND circuit) 33-3 TU3 detection unit (1-input inversion AND circuit) 33-4 TU2 detection unit (1-input inversion AND circuit) 33-5 TU12 detection unit (all-input inversion AND circuit) 33-6 Maximum value Setting units 33-7, 48-6A to 48-6C, 48-14A to 4
8-14C AND circuit (logical product circuit) 33-8, 33-11, 48-8D, 48-14D, 5
3-6B, 55-16B, 91-2A OR circuit (OR circuit) 33-9 Maximum value detection unit 33-10, 53-6A, 55-16A, 91-2B
Exclusive OR circuit 33-12 Count value addition unit 33-13 Count value initialization control unit (1 input inversion type A
ND circuit) 34 POH timing signal generators 34-1 to 34-6, 44-6 to 44-8, 45-5
45-6, 47-15, 49-10, 49-11, 55
-7 to 55-9, 71-5 to 71-7, 73-6, 73
-7,95-5 Decoding circuit (DEC) 34-7 TU3 detecting section (1 input inverting AND circuit) 34-8 TU2 detecting section (1 input inverting AND circuit) 34-9 TU12 detecting section (all input inverting type) AND circuit) 34-10 J1 condition detection unit (AND circuit) 34-11 B3 condition detection unit (AND circuit) 34-12 C2 condition detection unit (AND circuit) 34-13 G1 condition detection unit (AND circuit) 34-14 V5 condition detection unit (1 input inversion type AND circuit) 34-15 TU2J2 condition detection unit (AND circuit) 34-16 TU12J2 condition detection unit (AND circuit) 34-17 J2 condition detection unit (OR circuit) 34-18 J1 timing Signal generation unit (AND circuit) 34-19 B3 timing signal generation unit (AND circuit) 34-20 C2 timing signal generation unit (AND circuit) 34-21 G1 timing signal generator (AND circuit) 34-22 V5 timing signal generator (AND circuit) 34-23 J2 timing signal generator (AND circuit) 34-24 J1J2 timing signal generator (OR circuit) 34- 25 B3V5 Timing Signal Generation Unit (OR Circuit) 34-26 C2V5 Timing Signal Generation Unit (OR Circuit) 34-27 G1V5 Timing Signal Generation Unit (OR Circuit) 35 POH Timing Signal Shift Unit 36 LOM Holding RAM Operation Control Unit 36- 1-40-1, 42-1 and 43-1 Operation clock mask generation part (OR circuit) 36-3 to 40-3, 42-3, 43-3 Clock mask part (1 input inverting OR circuit) 37 FRNO Holding RAM operation control unit 38 BIP2 holding RAM operation control unit 39 SL holding RAM operation Work control unit 40 FERF holding RAM operation control unit 41 Reception expected value holding RAM operation control unit 41-1 Reception expected value read request detection unit (OR circuit) 41-2 EXP1 Expected value reading operation clock mask generation unit (1 input Inverted AND circuit) 41-3 EXP2 expected value read operation clock mask generation unit (AND circuit) 41-4 EXP1 expected value setting access Operation clock mask generation unit (1-input inverted AND circuit) 41-5 EXP2 expected value setting access Operation clock mask generation unit (AND circuit) 41-6 EXP1 clock mask generation unit (OR circuit) 41-7 EXP2 clock mask generation unit (OR circuit) 41-10 EXP1 clock mask unit (1-input inversion OR circuit) 41- 11 EXP2 Clock Mask Unit (1 Input Inverting OR Circuit) 41-12 XP1 write enable generation unit (1 input inverting type NAND circuit) 41-13 EXP2 write enable generator (NAN
D circuit) 42 BIPPM holding RAM operation control section 43 FEBEPM holding RAM operation control section 44 Multi-frame pattern serial detection section 44-4 Zero continuous count addition section 44-5 Zero continuous count reset section (1 input inversion type AND circuit) 44-9 Multi-frame head bit detection information reset unit (1 input inversion AND circuit) 44-10 Multi-frame head bit detection information set unit (OR circuit) 44-11 Frame number correction detection unit (AND circuit) 44-12 Multi Frame pattern detection unit (AND circuit) 45 Multi-frame number (FRNO) serial control unit 45-4 Frame number control unit 46 LOM serial detection unit 46-3 LOM protection stage number addition unit 46-6 Addition condition detection unit (exclusive negation logic Sum circuit) 46-7 LOM detection 7 Stage detection unit (AND circuit) 46-8 LOM release three-stage detection unit (AND circuit) 46-9, 47-11 State transition occurrence detection unit (OR circuit) 46-10 LOM protection stage number information reset unit (1 input inversion type) AND circuit) 46-11, 47-12, 49-16 State transition section (exclusive OR circuit) 46-12, 47-13, 49-17 Bypass control section (selector) 47 CRC serial detection section 47-3 CRC Operation result reset unit (AND circuit) 47-5 CRC data insertion unit (80hex insertion unit) 47-6 CRC calculation unit 47-7, 49-5 Mismatch detection unit 47-8 Protection stage control unit 47-9 CRC error detection 3 Stage detection unit (1-input inversion AND circuit) 47-10 CRC error cancellation 3-stage detection unit (1-input inversion NOR circuit) 47-14 CRC protection stage number addition unit 47-16 49-8 adder condition detection section (exclusive OR circuit) 47-17 detect and release the three-stage detector (AND circuit) 47-18 protection stage reset unit (1 input inversion type AND
Circuit) 48 reception expected value holding unit 48-1 first reception expected value (EXP1) holding RAM 48-2 second reception expected value (EXP2) holding RAM 48-3 to 48-5 signal label (SL) reception expectation Value MSB bit holding unit (FF circuit) 48-6 MSB bit software notification selection unit 48-7 reception expected value software notification selection unit (selector) 48-8 SL reception expected value read address control unit (1
Input inversion type AND circuit) 48-8, FF circuits 48-9, 48-10, decoding circuits 48-11 to 48-13, MSB bit selection unit 48-
14 and reception expected value selection unit (selector) 48-15 49 TIM serial detection unit 49-6 mismatch detection display unit (OR circuit) 49-7 mismatch detection display reset unit (1 input inversion type A
ND circuit) 49-9 TIM protection stage number addition unit 49-12 IM detection 7 stage detection unit (AND circuit) 49-13 TIM release 3 stage detection unit (AND circuit) 49-14 State transition occurrence detection unit (OR circuit) 49 -15 TIM protection stage number information reset unit (1 input inverting AND circuit) 50 LOM holding unit 50-1 LOM holding RAM 51 FRNO holding unit 51-1 FRNO holding RAM 52 alarm bit holding unit 52-1 TIM alarm bit holding Unit 52-2 CRC alarm bit holding unit 52-3 LOM alarm bit holding unit 52-4 alarm bit write address control unit (1
Input inversion type OR circuit) 52-5 Write enable generation unit [decode circuit (D
EC)] 52-6 Alarm bit read address control unit (1
Input inversion type OR circuit) 52-7 Read select generation unit (DEC) 52-8 TIM select unit (selector) 52-9 CRC select unit (selector) 52-10 LOM select unit (selector) 52-11 Line switching information read Select generator (D
EC) 52-12 Line switching information selector (selector) 52-13 Software notification read select generator (DE)
C) 52-14 Software notification selection unit (selector) 53 BIP2 error serial detection unit (BIP2 serial operation processing unit) 53A, 53B BIP2 serial operation processing unit 53-3 BIP2 operation value reset unit (1 input inversion type A)
ND circuit) 53-4 Odd bit BIP2 operation unit (exclusive OR circuit) 53-5 Even bit BIP2 operation unit (exclusive OR circuit) 53-6 BIP2 operation comparison unit 53-7 BIP2 error detection unit (AND circuit) ) 54 BIP2 holding unit 54-1 BIP2 holding RAM 55 BIP8 error serial detection unit (BIP8 serial operation processing unit) 55-1 to 55-3 BIP8 operation value holding unit (FF circuit) 55-4 to 55-6 BIP8 operation Result holding unit (FF circuit) 55-10 BIP operation value selection unit (selector) 55-11 BIP8 operation value reset unit (1-input inversion AND circuit) 55-12 BIP operation unit (exclusive OR circuit) 55-13 BIP8 operation value write enable generation unit (AND circuit) 55-14 BIP8 operation result write enable generation unit (AN 55-15 BIP8 operation result selection unit (selector) 55-16 BIP8 operation comparison unit 55-17 BIP8 error detection unit (AND circuit) 56 BIPPM count value initialization control unit 56-3 Timing control unit (1 input inversion type) OR circuit) 56-4 Read / write signal generator [decode circuit (D
EC)] 56-5 Write enable generation unit (OR circuit) 56-6 BIPPM count value initialization request signal holding unit (FF circuit) 56-7 BIPPM count value initialization request signal selection unit (selector) 57 BIPPM serial processing unit 57A BIP error selection unit 57B BIPPM serial addition unit 57C TU3 BIPPM serial addition unit 57D TU2 BIPPM serial addition unit 57E TU12 BIPPM serial addition unit 57F BIPPM selection unit 57-2 Error count value initialization control unit (1 input inversion type) AND circuit) 57-3 BIP error detection unit (OR circuit) 57-4 BIPPM addition unit 58 BIPPM holding unit 58A TU3 BIPPM holding unit 58B TU2 BIPPM holding unit 58C TU12 BIPPM holding unit 58-1 BIPPM holding unit AM 59 PMRAM address control unit 59-1 Count plane holding unit (FF circuit with enable) 61 TU pointer serial processing unit 61-1 Pointer extraction unit 61-2 Pointer processing unit 61-3 RAM control unit 61-4, 89 'RAM 62 TU pointer timing generation unit 62-1 Address generation unit 71 UNEQ detection unit 71-4 UNEQ protection stage number addition unit 71-8 Release stage number selection unit (selector) 71-9 SL range control unit (AND circuit) 71-10 UNEQ display Detection unit (NOR circuit) 71-11 Addition condition detection unit (exclusive OR circuit) 71-12 UNEQ detection 4-stage detection unit (1 input inversion type A)
ND circuit) 71-13 UNEQ release stage number detection unit (AND circuit) 71-14 State transition occurrence detection unit (OR circuit) 71-15 UNEQ protection stage number information reset unit (1 input inversion AND circuit) 71-16 State transition unit (Exclusive OR circuit) 72 SL holding unit (UNEQ data holding unit) 72A UNE3 UNEQ data holding unit 72B TU2 UNEQ data holding unit 72C TU12 UNEQ data holding unit 72-1 SL holding RAM 73 SLM detection unit 73 -5 SLM protection stage number addition unit 73-8 SL range control unit (AND circuit) 73-9 Mismatch detection unit 73-10 Addition condition detection unit (exclusive OR circuit) 73-11 SLM detection 7-stage detection unit (AND circuit) ) 73-12 SLM cancellation three-stage detection unit (AND circuit) 73-13 State transition occurrence detection unit (OR circuit) 73- 4 SLM protection stage number information reset unit (OR circuit) 73-15 State transition unit (exclusive OR circuit) 74 Alarm bit holding unit (SLM data holding unit) 74A TU3 SLM data holding unit 74B TU2 SLM data holding unit 74C TU12 SLM data holding unit 74-1 UNEQ alarm bit holding unit 74-2 SLM alarm bit holding unit 74-3 Alarm bit write address control unit (1
Input inversion type OR circuit) 74-4 Write enable generation unit [decode circuit (D
EC)] 74-5 Alarm bit read address control unit (1
Input inversion type OR circuit) 74-6 Read select generation unit [decode circuit (DE
C)] 74-7 UNEQ select section (selector) 74-8 SLM select section (selector) 74-9 Line switching information read select generating section [decoding circuit (DEC)] 74-10 UNEQ line switching information selecting section (selector) 74-11 SLM line switching information select unit (selector) 74-12 Soft notification read select generation unit (selector) 74-13 UNEQ Soft notification select unit (selector) 74-14 SLM software notification select unit (selector) 75, 75A C2UNEQ Display serial detection unit 76, 76A, 76B V5UNEQ display serial detection unit 77 UNEQ display selection unit 77A UNEQ data selection unit 78 UNEQ serial detection unit 78A UNE3 serial detection unit 78B UNE2 serial detection unit 78C TT U12 UNEQ serial detector 81, 81A C2 mismatch serial detector 82, 82A, 82B V5 mismatch serial detector 83 Mismatch detection selector 83A SLM data selector 84 SLM serial detector 84A TU3 SLM serial detector 84B TU2 SLM Serial detection unit 84C TU12 SLM serial detection unit 91 FEBE detection unit 91-2 G1 byte FEBE detection unit 91-3 selector 92 FEBEPM serial processing unit 92-2 FEBE count value initialization control unit (1-input inversion AND circuit) 92 -3 FEBEPM Adder 93 FEBEPM Holding 93A TU3 FEBEPM Holding 93B TU2 FEBEPM Holding 93C TU12 FEBEPM Holding 93-1 FEBEPM Holding RAM 94 FEBEPM Cow Input value initialization control unit 94-3 timing control unit (1 input inversion type OR circuit) 94-4 read / write signal generation unit [decode circuit (D
EC)] 94-5 Write enable generation unit (OR circuit) 94-6 FEBEPM count value initialization request signal holding unit 94-7 FEBEPM count value initialization request signal selection unit (selector) 95 FERF serial processing unit 95-4 FERF Protection stage number addition unit 95-6 FERF selection unit (selector) 95-7 Addition condition detection unit (exclusive OR circuit) 95-8 FERF detection cancellation 10 stage detection unit (AND circuit) 95-9 FERF protection stage number information reset unit (1 input inversion type AND circuit) 95-10 State transition part (exclusive OR circuit) 96 FERF holding part 96A TU3 FERF data holding part 96B TU2 FERF data holding part 96C TU12 FERF data holding part 96-1 FERF Holding RAM 97 Alarm bit holding unit (FERF data holding unit) 9 -1 FERF alarm bit holder 97-2 alarm bit write address control unit (1
Input inversion type OR circuit) 97-3 Write enable generation unit [decode circuit (D
EC)] 97-4 Alarm bit read address control unit (1
Input inversion type OR circuit) 97-5 Read select generation unit [decode circuit (DE
C)] 97-6 FERF select section (selector) 97-7 Soft notification read select generation section [decoding circuit (DEC)] 97-8 FERF soft notification select section (selector) 97 'Offset counter section 98, 98A G1FEBE serial detection Part 98 'Matching detection part 99, 99A, 99B V5FEBE serial detection part 100 FEBE selection part 100A FEBE selection part 100' Mapping setting register group 101 FEEBEPM serial addition part 101A FE3 FEBEPM serial addition part 101B TU2 FEBEPM serial addition part 101C TU12 FEBEPM serial addition unit 101 'Selector unit 102, 102A G1 FERF display serial detection unit 103, 103A, 103B V5 FERF display serial detection unit 104 FERF Display detection selection unit 104A FERF data selection unit 106 FERF serial detection unit 106A TU3 FERF serial detection unit 106B TU2 FERF serial detection unit 106C TU12 FERF serial detection unit 123 TU3 / TUG3 setting register 124 TU2 / TUG2 setting register 125A signal size Recognition unit 125-127 Selector 231 Section overhead (SOH) 232 AU4 pointer 233 Payload (SPE) 234 TU pointer 235 VC3-POH 236 VC2-POH 237 VC12-POH 246 TU pointer detection unit 301 Subscriber terminal 302 Line termination device (NT) ) 303, 306 Transmission terminal equipment (LT) 304 Switching equipment (SW) 305 Multiplexing equipment (MUX) 307 Relay transmission line

Continuation of the front page (56) Reference JP-A-8-51406 (JP, A) JP-A-7-50652 (JP, A) JP-A-5-110534 (JP, A) JP-A-3-7438 (JP , A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04J 3/00-3/26 H04L 5/22-5/26

Claims (26)

(57) [Claims] 1. A POH termination processing device that performs POH termination processing on a signal in which a plurality of channel information transmitted by the SDH transmission method is multiplexed, and a POH common to each channel that performs POH termination calculation processing on this multiplexed signal. Thailand showing a termination processing unit, a universal storage unit of reading and writing for storing for each channel a result of the operation in the POH termination processing unit, the position of the J1 byte and the V5 byte of said multiplexing signal
The PO based on the ming signal and the type information of the multiplexed signal.
POH timing signal for processing in the H-terminal arithmetic processing unit
POH timing signal serial to generate serial number
A generator, and when performing the POH termination arithmetic processing on the multiplexed signal,
Using the stored information about the corresponding channel stored in the storage unit, the POH termination calculation processing unit uses the PO information.
By performing the H termination arithmetic processing and storing the obtained POH termination arithmetic result in the storage area of the corresponding channel of the storage unit, the POH termination arithmetic processing is performed as it is without separating the multiplexed signal for each channel. A POH termination processing device in the SDH transmission system, which is configured as described above. 2. A plurality of SDH transmission systems are used for transmission.
POH termination processing for signals with multiplexed channel information
In the POH terminal treatment device for applying Each channel that performs POH termination calculation processing on this multiplexed signal
A common POH termination arithmetic processing unit for the channel, The calculation result of the POH termination calculation processing unit is calculated for each channel.
A readable and writable storage unit for storing, Address for identifying each channel of the multiplexed signal
With an address creation unit that generates information, When performing the POH termination arithmetic processing on the multiplexed signal,
For the corresponding channel stored in the storage
By using the stored information, the POH termination arithmetic processing unit PO
H-terminal calculation processing is performed, and the obtained POH-terminal calculation result is
It can be stored in the storage area of the corresponding channel of the storage unit.
And divide the multiplexed signal into Cereal
It is configured to perform the POH termination calculation processing as it is.
Characteristic, POH termination processing device in SDH transmission system
Place 3. When the POH termination arithmetic processing in the POH termination arithmetic processing section, storage information about a corresponding channel read from the storage section and POH byte data for performing processing in the multiplexed signal are stored. 3. A latch section for temporarily storing the information is provided.
POH termination processing apparatus in SDH transmission system according to. 4. The POH termination arithmetic processing section is configured as a J1 and J2 byte serial termination processing section that serially performs termination processing of J1 bytes and J2 bytes included in the multiplexed signal, and the storage section is , The J1, J2 byte serial termination processing unit stores the calculation result for each channel, and
The POH termination processing device in the SDH transmission system according to claim 1 or 2, wherein the POH termination processing device is configured to supply storage information to a 1, J2 byte serial termination processing unit. 5. A multi-frame pattern serial detector for serially detecting the multi-frame pattern of the J1 byte and the J2 byte, the J1, J2 byte serial termination processing unit, and a multi-frame of the J1 byte and the J2 byte. A multi-frame pattern number serial control unit that serially controls the number of frames, a LOM serial detection unit that serially detects LOM of the J1 byte and J2 byte, and a CRC detection of the J1 byte and J2 byte described above. And a TIM serial detection unit for serially detecting the TIM of the J1 byte and the J2 byte, and the storage unit includes the multi-frame pattern serial detection unit. Part, number of multi-frame patterns Serial controller , LO
The calculation results of the M serial detection unit, the CRC serial detection unit, and the TIM serial detection unit are stored for each channel, and the multi-frame pattern serial detection unit, the multi-frame pattern number serial control unit, and the LOM described above are stored.
The PO in the SDH transmission system according to claim 4, wherein the PO is configured to supply storage information to the serial detection unit, the CRC serial detection unit, and the TIM serial detection unit.
H termination processing device. 6. The POH termination arithmetic processing unit serially performs termination processing of B3 bytes of B3 bytes and V5 bytes included in the multiplexed signal and termination processing of BIPPM of B3 bytes and V5 bytes included in the multiplexed signal B3, respectively. The storage unit is configured as a V5 byte serial termination processing unit, and the storage unit stores the calculation result in the B3, V5 byte serial termination processing unit for each channel.
The POH termination processing device in the SDH transmission system according to claim 1 or 2, which is configured to supply storage information to a V5 byte serial termination processing unit. 7. A BIP8 arithmetic serial processing unit in which the B3, V5 byte serial termination processing unit serially performs BIP8 arithmetic operation on the multiplex signal, and a BIP2 arithmetic serial processing unit serially performs BIP2 arithmetic operation on the multiplex signal. And a BIP error selecting section for selecting a BIP error signal output from the BIP8 arithmetic serial processing section and the BIP2 arithmetic serial processing section, and addition of BIPPM based on the BIP error signal selected by the BIP error selecting section. BI for serial calculation
And a storage unit for storing each calculation result of the BIPPM serial addition unit for each channel and supplying storage information to the BIPPM serial addition unit. P in the SDH transmission system according to claim 6 , characterized in that
OH termination processing device. 8. A BIP8 arithmetic serial processing unit in which the B3, V5 byte serial termination processing unit serially performs a BIP8 arithmetic operation on the multiplexed signal, and a BIPPM signal based on a BIP error signal from the BIP8 arithmetic serial processing unit. A first BIPPM serial addition unit that performs addition operation in serial, a BIP2 operation serial processing unit that performs BIP2 operation on the multiplexed signal in serial, and an addition operation of BIPPM based on a BIP error signal from the BIP2 operation serial processing unit. A second BIPPM serial addition unit that performs serially, and the first BIPPM serial addition unit and the second BIPP described above.
And a BIPPM selection unit that selects the BIPPM output from the M serial addition unit, and the storage unit stores each calculation result of the first BIPPM serial addition unit for each channel, The first BI
A first storage unit capable of supplying storage information to the PPM serial addition unit, and each calculation result in the second BIPPM serial addition unit are stored for each channel, and the second BIPPM is also stored.
7. The POH termination processing device in the SDH transmission system according to claim 6 , further comprising a second storage unit capable of supplying storage information to the serial addition unit. 9. The POH termination arithmetic processing section is configured as a UNEQ serial termination processing section that serially performs termination processing of UNEQ of C2 bytes and V5 bytes included in the multiplexed signal, and the storage section is SDH transmission according to claim 1 or 2 , characterized in that the operation result of the UNEQ serial termination processing unit is stored for each channel and the storage information is supplied to the UNEQ serial termination processing unit. POH termination processing device in the system. 10. A C2UNEQ display serial detection unit for serially detecting whether or not the C2 byte is in UNEQ display by the UNEQ serial termination processing unit, and serially for checking whether or not the V5 byte is in UNEQ display. V5UNEQ display serial detection unit for detecting, and C2UNEQ display serial detection unit and V5UNE
A UNEQ display selection unit that selects the UNEQ display detection signal output from the Q display serial detection unit, and a UNEQ display of C2 bytes and V5 bytes serially based on the UNEQ display detection signal selected by the UNEQ display selection unit. And a storage unit for storing the detection result of the UNEQ serial detection unit for each channel and supplying storage information to the UNEQ serial detection unit. 10. The P in the SDH transmission system according to claim 9 , characterized in that
OH termination processing device. 11. A C2UNEQ display serial detection unit for serially detecting whether or not the C2 byte is in UNEQ display by the UNEQ serial termination processing unit, and a UNEQ display detection signal from the C2UNEQ display serial detection unit. , A first UNEQ serial detection section for serially performing UNEQ display of C2 bytes, a V5UNEQ display serial detection section for serially detecting whether or not the V5 byte is in UNEQ display, and a UNEQ display from the V5UNEQ display serial detection section A second UNEQ serial detection unit that serially performs V5 byte UNEQ display based on the detection signal, and a UNEQ display selection unit that selects the UNEQ display output from the first UNEQ serial detection unit and the second UNEQ serial detection unit. Configured for Together are, together the storage unit stores the detection results in said 1UNEQ serial detector for each channel, said 1UNEQ
A first storage unit capable of supplying stored information to the serial detection unit;
Each of the detection results of the second UNEQ serial detection section is stored for each channel, and the second UNEQ serial detection section is provided with a second storage section capable of supplying storage information to the second UNEQ serial detection section. The POH termination processing device in the SDH transmission system according to claim 9 . 12. The POH termination arithmetic processing unit is configured as an SLM serial termination processing unit that serially terminates C2 byte and V5 byte SLMs included in the multiplexed signal, and the storage unit is The SDH transmission according to claim 1 or 2 , wherein the SLM serial termination processing unit is configured to store a calculation result for each channel and to supply storage information to the SLM serial termination processing unit. POH termination processing device in the system. 13. The SLM serial termination processing unit serially detects that the C2 byte has detected a mismatch, and the SLM serial termination processing unit serially detects that the V5 byte has detected a mismatch. A V5 mismatch serial detection unit, a mismatch detection selection unit for selecting a mismatch detection signal output from the C2 mismatch serial detection unit and the V5 mismatch serial detection unit, and a mismatch detection signal selected by the mismatch detection selection unit. Based on the above, it is configured to include an SLM serial detection unit that serially detects C2 byte and V5 byte SLMs, and the storage unit stores each detection result of the SLM serial detection unit for each channel. Both are configured to supply stored information to the SLM serial detector. It characterized the door, POH termination processing apparatus in SDH transmission system according to claim 1 wherein. 14. The C2 mismatch serial detection unit, which serially detects that the C2 byte is mismatch detected by the SLM serial termination processing unit, and C2 based on the mismatch detection signal from the C2 mismatch serial detection unit. A first SLM serial detection unit that serially detects the byte SLM, a V5 mismatch serial detection unit that serially detects that the V5 byte is mismatch detected, and a mismatch detection signal from the V5 mismatch serial detection unit. Based on the above, a second SLM serial detection unit that serially detects V5 byte SLMs and an SLM selection unit that selects the SLMs output from the first SLM serial detection unit and the second SLM serial detection unit are configured. In addition, the storage unit stores the first SLM serial detection The detection result at the output unit is stored for each channel, and the detection result at the first SLM serial detection unit and the detection result at the second SLM serial detection unit are stored for each channel. stores the, and a second storage unit capable of supplying stored information to said 2SLM serial detection unit, characterized in that it is configured, POH termination processing apparatus in SDH transmission system according to claim 1 wherein. 15. The POH termination arithmetic processing unit terminates G1 byte and V5 byte FEBE included in the multiplexed signal and the G1 byte and V5 byte FEBEP.
It is configured as an FEBE serial termination processing unit that performs M termination processing in serial, and the storage unit stores the calculation result in the FEBE serial termination processing unit for each channel and also to the FEBE serial termination processing unit. The POH termination processing device in the SDH transmission system according to claim 1 or 2, which is configured to supply stored information. 16. A G1F in which the FEBE serial termination processing unit serially performs FEBE detection of the G1 byte.
An EBE serial detection unit and a V5F that serially performs FEBE detection of the V5 byte
An EBE serial detector, an FEBE selector that selects the FEBE detection signals output from the G1FEBE serial detector and the V5FEBE serial detector, and the addition of FEBEPM based on the FEBE detection signal selected by the FEBE selector. FEB for serial calculation
An EPM serial addition unit is provided, and the storage unit stores each addition result of the FEBEPM serial addition unit for each channel.
Characterized in that it is configured to supply stored information to the serial addition unit, POH termination processing apparatus in SDH transmission system according to claim 1 5, wherein. 17. A G1F in which the FEBE serial termination processing unit serially performs FEBE detection of the G1 byte.
An EBE serial detector, a first FEBEPM serial adder that serially performs FEBEPM addition operation based on the FEBE detection signal from the G1FEBE serial detector, and a V5F that serially performs FEBE detection of the V5 byte.
An EBE serial detection unit, a second FEEBEPM serial addition unit that serially performs the FEBEPM addition operation based on the FEBE detection signal from the V5FEBE serial detection unit, and the above-mentioned first FEEBEPM serial addition unit and second FEB
And a FEBEPM selection unit that selects the FEEBEPM output from the EPM serial addition unit, and the storage unit stores the addition result of the FEBEPMS serial addition unit for each channel and FEBEPM
Characterized in that it is configured to supply stored information to the serial addition unit, POH termination processing apparatus in SDH transmission system according to claim 1 5, wherein. 18. The POH termination arithmetic processing section is configured as a FERF serial termination processing section for serially performing termination processing of FERF of G1 byte and V5 byte included in the multiplexed signal, and the storage section is SDH transmission according to claim 1 or 2 , characterized in that it is configured to store the calculation result in the FERF serial termination processing unit for each channel and to supply the stored information to the FERF serial termination processing unit. POH termination processing device in the system. 19. The G1 FERF display serial detector for serially detecting that the G1 byte displays FERF, and the V5 byte for serially displaying FERF. V5FERF display serial detection unit for detecting, and the above G1FERF display serial detection unit and V5FER
An FERF display detection selection unit that selects the FERF display detection signal output from the F display serial detection unit, and based on the FERF display detection signal selected by the FERF display detection selection unit, the G1 byte and the V5 byte F
The storage unit is configured to include an FERF serial detection unit that performs ERF detection serially, and the storage unit stores each detection result of the FERF serial detection unit for each channel and also to the FERF serial detection unit. P in the SDH transmission system according to claim 18 , characterized in that it is configured to supply information.
OH termination processing device. 20. The FERF serial termination processing unit detects the FERF of the G1 byte by serially detecting a G1FERF display serial detection unit, and a FERF display detection signal from the G1FERF display serial detection unit. From the first FERF serial detection unit that serially performs the FERF detection of the G1 byte, the V5FERF display serial detection unit that serially detects that the V5 byte displays FERF, and the V5FERF display serial detection unit. Based on the FERF display detection signal, the second FERF serial detection unit that serially performs the V5 byte FERF detection and the FERF display output from the first FERF serial detection unit and the second FERF serial detection unit are selected. Structured with FERF display selection unit Together are, the storage unit stores the detection results in said 1FERF serial detector for each channel, said 1FER
A first storage unit capable of supplying storage information to the F serial detection unit and each detection result of the second FERF serial detection unit can be stored for each channel, and storage information can be supplied to the second FERF serial detection unit. The SD according to claim 18 , characterized in that the SD is provided with a second storage section.
POH termination processing device in H transmission system . 21. A count value initialization unit for initializing an SPE count value, wherein the POH timing signal serial generation unit receives a timing signal indicating a position of a J1 byte and a V5 byte of the multiplexed signal, and the count value. A count value addition control unit that performs addition control of the SPE count value based on a signal from the initialization unit, and holds the SPE count addition value in the count value addition control unit for each channel, and holds for each channel Based on the write / read-free storage unit that can supply data to the count value initialization unit and the signal from the count value initialization unit and the type information of the multiplex signal, the POH termination calculation processing unit characterized in that the POH timing signal is configured to include a POH timing signal generator for generating for processing, SDH transmission according to claim 1, wherein POH termination unit in formula. 22. The POH termination processing section is included J1 bytes contained in said multiplexing signal, and J1, J2 byte serial termination processing section for performing termination processing J2 byte serial, in said multiplexing signal B3 BI of byte and V5 byte
Termination process of P and BIP of B3 byte and V5 byte mentioned above
B3, V5 byte serial termination processing unit for serially performing PM termination processing, and C2 byte and V5 byte UN included in the multiplexed signal
In addition to serially terminating the EQ, the above C2
UNEQ / SLM serial termination unit for serially terminating SLM of 5 bytes and V5 byte, and FE of G1 byte and V5 byte included in the multiplexed signal
BE termination processing and F of G1 byte and V5 byte described above
The FEBE / FERF serial termination processing unit is configured to perform serial termination processing of EBEPM and serially perform termination processing of FERF of G1 byte and V5 byte described above. , J2 byte serial termination unit,
The B3, V5 byte serial termination processing unit, the UNEQ
The calculation results in the SLM serial termination processing unit and the FEBE / FERF serial termination processing unit are stored for each channel, and the J1, J2 byte serial termination processing unit, the B3, V5 byte serial termination processing unit, and the UNEQ. S
3. The POH termination processing device in the SDH transmission system according to claim 1 or 2, wherein the POH termination processing device is configured to supply storage information to the LM serial termination processing unit and the FEBE / FERF serial termination processing unit. 23. When performing POH termination processing on a signal multiplexed with a plurality of channel information transmitted by the SDH transmission method, a tie indicating the position of the J1 byte and V5 byte of the multiplexed signal.
Each channel based on the ming signal and the type information of the multiplexed signal.
P for processing in the POH termination arithmetic processing unit common to the channel
The OH timing signal is serially generated , and the POH termination calculation processing unit uses the storage information about the POH termination processing calculation result for the corresponding channel stored in the readable and writable storage unit to terminate the POH termination in the POH termination calculation processing unit. By performing the arithmetic processing and storing the obtained POH termination arithmetic result in the storage area of the corresponding channel of the storage unit, it is possible to perform the POH termination arithmetic processing as serial without separating the multiplexed signal for each channel. A feature is a POH termination processing method in an SDH transmission system. 24. A plurality of data transmitted by SDH transmission system
POH termination processing for the signal in which the channel information of
When applying reason Address for identifying each channel of the multiplexed signal
Generates information and stores it in a readable and writable storage unit
POH termination for the corresponding stored channel
Each channel using the stored information about the processing operation result
POH termination calculation processing common to all
And the obtained POH end calculation result is stored in the storage unit.
By storing in the storage area of the channel
Duplicate signals are not separated for each channel
SDH transmission system characterized by performing edge arithmetic processing
POH termination treatment method in. 25. In a pointer / POH termination processing device that performs pointer processing and POH termination processing on a signal multiplexed with a plurality of channel information transmitted by the SDH transmission system, the multiplexed signal is not separated for each channel. A serial pointer processing unit for performing pointer processing as it is, and a tie indicating the position of the J1 byte and V5 byte of the multiplexed signal.
POH based on the ming signal and the type information of the multiplexed signal
Serially generate POH timing signal for termination processing
Form, characterized in that it is configured to include a serial POH termination processing section for performing POH termination remains Serial without separation per channel for said multiplexing signals, pointer · POH termination unit in the SDH transmission scheme. 26. A plurality of data transmitted by the SDH transmission system
Pointer processing is performed on the signal with multiplexed channel information.
Pointer / POH termination processing for physical processing and POH termination processing
In the device, This multiplexed signal is serialized without being separated for each channel.
A serial pointer processing unit that performs pointer processing as it is, Address for identifying each channel of the multiplexed signal
Information is generated and the multiplexed signal is separated for each channel.
Serial POH that is POH terminated without being serialized
Characterized in that it is configured with a termination processing unit,
Pointer / POH termination processing device for SDH transmission method
Place