JP3418162B2 - Method of etching TiN and SiO2 material and method of forming terminal via - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit (I).
C), and more particularly, to an improved method for etching at substantially the same rate of TiN and SiO ₂ materials.
There are valuable applications in making electrical connections in openings referred to as "terminal vias".

[0002]

2. Description of the Related Art Terminal vias are widely used in the manufacture of semiconductor integrated circuits, particularly in the manufacture of dynamic random access memory (DRAM) chips. As is well known to those skilled in the art, the final step in wafer processing involves the formation of specific via holes, so-called terminal vias, and wiring connections for externally connecting devices integrated in the chip.

[0003] The terminal via formation process is referred to as T
This is referred to as a V forming process, which will be described with reference to FIGS. FIG. 1 shows a structure 10 showing a portion of a silicon wafer in a manufacturing stage in which terminal vias are formed.
(Note that the figures are not necessarily drawn to scale). Returning to FIG. 1, the initial structures 10 are essentially each a gate conductor (GC) 1
2, a first metallization (M1) level conductive land 13 and a second metallization (M2)
It comprises a dielectric isolation layer 11 in which three metal layers called level contact pads 14 are embedded. Normal,
The dielectric layer 11 is composed of two parts. That is, BPSG
/ TEOS SiO ₂ material bottom layer 11A and pure Si
This is the upper layer 11B of the O ₂ material. As is evident from FIG. 1, the M2 metal pads 14 are 14A, 14B and 14C.
Of three metal layers. Typically, the center portion 14A is made of an aluminum / copper (Al / Cu) alloy and has two titanium / titanium nitride layers (Ti / TiN) 1
It is sandwiched between 4B and 14C. However, at the stage of manufacturing shown in FIG. 1, the material forming the upper double layer 14B is actually TiN.

Returning to FIG. 2, passivation layers 15 and 16 of SiO ₂ and Si ₃ N ₄ materials, respectively, are blanket deposited on structure 10 by PECVD. Following this step, spin-on deposition of the photoimide layer 17 is performed. As a result, a stack of these three layers is formed and used to protect the top surface of the chip during and after the packaging step.

Referring to FIG. 3, the photoimide material of layer 17 is exposed, fired, and developed as a standard for fabricating a photomask designated at 17.
Then, using this photomask 17, the underlying Si ₃ N ₄
The layers and the SiO ₂ layer 16 and 15 is patterned at the location of the bay (bay) indicated respectively 18 and 19 on the fuse and the metal M2 pad 14. Fuse is widely used in DRAM chips to disable a failed memory cell. In effect, the fuse controlling the failed memory cell is blown. In this example, the fuse is formed simultaneously with the gate conductor 12.

Next, the Si of the layers 16, 15 and 14B
_The 3N ₄ , SiO ₂ and TiN materials are etched into a desired pattern using the photomask 17. In this generation of DRAM chips, where the fuse is formed at the same time as the gate conductor 12 and is buried under the thick insulating layer 11, the purpose of the TV formation process is to overlie the gate conductor / fuse 12 deeply buried in the structure 10. Is to expose the central portion 14A of the M2 metal pad without removing the entire insulating material of the layer 11 of FIG.

[0007] Etching is performed using CF ₄ / CHF ₃ chemistry and Applie, Santa Clara, California, USA.
AME, a reactor commercially available from d Materials
This is performed in the MxP + chamber of the 5000 RIE etching apparatus. The wafer is placed on a reactor electrostatic chuck that is typically cooled with a helium (He) flow. The following operating conditions are appropriate: CF ₄ flow: 60 sccm CHF ₃ flow: 10 sccm Ar flow: 100 sccm Pressure: 40 mT Cathode / wall temperature: 15/15 ° C. He backside cooling: 14 Torr Power: 1000 W

[0008] The end point of the etch is determined by a sharp drop in the intensity of the 387.5 radiation (CN) detected by the optical spectrometer. The final structure at this stage of the TV formation process is shown in FIG. The terminal via etching step described above works well, but utilizes a photomask that produces some polymer by-products when etched with CHF ₃ , which makes the reactor very fast Get dirty. This step is hereinafter referred to as a TV etching step.

FIG. 5 shows the top surface of the structure 10 of FIG. 4 to illustrate the relative placement of the M2 metal pads 14, and the fuse bays 20 and individual fuses 21 contained therein.

Table 1 below summarizes the essential features of the TV etching step with the CF ₄ / CHF ₃ based chemistry described above. Table 1 Conductor etching rate: 275 nm / mim Conductor etching uniformity: 1.7% SiO ₂ : TiN Selectivity: 11 Polymer formation: Yes

Recently, a new generation 64 Mbyte DRAM chip has been designed by different means for high device density integration. In this case, the fuse is made at the first metallization (MI) level and is therefore much closer to the top surface of the structure 10. This new design is shown schematically in FIG.
Shown in In FIG. 6, the structure indicated by 10 'is very similar to the structure 10 of FIG. 1 except that the fuse is fabricated with the M1 metal land 13 rather than with the gate conductor 12. Normally, the thickness of the SiO ₂ layer 11B is equal to 450 nm, and the thickness of the TiN layer 14B is 35 nm.

Therefore, without removing the dielectric material above the M1 metal land / fuse 13, the M2 metal pad central portion 1 is removed.
The purpose of exposing 4A will be much more critical and difficult than before. Unfortunately, the TV formation process described above has not been able to meet this purpose because this particular TV etching step is not well controlled. In fact, the structure obtained at the end of the normal TV formation process is:
Since the control of the TV etching step is not good, the structure shown in FIG. 7 or the structure shown in FIG. 8 is used.

In the example shown in FIG. 7, the M1 metal land / fuse 13 is not exposed in the opening 18,
Since the material has not been completely removed, some TiN material in layer 14B remains over the central portion 14A of the M2 metal pad in opening 19. As a result, the contact resistance with the central portion 14A of the M2 metal pad increases.

On the contrary, FIG.
Although all of the TiN material has been removed, an example is shown where the M1 metal land / fuse 13 is exposed at the opening 18 and can cause metal corrosion and contamination.

Therefore, in this new generation DRAM chip,
The TV etching step described above is obviously not appropriate due to three problems. 1. As mentioned above, if some TiN material remains on the central portion 14A of the M2 metal pad, some contact resistance problems arise. 2. S of the layer 11B for protecting the metal land / fuse 13
Conversely, if the iO ₂ material is etched, metal corrosion and contamination problems arise. 3. Finally, polymer by-products are formed inside the reactor, causing a problem of equipment up-time.

It is clear that the TV etching step of the conventional TV formation process utilizing the CF ₄ -CHF ₃ based chemistry described above is not compatible with the structure 10 'of FIG.

Other chlorine-based gases, such as Cl ₂ , HCl or BCl _3, are well suited for etching TiN, which is selective for SiO ₂ , but they etch aluminum copper very quickly, so such gases. , M
The central portion 14A of the two metal pads is violently attacked.

Therefore, a very clean process for etching the TiN material forming the outer layer of the M2 metal pad 14 without removing all of the SiO ₂ material on the M1 metal land / fuse 13 is now highly desirable.

[0019]

The main object of the invention is to solve the above invention therefore is to provide an improved method for etching at substantially the same rate of TiN and SiO ₂ materials.

Another object of the present invention is to provide a method for forming a M2 without exposing an M1 metal land / fuse in a TV forming process.
Can be etched outer TiN layer of metal pads is to provide an improved method of etching at substantially the same rate of TiN and SiO ₂ materials.

It is another object of the present invention to provide an improved method for a clean process that etches TiN and SiO ₂ materials at substantially the same rate without producing polymeric by-products.

[0022]

According to the present invention, there is provided a method of etching a TiN and SiO ₂ material, wherein a metal pad comprising a bottom metal layer, an Al-Cu layer and a TiN layer thereon is provided thereon. providing a structure which is a part of a silicon wafer including, a power lower than 500W at the wafer on the electrostatic chuck of the vacuum chamber of the RIE etcher addition formed an upper insulating SiO ₂ layer The structure is larger than 40 sccm NF so that the selectivity of SiO ₂ : TiN is equal to about 1: 4.
Contacting with _three gas streams. [0023] According to another feature of the invention, a method of forming a terminal via (TV) in a semiconductor structure, comprising:
A bottom metal layer, providing a structure which is a part of a semiconductor wafer including the Al-Cu layer and thereon an upper insulating SiO ₂ layer metal pads formed thereon comprising a TiN layer, the SiO ₂ by PECVD on the structure
Sequentially depositing a thin passivation layer and a thick passivation layer of Si ₃ N ₄ , forming a masking layer having a desired pattern on the structure,
The masking layer is used to expose the SiO ₂ underlayer using a CF ₄ / NF ₃ chemistry.
Etching the ₃ N ₄ layer, less power 500W was added at the wafer on the vacuum chamber of the electrostatic chuck of the RIE etching apparatus, SiO _2: Selectivity of TiN is about 1: to equal 4 In addition, the structure
The method comprising contacting a 0sccm larger NF ₃ gas stream, without exposing the bottom metal layer, using a NF ₃ chemistry to create a terminal via completely removed TiN layer on the metal pads And etching the SiO ₂ layer and the TiN layer. [0024] According to another important feature of the invention, the pressure of the helium gas normally used to cool the wafer placed on the electrostatic chuck is reduced as much as possible, e.g.
Raise the temperature of the wafer to achieve the lowest SiO ₂ : TiN selectivity equal to 1: 2 . [0030] TiN and SiO ₂ are etched at substantially the same rate ( the selectivity of SiO ₂ : TiN is about
1: 2 ). NF ₃ gas was chosen for more chemically etched materials such as silicon nitride, etc., which have a high etch rate and are suitable for use as base compounds in the above two etching processes. Because it is. Surprisingly, this did not adversely affect the SiO ₂ etch rate, indicating a high TiN etch rate. In addition, this allows for a clean process without the formation of polymers and RIE for cleaning.
Multiple batches of wafers (batc) without shutting down the reactor
h) can be processed. [0031] Furthermore, it has been found that as high a wafer temperature as possible is advantageous for obtaining as low a selectivity as possible. Typically, wafer temperatures above 100 ° C. are adequate. This is easily obtained by significantly reducing the cooling fluid flow. This is the same as Step 14
It will be evident from the fact that the He wafer backside cooling pressure parameter is 2 Torr instead of Torr. Power is less than 500 W, NF ₃ flow exceeds 40 sccm, H
If e backside cooling pressure is 14 Torr, Step 2 Si
The selectivity of O ₂ : TiN is equal to about 1: 4 and cannot be lowered. 1: 2 S worth 2 torr
Selectivity of iO ₂ : TiN can be obtained (the wafer temperature in this case is estimated to be equal to about 150 ° C.).

According to another feature of the invention, a semiconductor device includes:
Forming a terminal via (TV) in the
It consists of a bottom metal layer, an Al-Cu layer and a TiN layer on it.
Upper insulating SiO 2 with a metal pad formed thereon_Twolayer
Providing a structure that is part of a semiconductor wafer including:
Step and SiO on the structure by PECVD_Two
Thin passivation layer and Si_ThreeN _FourThick passivation
Sequentially depositing a layer of
Forming a masking layer having a pattern;
CF_Four/ NF_ThreeThe above-mentioned SiO using chemicals_TwoExposing the underlayer
Using the masking layer to remove the Si
_ThreeN_FourEtching the layer and RIE etching
Place the wafer on the electrostatic chuck in the vacuum chamber of the device
Power of less than 500 W_Two: TiN
The structure is 40s so that the selectivity is equal to about 4.
NF greater than ccm_ThreeIn the step of contacting the gas stream
On the metal pad without exposing the bottom metal layer
Completely removes TiN layer to create terminal vias
NF to do_ThreeThe above-mentioned SiO using chemicals_TwoLayers and said
Etching a TiN layer.
Is done.

According to another important feature of the present invention, the pressure of the helium gas normally used for cooling the wafer placed on the electrostatic chuck is reduced as much as possible, for example, with the lowest SiO 2 equal to about 2. ₂ : Raise wafer temperature to achieve TiN selectivity.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An improved terminal via (TV) forming process will now be described. Structure 10 'of FIG.
Is a superposed layer 1 of SiO ₂ , Si ₃ N ₄ and photoimide
Coated with 5, 16 and 17, the photoimide of layer 17 is exposed and developed to form photomask 17 as described above with reference to FIGS.

This new TV etching process is:
To remove the TiN material more quickly and reduce sensitivity to pattern effect factors, NF ₃
It is carried out in two steps using the chemicals of the substrate. These two steps are the same as described above for the complete clustering process.
Performed in the same MxP + chamber of the 5000 RIE etcher.

The CF ₄ / NF ₃ chemistry is used in the following steps to etch the Si ₃ N ₄ material of layer 16 in a first step. Si ₃ N ₄ etching NF ₃ flow: 80 sccm CF ₄ flow: 40 sccm Pressure: 150 mT Cathode / wall temperature: 15/15 ° C. He cooling pressure: 14 Torr Power: 1000 W

The end point of the etch is defined by a sharp increase in the 483 nm (CO) radiation intensity detected by the optical spectrometer. The resulting structure is shown in FIG. As is apparent from FIG. 9, the thin SiO ₂ passivation layer 15 is exposed in the openings 18 and 19.

Next, during a second step, the SiO of layer 15
_2. The TiN of layer 14B and the SiO _{2 of} layer 11B are etched in the same chamber using NF ₃ chemistry under the following operating conditions. Etching of TiN and SiO ₂ NF ₃ flow: 50 sccm Pressure: 50 mT Cathode / wall temperature: 15/15 ° C. He cooling pressure: 2 Torr Power: 400 W

TiN and SiO ₂ are etched at substantially the same rate (selectivity equal to 2). NF ₃ gas was chosen for more chemically etched materials such as silicon nitride, etc., which have a high etch rate and are suitable for use as base compounds in the above two etching processes. Because it is. Surprisingly, this did not adversely affect the SiO ₂ etch rate, indicating a high TiN etch rate. In addition, this allows for a clean process without polymer formation,
Multiple wafer batches can be processed without stopping the RIE reactor for cleaning.

Furthermore, it has been found that a wafer temperature as high as possible is advantageous for obtaining a selectivity as low as possible. Typically, wafer temperatures above 100 ° C. are adequate. This is easily obtained by significantly reducing the cooling fluid flow. This is the same as Step 14
It will be evident from the fact that the He wafer backside cooling pressure parameter is 2 Torr instead of Torr. Power is less than 500 W, NF ₃ flow exceeds 40 sccm, H
e If the backside cooling pressure is 14 Torr, the selectivity of step 2 is equal to about 4 and cannot drop below it. At a value of 2 Torr, a valuable 2 selectivity can be obtained (the wafer temperature in this case is estimated to be equal to about 150 ° C.).

Finally, an improvement of 1.7-0.7% can be seen in the uniformity of the SiO ₂ etching.

FIG. 10 shows the final structure. As can be seen in FIG. 10, all of the TiN material in layer 14B has been removed, but a sufficient amount of insulating layer 11B remains on M1 land / fuse 13.

Table 2 below summarizes the overall characteristics of the improved NF ₃ -based chemistry of the TV etching process of the present invention. Table 2 SiO ₂ etching rate: 128 nm / min SiO ₂ etching uniformity: 0.7% SiO2: TiN selectivity: 2 polymer accumulation: None Residual TiN: None

The absence of polymer accumulation proves that this new TV etching step is clean.

In summary, the following is disclosed regarding the configuration of the present invention.

(1) TiN and SiO_TwoEtch material
A bottom metal layer, an Al-Cu layer,
A metal pad consisting of a TiN layer thereon is formed thereon.
Upper insulating SiO_TwoSilicon wafer with layers
Providing a structure that is part of a RIE etch
Wafer on an electrostatic chuck in a vacuum chamber of a
And apply a power of less than 500 W to the
O_Two: So that the selectivity of TiN is equal to about 4
NF greater than 40 sccm_ThreeContact with gas flow
And b. (2) on the electrostatic chuck to reduce selectivity
Helium used to cool the placed wafer
・ Lower gas pressure and higher wafer temperature
The method according to (1). (3) SiO_Two: The selectivity of TiN is equal to about 2.
Thus, the helium cooling pressure is equal to 2 Torr
The method according to (2). (4) The temperature of the wafer is higher than 100 ° C. (3).
The method described in. (5) The vacuum chamber is an AME5000RIE etch
Described in (2) above, which is an MxP + chamber of the
Method. (6) The RIE step NF_ThreeFlow: 50sccm Pressure: 50mT Cathode / wall temperature: 15/15 ° C He cooling pressure: 2 Torr Power: 400W The method according to (5), wherein the method is performed under the following operating conditions. (7) Form terminal vias (TV) in the semiconductor structure
A bottom metal layer, an Al-Cu layer and a
A metal pad consisting of a TiN layer on top is formed thereon.
Upper insulating SiO_TwoAnd a part of the semiconductor wafer
Providing a structure; and providing PE on the structure.
SiO by CVD_TwoThin passivation layer and Si_Three
N _FourStep of sequentially depositing a thick passivation layer
And masking having a desired pattern on the structure
Forming a layer; CF_Four/ NF_ThreeUsing chemicals
The SiO_TwoTo expose the underlayer,
Using the Si layer_ThreeN_FourStep to etch the layer
Terminal vias without exposing the bottom metal layer
NF to create_ThreeThe above-mentioned SiO using chemicals_Two
Etch the layer and the TiN layer to remove
Completely removing said TiN layer. (8) Electrostatic chamber of vacuum chamber of RIE etching equipment
Place the wafer on the rack and power it to less than 500W
Is added, and SiO_Two: The selectivity of TiN is equal to about 4.
As described above, the structure is formed with an NF larger than 40 sccm._ThreeMoth
(7) comprising the step of contacting
Method. (9) On the electrostatic chuck to reduce selectivity
Helium used to cool the placed wafer
・ Lower gas pressure and higher wafer temperature
The method according to (8). (10) The step of forming a masking layer is a photo
Depositing a layer of imide;
Exposing to light and developing the photoimide layer.
(7). (11) Si_ThreeN_FourSaid step of etching the material
MxP + Chan of AME5000RIE etching equipment
In the bath NF_ThreeFlow: 80sccm CF_FourFlow: 40sccm Pressure: 150mT Cathode / wall temperature: 15/15 ° C He cooling pressure: 14 Torr Power: 1000W The method according to (9), wherein the method is performed under the following operating conditions. (12) TiN and SiO_TwoOf said material etching
Step is the same as AME5000 RIE etching equipment
For the whole assembly process in MxP + chamber NF_ThreeFlow: 50sccm Pressure: 50mT Cathode / wall temperature: 15/15 ° C He cooling pressure: 2 Torr Power: 400W The method described in (11) above, which is performed under the operating conditions of
Law. (13) The above (7), wherein the bottom metal layer comprises a fuse.
The method described in.

[Brief description of the drawings]

FIG. 1 is a diagram showing a semiconductor structure subjected to basic steps of a conventional terminal via (TV) forming process.

FIG. 2 shows a semiconductor structure subjected to the basic steps of a conventional terminal via (TV) formation process.

FIG. 3 illustrates a semiconductor structure subjected to basic steps of a conventional terminal via (TV) formation process.

FIG. 4 illustrates a semiconductor structure subjected to the basic steps of a conventional terminal via (TV) formation process.

FIG. 5 is a top view of the structure 10 at the stage of FIG. 4 to show the relative arrangement of the M2 pad and the fuse bay.

FIG. 6 shows the structure 10 of FIG. 1 slightly modified to take into account that the fuse is made of metal lands at an initial metallization level.

FIG. 7 illustrates the use of an etching step using CF ₄ / CHF ₃ chemistry in a conventional TV forming process;
FIG. 7 is a diagram showing the structure of FIG. 6 that should be obtained due to insufficient control.

FIG. 8 illustrates the use of an etching step using CF ₄ / CHF ₃ chemistry in a conventional TV formation process;
FIG. 7 is a diagram showing the structure of FIG. 6 that should be obtained due to insufficient control.

FIG. 9 shows the structure of FIG. 6 subjected to the final step of an improved TV formation process implemented in two steps using NF ₃ / CF ₄ chemistry and then NF ₃ chemistry in accordance with the present invention. FIG.

FIG. 10 shows NF ₃ / CF ₄ chemicals according to the invention,
FIG. 6 is then subjected to the final steps of an improved TV formation process performed in two steps using NF ₃ chemistry
FIG. 3 is a diagram showing the structure of FIG.

[Explanation of symbols] 10 Structure 10 'structure 11A insulating layer 11B insulating layer 12 Gate conductor 13 M1 Metal Land / Fuse 14A metal pad 14B metal pad 14C metal pad 15 Passivation layer 16 Passivation layer 17 Photomask photoimide layer 18 opening 19 Opening

────────────────────────────────────────────────── ─── front page continued (51) Int.Cl. ⁷ identifications FI H01L 27/108 (72) inventor Francois Reveru France 77240 Cesson Ryu de Interview-Shanpo 13 (56) references Patent Rights 8- 321545 (JP, A) JP-A-10-173049 (JP, A) JP-A-2000-133633 (JP, A) JP-A-2000-174126 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , (DB name) H01L 21/3065 H01L 21/3205 H01L 21/3213 H01L 21/768 H01L 21/8242 H01L 27/108

Claims (13)

(57) [Claims] 1. A method of etching a TiN and SiO ₂ material, comprising: a bottom metal layer; and an upper insulating SiO ₂ layer on which a metal pad including an Al—Cu layer and a TiN layer is formed. Providing a structure that is part of a silicon wafer, comprising: placing the wafer on an electrostatic chuck of a vacuum chamber of an RIE etcher, applying less than 500 W to it, and selecting SiO ₂ : TiN. Contacting said structure with a flow of NF ₃ gas greater than 40 sccm such that the property is equal to 1: 4 . 2. A method for etching a TiN and SiO ₂ material, comprising: a bottom metal layer; and an upper insulating SiO ₂ layer having a metal pad comprising an Al—Cu layer and a TiN layer thereon formed thereon. Providing a structure that is part of a silicon wafer, comprising: placing the wafer on an electrostatic chuck of a vacuum chamber of an RIE etcher, applying less than 500 W to it, and selecting SiO ₂ : TiN. The pressure of the helium gas used to cool the wafer placed on the electrostatic chuck is reduced to less than 14 Torr and the temperature of the wafer is increased so as to increase the temperature of the wafer in order to reduce the resistance to less than 1: 4. Contacting the structure with a flow of NF ₃ gas greater than 40 sccm. 3. The method of claim 2 wherein said helium cooling pressure is equal to 2 Torr so that said selectivity of SiO ₂ : TiN is equal to 1: 2 . 4. The method according to claim 3, wherein the temperature of the wafer is higher than 100 ° C. 5. The method according to claim 1, wherein said vacuum chamber is AME5000RIE.
3. The method according to claim 2, wherein the etching apparatus is a MxP + chamber. 6. The method according to claim 5, wherein the RIE step is performed under the following operating conditions: NF ₃ flow: 50 sccm pressure: 50 mT Cathode / wall temperature: 15/15 ° C. He cooling pressure: 2 Torr power: 400 W . 7. A terminal via (T) in a semiconductor structure.
V), comprising: a bottom metal layer; and an upper insulating SiO ₂ layer on which a metal pad composed of an Al—Cu layer and a TiN layer is formed. Providing sequentially a thin passivation layer of SiO ₂ and a thick passivation layer of Si ₃ N ₄ by PECVD on said structure; masking having a desired pattern on said structure Forming a layer, etching the Si ₃ N ₄ layer using the masking layer to expose the SiO ₂ underlayer using CF ₄ / NF ₃ chemistry, and the bottom metal layer to create a terminal via without exposing the, by etching the TiN layer and the SiO ₂ layer by using a NF ₃ chemicals, before on the metal pad Method comprising completely remove steps TiN layer. 8. A structure in which a wafer is placed on an electrostatic chuck in a vacuum chamber of an RIE etching apparatus and a power of less than 500 W is applied to the wafer so that the selectivity of SiO ₂ : TiN is equal to 1: 4. the comprises the step of contacting with 40sccm larger NF ₃ gas flow, method of claim 7. 9. The method of claim 8, wherein the pressure of the helium gas used to cool the wafer placed on the electrostatic chuck is reduced to increase the temperature of the wafer to reduce selectivity. Method. 10. The method of claim 7, wherein said step of forming a masking layer comprises the steps of depositing a layer of photoimide, exposing to the desired pattern, and developing the photoimide layer. the method of. 11. The step of etching a Si ₃ N ₄ material may be performed using MxP + of an AME5000 RIE etching apparatus.
The method according to claim 9, which is carried out in the chamber under the following operating conditions: NF ₃ flow: 80 sccm CF ₄ flow: 40 sccm Pressure: 150 mT Cathode / wall temperature: 15/15 ° C. He cooling pressure: 14 Torr power: 1000 W 12. The step of etching the TiN and SiO ₂ materials is performed in the same MxP + chamber of an AME5000 RIE etcher for a NF ₃ flow: 50 sccm pressure: 50 mT cathode / wall temperature: 15/15 ° C. for the entire assembly process. The method according to claim 11, which is carried out under operating conditions of He cooling pressure: 2 Torr power: 400 W. 13. The method of claim 7, wherein said bottom metal layer comprises a fuse.