JP3418962B2 - Output current monitor circuit - Google Patents
Output current monitor circuitInfo
- Publication number
- JP3418962B2 JP3418962B2 JP04037992A JP4037992A JP3418962B2 JP 3418962 B2 JP3418962 B2 JP 3418962B2 JP 04037992 A JP04037992 A JP 04037992A JP 4037992 A JP4037992 A JP 4037992A JP 3418962 B2 JP3418962 B2 JP 3418962B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- current
- output
- current detection
- dummy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000001514 detection method Methods 0.000 claims description 44
- 238000012544 monitoring process Methods 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000007599 discharging Methods 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
- Particle Accelerators (AREA)
- Rectifiers (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は直流高圧電源から負荷に
流れる出力電流をモニターする出力電流モニター回路に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output current monitor circuit for monitoring an output current flowing from a DC high voltage power supply to a load.
【０００２】[0002]
【従来の技術】図４及び図５に基づいて従来例における
出力電流モニター回路を説明する。図４において、トラ
ンスＴ１の１次側の入力電圧ＶｉｎはトランジスタＱ１
によってスイッチングされる。制御部１はこのトランジ
スタＱ１を制御する。２次側はコンデンサＣ１〜Ｃｎと
ダイオードＣＲ１〜ＣＲｎによってｎ段の直流高圧−Ｈ
Ｖを発生させている。出力電流ＩＬとダミー電流Ｉｄは
トランスＴ１の零電位のラインの電流検出抵抗Ｒｓに流
れた後、出力電流ＩＬは負荷抵抗ＲＬに流れ、ダミー電
流Ｉｄはダミー抵抗Ｒｄに流れる。電流検出抵抗Ｒｓに
おける電圧降下は抵抗Ｒ１、Ｒ２、ダイオードＣＲ１０
０、ＣＲ１０１を介して集積回路Ｕ１に入力される。こ
の集積回路Ｕ１の出力が電流モニターとしてモニターさ
れる。なお、ダイオードＣＲ１００、ＣＲ１０１はサー
ジ電圧に対する集積回路Ｕ１の保護用である。また、記
号ＶCCとＶEEは集積回路Ｕ１の電源電圧であり、抵抗Ｒ
４は集積回路Ｕ１の帰還用抵抗であり、抵抗Ｒ３、コン
デンサＣ１０１は集積回路Ｕ１の出力段を構成してい
る。2. Description of the Related Art A conventional output current monitor circuit will be described with reference to FIGS. In FIG. 4, the input voltage Vin on the primary side of the transformer T1 is the transistor Q1.
Is switched by. The control unit 1 controls the transistor Q1. On the secondary side, capacitors C1 to Cn and diodes CR1 to CRn are used for n-stage high voltage DC-H.
V is generated. After the output current IL and the dummy current Id flow through the current detection resistor Rs of the zero potential line of the transformer T1, the output current IL flows through the load resistor RL and the dummy current Id flows through the dummy resistor Rd. The voltage drop in the current detection resistor Rs is caused by the resistors R1 and R2 and the diode CR10.
0, input to integrated circuit U1 via CR101. The output of this integrated circuit U1 is monitored as a current monitor. The diodes CR100 and CR101 are for protecting the integrated circuit U1 against surge voltage. The symbols V CC and V EE are the power supply voltage of the integrated circuit U1, and the resistance R
Reference numeral 4 denotes a feedback resistor of the integrated circuit U1, and the resistor R3 and the capacitor C101 form an output stage of the integrated circuit U1.
【０００３】図５は図４の従来例の出力電流モニター回
路における出力電流ＩＬと電流モニターの関係を示す電
流モニター特性表である。図から明らかなように、出力
電流が零になっても電流モニターの値は零にならない。FIG. 5 is a current monitor characteristic table showing the relationship between the output current IL and the current monitor in the conventional output current monitor circuit of FIG. As is clear from the figure, the value of the current monitor does not become zero even if the output current becomes zero.
【０００４】[0004]
【発明が解決しようとする課題】直流高圧電源から負荷
に流れる出力電流は数１０μＡの非常に微小な電流であ
るので、ダミー抵抗に流れるダミー電流を無視すること
ができない。従って従来の出力電流モニター回路のよう
に、出力電流とダミー電流の合計した電流を電流検出抵
抗で検出するのでは、電流モニターにダミー電流が重畳
されており電流モニターと出力電流とはリニアな関係と
はならない。Since the output current flowing from the DC high voltage power supply to the load is a very small current of tens of microamperes, the dummy current flowing through the dummy resistor cannot be ignored. Therefore, as in the conventional output current monitor circuit, when the total current of the output current and the dummy current is detected by the current detection resistor, the dummy current is superimposed on the current monitor, and the linear relationship between the current monitor and the output current. Does not mean
【０００５】本発明はこのような点に鑑みてなされたも
のであり、上記の従来技術の欠点を除き、出力電流を正
確にモニターできる出力電流モニター回路を提供するこ
とを目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an output current monitor circuit capable of accurately monitoring an output current, excluding the above-mentioned drawbacks of the prior art.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
に本発明による出力電流モニター回路は、第１の出力端
子と第２の出力端子との間に直流高圧を発生する直流高
圧電源がこの第１の出力端子とアースとの間に接続され
た負荷に流す出力電流を、モニターする出力電流モニタ
ー回路において、第１の電流検出抵抗と第２の電流検出
抵抗とダミー抵抗とが直列に接続された第１の直列回路
と、第１の抵抗と第２抵抗とが直列に接続された第２の
直列回路とを備え、前記第１の直列回路の一端である第
１の電流検出抵抗の端部を、前記第２の出力端子に接続
し、前記第１の直列回路の他端であるダミー抵抗の端部
を、前記第１の出力端子に接続し、かつ前記第１の電流
検出抵抗と前記第２の電流検出抵抗との接続点をアース
に接続すると共に、前記第２の直列回路の一端である第
１の抵抗の端部を、前記第２の出力端子に接続し、前記
第２の直列回路の他端である第２の抵抗の端部を、前記
第１の直列回路の前記第２の電流検出抵抗と前記ダミー
抵抗との接続点に接続することによって、前記出力電流
および前記ダミー抵抗に流れるダミー電流を、前記第１
の電流検出抵抗に流し、前記ダミー電流だけを前記第２
の電流検出抵抗と前記ダミー抵抗とに流し、前記第１の
電流検出抵抗の電圧によって前記第１の抵抗に発生する
電圧と、前記第２の電流検出抵抗の電圧によって前記第
２の抵抗に発生する電圧とによって、前記第１の抵抗と
前記第２の抵抗との間に生ずる電圧を、前記第１の抵抗
と前記第２の抵抗との接続点から出力し、この出力され
た電圧から前記出力電流をモニターすることに特徴を有
している。請求項１に記載の出力電流モニター回路にお
いて、前記第１の電流検出抵抗の抵抗値と前記第２の電
流検出抵抗の抵抗値とを同じ値にし、かつ、前記第１の
抵抗の抵抗値と前記第２の抵抗の抵抗値とを同じ値にし
たことを特徴とする。 In order to solve the above problems, the output current monitor circuit according to the present invention is provided with a first output terminal.
DC high voltage that generates high DC voltage between the child and the second output terminal
A piezoelectric power supply is connected between this first output terminal and ground.
Output current monitor to monitor the output current flowing through the load
Circuit, the first current detection resistor and the second current detection
First series circuit in which a resistor and a dummy resistor are connected in series
And a second resistor in which a first resistor and a second resistor are connected in series.
And a series circuit, which is one end of the first series circuit.
Connect the end of the current detection resistor 1 to the second output terminal
The end of the dummy resistor which is the other end of the first series circuit
Is connected to the first output terminal, and the first current is
The connection point between the detection resistor and the second current detection resistor is grounded
And a first end of the second series circuit.
The end of the resistor 1 is connected to the second output terminal,
The end of the second resistor, which is the other end of the second series circuit, is
The second current detection resistor of the first series circuit and the dummy
By connecting to the connection point with a resistor, the output current
And a dummy current flowing through the dummy resistor,
To the second current detection resistor and only the dummy current is passed to the second
Current detection resistor and the dummy resistor,
Generated in the first resistor by the voltage of the current detection resistor
The voltage and the voltage of the second current detection resistor
And the voltage generated in the second resistor,
The voltage generated between the second resistor and the first resistor is
Is output from the connection point between the second resistor and the
The output current is monitored from the applied voltage . The output current monitor circuit according to claim 1.
The resistance value of the first current detection resistor and the second current detection resistor.
The resistance value of the flow detection resistor is set to the same value, and the first
Set the resistance value of the resistor and the resistance value of the second resistor to the same value.
It is characterized by that.
【０００７】[0007]
【作用】ダミー抵抗に流れるダミー電流と負荷に流れる
出力電流を第１の抵抗に流す。さらに、ダミー電流だけ
を第２の抵抗に流す。第１の抵抗による電圧降下と第２
の抵抗による電圧降下から出力電流を求める。このよう
に、第１と第２の抵抗を電流検出用抵抗とすることによ
って負荷に流れる出力電流を正確にモニターすることが
できる。The dummy current flowing through the dummy resistor and the output current flowing through the load are passed through the first resistor. Further, only the dummy current is passed through the second resistor. The voltage drop due to the first resistance and the second
Calculate the output current from the voltage drop due to the resistance of. Thus, the output current flowing through the load can be accurately monitored by using the first and second resistors as the current detection resistors.
【０００８】[0008]
【実施例】以下、本発明の一実施例である出力電流モニ
ター回路を図１、図２に基づいて説明する。なお、図
４、図５と同一符号を付したものはそれぞれ同一の要素
を示しており、説明を省略する。図１において、第１の
抵抗である電流検出抵抗Ｒｓ１と第２の抵抗であるＲｓ
２は同じ抵抗値に設定しておく。抵抗Ｒ１とＲ２は同じ
抵抗値であり、電流検出抵抗Ｒｓ１とＲｓ２に比べて充
分に高い抵抗値である。負荷抵抗ＲＬはアースに対して
負の高圧、−ＨＶが印加されている。また、直列に接続
されている電流検出抵抗Ｒｓ２とダミー抵抗Ｒｄにも−
ＨＶが印加されている。従って、電流検出抵抗Ｒｓ１に
は負荷抵抗ＲＬに流れる出力電流ＩＬとダミー抵抗Ｒｄ
に流れるダミー電流Ｉｄが流れ、その電圧降下はＶｓ１
（アースに対して正の電圧）である。また、電流検出抵
抗Ｒｓ２にはダミー抵抗Ｒｄに流れるダミー電流Ｉｄだ
けが流れ、その電圧降下はＶｓ２（アースに対して負の
電圧）である。抵抗値はダミー抵抗Ｒｄ＞＞負荷抵抗Ｒ
Ｌである。なお、ダミー抵抗Ｒｄは、負荷抵抗ＲＬがオ
ープンになった場合、Ｃ１〜Ｃｎにチャージされた電荷
による負の高圧を放電させる機能を有している。 さら
に、ダミー抵抗を用いることにより高圧の出力電流を直
接検出しなくても高精度に出力電流をモニターできるよ
うにしている。図に示すように、電流検出抵抗Ｒｓ１と
電流検出抵抗Ｒｓ２の接続点はグランドにアースされて
いるので、上記電圧降下のＶｓ１とＶｓ２は極性が逆に
なっている。抵抗Ｒ１と抵抗Ｒ２を介して電圧降下Ｖｓ
１とＶｓ２を合成すると、Ｖｓ１＋（−Ｖｓ２）とな
る。電流検出抵抗Ｒｓ１と電流検出抵抗Ｒｓ２の抵抗値
は等しいので、Ｖｓ１＋（−Ｖｓ２）は電流検出抵抗Ｒ
ｓ１に流れる出力電流ＩＬの電圧降下に等しい電圧であ
る。集積回路Ｕ１のプラス側に印加されたこの電圧は集
積回路Ｕ１で増幅され、電流モニターとして出力され
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS An output current monitor circuit according to an embodiment of the present invention will be described below with reference to FIGS. It is to be noted that the components denoted by the same reference numerals as those in FIGS. 4 and 5 respectively represent the same elements, and the description thereof will be omitted. In FIG. 1, a current detection resistor Rs1 which is a first resistor and a second resistor Rs which is a second resistor.
2 is set to the same resistance value. The resistors R1 and R2 have the same resistance value and are sufficiently higher than the current detection resistors Rs1 and Rs2. The load resistor RL is applied with a negative high voltage, -HV, with respect to the ground. In addition, the current detection resistor Rs2 and the dummy resistor Rd connected in series also have −
HV is being applied. Therefore, the output current IL flowing through the load resistor RL and the dummy resistor Rd are connected to the current detection resistor Rs1.
A dummy current Id flows through the gate, and its voltage drop is Vs1.
(Positive voltage with respect to ground) . Further, only the dummy current Id flowing through the dummy resistor Rd flows through the current detection resistor Rs2, and the voltage drop thereof is Vs2 (negative voltage with respect to the ground). Resistance value is dummy resistance Rd >> load resistance R
It is L. The dummy resistor Rd has a function of discharging a negative high voltage due to the electric charges charged in C1 to Cn when the load resistor RL is opened . Furthermore
In addition, by using a dummy resistor, the high voltage output current is
You can monitor the output current with high accuracy without contact detection.
I am sorry. As shown in the figure, since the connection point between the current detection resistor Rs1 and the current detection resistor Rs2 is grounded to the ground, the polarities of Vs1 and Vs2 of the above voltage drop are opposite. Voltage drop Vs through the resistors R1 and R2
When 1 and Vs2 are combined, it becomes Vs1 + (-Vs2). Since the current detection resistors Rs1 and Rs2 have the same resistance value, Vs1 + (-Vs2) is equal to the current detection resistor Rs.
The voltage is equal to the voltage drop of the output current IL flowing through s1. This voltage applied to the plus side of the integrated circuit U1 is amplified by the integrated circuit U1 and output as a current monitor.
【０００９】図２は図１の本発明の一実施例である出力
電流モニター回路における出力電流ＩＬと電流モニター
の関係を示す電流モニター特性表である。図から明らか
なように、電流モニターの値と出力電流ＩＬはリニアな
関係にあり、良く一致している。FIG. 2 is a current monitor characteristic table showing the relationship between the output current IL and the current monitor in the output current monitor circuit according to the embodiment of the present invention shown in FIG. As is clear from the figure, the value of the current monitor and the output current IL have a linear relationship and are in good agreement.
【００１０】図３は本発明の出力電流モニター回路を過
電流保護回路に応用したものであり、その要部を示して
いる。なお、図１、図２、図４、図５と同一符号を付し
たものはそれぞれ同一の要素を示しており、説明を省略
する。集積回路Ｕ２の反転入力端子には基準電圧として
の基準電源Ｖｒｅｆが接続されており、非反転入力端子
には集積回路Ｕ１の出力電流ＩＬのモニター電圧が印加
される。非反転入力端子に印加される電圧が基準電源Ｖ
ｒｅｆの基準電圧を超えると、集積回路Ｕ２はハイを出
力し、その出力はダイオードＣＲ２を介してトランジス
タＱ２のベースに印加され、トランジスタＱ２はオンと
なり、トランジスタＱ１のベース電位を下げてトランジ
スタＱ１の動作を停止させる。FIG. 3 shows an application of the output current monitor circuit of the present invention to an overcurrent protection circuit, and shows the main part thereof. It is to be noted that components denoted by the same reference numerals as those in FIGS. 1, 2, 4, and 5 respectively denote the same elements, and description thereof will be omitted. The reference power supply Vref as a reference voltage is connected to the inverting input terminal of the integrated circuit U2, and the monitor voltage of the output current IL of the integrated circuit U1 is applied to the non-inverting input terminal. The voltage applied to the non-inverting input terminal is the reference power source V
When the reference voltage of ref is exceeded, the integrated circuit U2 outputs high, the output is applied to the base of the transistor Q2 via the diode CR2, the transistor Q2 is turned on, and the base potential of the transistor Q1 is lowered to lower the base potential of the transistor Q1. Stop the operation.
【００１１】[0011]
【発明の効果】以上説明したように本発明による出力電
流モニター回路は、ダミー抵抗に流れるダミー電流と前
記出力電流が共に流れる第１の抵抗と、前記ダミー電流
だけが流れる第２の抵抗を設け、第１の抵抗による電圧
降下と第２の抵抗による電圧降下から前記出力電流を求
めることにより出力電流をモニターするように構成され
ているので、ダミー電流による影響を受けることなく負
荷に流れる出力電流を正確にモニターすることができ
る。As described above, the output current monitor circuit according to the present invention is provided with the first resistor through which the dummy current flowing through the dummy resistor and the output current both flow, and the second resistor through which only the dummy current flows. Since the output current is monitored by obtaining the output current from the voltage drop due to the first resistance and the voltage drop due to the second resistance, the output current flowing through the load without being affected by the dummy current. Can be accurately monitored.
【図１】本発明の一実施例における出力電流モニター回
路の回路図である。FIG. 1 is a circuit diagram of an output current monitor circuit according to an embodiment of the present invention.
【図２】本発明の出力電流モニター回路における出力電
流と電流モニターの特性表である。FIG. 2 is a characteristic table of output current and current monitor in the output current monitor circuit of the present invention.
【図３】本発明の出力電流モニター回路を応用した応用
例の要部を示す回路図である。FIG. 3 is a circuit diagram showing a main part of an application example in which the output current monitor circuit of the present invention is applied.
【図４】従来例における出力電流モニター回路の回路図
である。FIG. 4 is a circuit diagram of an output current monitor circuit in a conventional example.
【図５】従来例における出力電流モニター回路における
出力電流と電流モニターの特性表である。FIG. 5 is a characteristic table of output currents and current monitors in an output current monitor circuit in a conventional example.
１ 制御部 Ｃ１〜Ｃｎ コンデンサ Ｃ１０１、Ｃ１０２ コンデンサ ＣＲ１〜ＣＲｎ ダイオード ＣＲ１００〜ＣＲ１０２ ダイオード Ｉｄ ダミー電流 ＩＬ 出力電流 Ｑ１、Ｑ２ トランジスタ Ｒ１〜Ｒ５ 抵抗 Ｒｄ ダミー抵抗 ＲＬ 負荷抵抗 Ｒｓ 電流検出抵抗 Ｒｓ１ 電流検出抵抗 Ｒｓ２ 電流検出抵抗 Ｔ１ トランス Ｕ１、Ｕ２ 集積回路 Ｖｒｅｆ 基準電源 1 control unit C1-Cn capacitors C101, C102 capacitors CR1-CRn diode CR100-CR102 diode Id dummy current IL output current Q1 and Q2 transistors R1 to R5 resistance Rd dummy resistor RL load resistance Rs current detection resistor Rs1 current detection resistor Rs2 Current detection resistor T1 transformer U1, U2 integrated circuits Vref reference power supply
Claims (2)
に直流高圧を発生する直流高圧電源がこの第１の出力端
子とアースとの間に接続された負荷に流す出力電流を、
モニターする出力電流モニター回路において、 第１の電流検出抵抗と第２の電流検出抵抗とダミー抵抗
とが直列に接続された第１の直列回路と、第１の抵抗と
第２抵抗とが直列に接続された第２の直列回路とを備
え、 前記第１の直列回路の一端である第１の電流検出抵抗の
端部を、前記第２の出力端子に接続し、前記第１の直列
回路の他端であるダミー抵抗の端部を、前記第１の出力
端子に接続し、かつ前記第１の電流検出抵抗と前記第２
の電流検出抵抗との接続点をアースに接続すると共に、
前記第２の直列回路の一端である第１の抵抗の端部を、
前記第２の出力端子に接続し、前記第２の直列回路の他
端である第２の抵抗の端部を、前記第１の直列回路の前
記第２の電流検出抵抗と前記ダミー抵抗との接続点に接
続することによって、 前記出力電流および前記ダミー抵抗に流れるダミー電流
を、前記第１の電流検出抵抗に流し、前記ダミー電流だ
けを前記第２の電流検出抵抗と前記ダミー抵抗とに流
し、 前記第１の電流検出抵抗の電圧によって前記第１の抵抗
に発生する電圧と、前記第２の電流検出抵抗の電圧によ
って前記第２の抵抗に発生する電圧とによって、前記第
１の抵抗と前記第２の抵抗との間に生ずる電圧を、前記
第１の抵抗と前記第２の抵抗との接続点から出力し、こ
の出力された電圧から 前記出力電流をモニターすること
を特徴とする出力電流モニター回路。1.Between the first output terminal and the second output terminal
The DC high voltage power supply that generates high DC voltage is
The output current that flows in the load connected between the child and ground is
In the output current monitor circuit to monitor, First current detection resistor, second current detection resistor, and dummy resistor
A first series circuit in which and are connected in series, and a first resistor
A second series circuit in which a second resistor is connected in series
e, Of the first current detection resistor, which is one end of the first series circuit,
The end is connected to the second output terminal and the first series is connected.
The end of the dummy resistor, which is the other end of the circuit, is connected to the first output.
The first current detection resistor and the second current detection resistor.
While connecting the connection point with the current detection resistor of to the ground,
An end of the first resistor, which is one end of the second series circuit,
Other than the second series circuit connected to the second output terminal.
The end of the second resistor, which is the end, is connected to the front of the first series circuit.
Note Connect to the connection point between the second current detection resistor and the dummy resistor.
By continuing, Dummy current flowing through the output current and the dummy resistor
Is passed through the first current detection resistor, and the dummy current
Flow through the second current detection resistor and the dummy resistor.
Then The first resistance is detected by the voltage of the first current detection resistance.
Of the voltage generated at the second current detection resistor and the voltage of the second current detection resistor.
The voltage generated in the second resistor,
The voltage generated between the first resistance and the second resistance is
Output from the connection point between the first resistor and the second resistor,
From the output voltage of Monitoring the output current
Output current monitor circuit characterized by.
第２の電流検出抵抗の抵抗値とを同じ値にし、かつ、前
記第１の抵抗の抵抗値と前記第２の抵抗の抵抗値とを同
じ値にしたことを特徴とする請求項１に記載の出力電流
モニター回路。 2. The resistance value of the first current detection resistor and the
The same value as the resistance value of the second current detection resistor, and
The resistance value of the first resistor is the same as the resistance value of the second resistor.
The output current according to claim 1, wherein the output current is the same value.
Monitor circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04037992A JP3418962B2 (en) | 1992-01-30 | 1992-01-30 | Output current monitor circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04037992A JP3418962B2 (en) | 1992-01-30 | 1992-01-30 | Output current monitor circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05209901A JPH05209901A (en) | 1993-08-20 |
| JP3418962B2 true JP3418962B2 (en) | 2003-06-23 |
Family
ID=12579023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04037992A Expired - Fee Related JP3418962B2 (en) | 1992-01-30 | 1992-01-30 | Output current monitor circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3418962B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7310464B2 (en) * | 2019-09-06 | 2023-07-19 | 株式会社リコー | Power supply and image forming device |
| JP2021113908A (en) * | 2020-01-20 | 2021-08-05 | 株式会社リコー | Power supply and image forming equipment |
-
1992
- 1992-01-30 JP JP04037992A patent/JP3418962B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05209901A (en) | 1993-08-20 |
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