JP3419861B2 - Phase trip circuit of current supply type inverter and signal shaping circuit thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase trip circuit of a current supply type inverter and its signal shaping circuit,
More specifically, the present invention relates to a phase trip circuit and a signal shaping circuit that control a trip operation that stops a switching operation in an inverter circuit.

[0002]

2. Description of the Related Art In a constant current supply type inverter using a conventional inverter circuit composed of self-extinguishing type switching elements, since the operating frequency is operated near the resonance point of the load, the inverter side of the inverter side It is necessary to control the phase of the high-frequency voltage signal and the high-frequency current signal supplied to the.

Therefore, a phase difference detection circuit for detecting a phase difference based on each feedback signal of the high frequency voltage signal and the high frequency current signal is provided, and the phase difference (phase) signal output from this phase difference detection circuit is used. , Judge whether the phase of the high frequency current signal is "lagging" or "leading" to the high frequency voltage signal, and "lag" and "lead" of that phase
VCO that sets the operating frequency of the high-frequency current signal according to
By adjusting the potential of the voltage signal supplied to the (voltage controlled oscillator), the operating frequency of the high frequency current signal is raised or lowered to control the high frequency current phase to be delayed or advanced. ing.
As a result, the phases of the operating frequencies of the high-frequency voltage signal and the high-frequency current signal are controlled so as to match each other near the resonance point of the load.

FIG. 12 shows a concrete example of phase control by this phase difference detection circuit. In FIG. 12, there is a comparator (COMP) to which a high frequency voltage feedback signal is input and a comparator to which a high frequency current feedback signal is input, and the high frequency is calculated from the difference between the pulse signals (a) and (b) output from each comparator. The signals (c) and (d) indicating whether the phase of the current signal is "leading" or "lagging" with respect to the high frequency voltage signal are output to the VCO shown in FIG. 13 to raise or lower the input potential Vi of the VCO. Let VC
The frequency setting signal f output from O is raised and lowered.

[0005]

However, in such a conventional constant current supply type inverter, the phase control of the high frequency voltage signal and the high frequency current signal supplied to the load side by the inverter circuit is performed by the high frequency current signal. The phase delay and lead of the operating frequency of the high frequency current signal are adjusted based on the phase difference signal output from the phase difference detection circuit that detects the phase difference with respect to the high frequency voltage signal of , The operating frequency of the high frequency current signal is maintained within a predetermined allowable range, but in the case where an abnormality (short circuit, open) occurs on the load side and the phase of the feedback signal of the high frequency current signal is significantly deviated. Since no measures were taken, there were the following problems.

That is, even if a phase shift of a high frequency current feedback signal occurs due to a sudden load abnormality, it cannot immediately respond, and an overvoltage such as a spike voltage is transiently applied to a switching element forming an inverter circuit,
There is a problem that the switching element is likely to be destroyed.

In order to avoid such a situation, it is necessary to monitor the phase shift of the high frequency current feedback signal, detect a load abnormality as soon as possible, and stop the switching operation.

Further, in the case of the high frequency voltage feedback signal input to the phase difference detection circuit, since it is the resonance load voltage, it has a clean sine waveform as shown in FIG. However, in the case of the high frequency current feedback signal, since it is a feedback signal by the high frequency current signal generated by turning on / off the switching element in the inverter circuit, there is a deviation between the operating frequency and the load resonance frequency,
Alternatively, when the current overlapping angle width is not appropriate, the trapezoidal wave as shown in FIG.
The vibration waveform as shown in FIG. When the rising portion of the high frequency current feedback signal vibrates in this manner, the phase of the current feedback signal is advanced with respect to the high frequency voltage feedback signal, as shown in FIGS. Nevertheless, due to the vibration of the high-frequency current feedback signal, the pulse width and the phase delay are determined as the phase advance, and it is determined that the phase is delayed.

Therefore, the VCO is controlled so as to raise the operating frequency of the high frequency current signal, and the operating frequency becomes too high, causing hunting or runaway, which causes the switching element to be destroyed.

[Object] An object of the present invention is to provide a phase trip circuit and a signal shaping circuit that detect a phase shift of a high frequency current feedback signal in a current supply type inverter and control a trip operation.

[0011]

The invention according to claim 1 is
Output from the phase difference detection circuit that detects the phase difference between the high frequency voltage signal and the high frequency current signal based on each feedback signal of the high frequency voltage signal and the high frequency current signal supplied to the load side from the inverter circuit composed of switching elements A phase trip circuit for controlling a trip operation for stopping a switching operation in the inverter circuit by a phase difference detection signal, wherein a phase delay of the high frequency voltage signal or the high frequency current signal based on the phase difference detection signal or A monitor signal generation circuit that generates a phase shift monitor signal that monitors the advance, and a signal width of the phase difference detection signal that is monitored based on the phase shift monitor signal that is generated by this monitor signal generation circuit. When the lead is detected, the switching operation in the inverter circuit is The generates a trip operation control signal to perform a trip operation to stop, is characterized by and a trip signal generating circuit for outputting to said inverter circuit.

According to a second aspect of the invention, there is provided a switching element.
Is supplied to the load side from the inverter circuit
High frequency voltage signal and high frequency current signal
The high-frequency voltage signal and the high-frequency current signal
A signal shaping circuit for shaping a feedback signal of the high frequency current signal input to a phase difference detection circuit for detecting the phase difference of the signal, the latch being for latching and outputting the potential of the feedback signal of the high frequency current signal for a predetermined time. Circuit, the feedback signal output from the latch circuit, and the high frequency power input without passing through the latch circuit.
And a calculation circuit that outputs the calculation result of the flow signal and the feedback signal to the phase difference detection circuit as a detection signal for detecting the phase difference of the high frequency current signal.

[0013]

The operation of the means of the present invention is as follows.

According to the first aspect of the invention, the high frequency voltage signal and the high frequency current are supplied based on the feedback signals of the high frequency voltage signal and the high frequency current signal supplied to the load side from the inverter circuit including the switching element. A phase trip circuit for controlling a trip operation for stopping a switching operation in the inverter circuit by a phase difference detection signal output from a phase difference detection circuit for detecting a phase difference between signals, wherein the phase difference is detected by a monitoring signal generation circuit. A phase shift monitoring signal for monitoring the delay or advance of the phase of the high frequency voltage signal or the high frequency current signal is generated based on the detection signal, and the phase difference detection circuit is generated based on the phase shift monitoring signal generated by the monitoring signal generation circuit. The signal width of the phase difference detection signal output from When it is or proceeds is detected, a trip operation control signal to perform a trip operation for stopping the switching operation of the inverter circuit is generated and outputted to the gate circuit.

Therefore, the phase shift of the high-frequency current phase signal or the high-frequency voltage phase signal can be detected promptly, and the phase trip operation for stopping the output of the high-frequency output current and the high-frequency output voltage can be performed, and the inverter circuit is constructed. It is possible to prevent transient application of an overvoltage such as a spike voltage to the switching element, and it is possible to prevent the switching element from being destroyed.

As a result, the reliability of the current supply type inverter can be improved.

According to the second aspect of the invention, the switch
From the inverter circuit composed of
High-frequency voltage signal and high-frequency current signal supplied
Based on the feedback signal, its high frequency voltage signal and high frequency
A signal shaping circuit that shapes a feedback signal of the high-frequency current signal input to a phase difference detection circuit that detects a phase difference of current signals, wherein a potential of the high-frequency current signal feedback signal is latched by a latch circuit for a predetermined time. Output of the feedback signal output from the latch circuit by the arithmetic circuit and the calculation result of the feedback signal of the high frequency current signal input without passing through the latch circuit to detect the phase difference of the high frequency current signal. Is output to the phase difference detection circuit.

Therefore, when there is a trough in the current phase signal, it is possible to avoid the situation in which the trough and the trough are detected as separate current phase signals, and the phase difference of the high frequency current feedback signal is accurately detected. In addition, the phase control of the operating frequency of the switching element and the malfunction of the phase trip operation can be prevented.

As a result, the phase control of the operating frequency and the phase trip operation in the current supply type inverter can be reliably performed, and the reliability of the current supply type inverter can be further improved.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1 to 11 are views showing an embodiment of a current supply type inverter to which the phase trip circuit and the signal shaping circuit of the invention described in claims 1 and 2 are applied.

First, the structure will be described.

FIG. 1 is a circuit configuration diagram of a current supply type inverter.

In FIG. 1, a current supply type inverter 1 includes a three-phase full-wave phase control rectifier circuit 2, a freewheel diode FD, DC reactors LD1 and LD2, an inverter circuit 3, gate circuits GA to GD, and a high frequency transformer 4. ,
The heating coil 5, a current detection circuit 6, a high frequency current detection transformer CT, a high frequency voltage detection transformer PT, a phase difference detection control circuit 7 and a phase trip circuit 8.

The three-phase full-wave phase control rectifier circuit 2 has three
The three-phase AC voltage input from the phase AC power supply is rectified and a DC voltage is output, and the free wheel diode FD discharges the stored energy during the trip operation. The DC reactors LD1 and LD2 smooth the pulsating flow component contained in the DC voltage output from the three-phase full-wave phase control rectifier circuit 2.

The gate circuits GA to GD are power MOS-
An inverter circuit 3 configured by bridge-connecting switching elements S1 to S4 by FETs and a gate control signal for controlling the switching operation of each switching element S1 to S4 are output to the gate electrodes of each switching element S1 to S4. .

The high frequency transformer 4 forms an LC vibration circuit together with the output capacitor C to generate an alternating magnetic flux in the heating coil 5 by the high frequency output voltage VINV output from the inverter circuit 3, and the current detection circuit 6 is a direct current. Reactor L
DC current IDC flowing through D1 and LD2 is detected.

The high frequency voltage detecting transformer PT includes a high frequency current detecting transformer CT which detects the high frequency output current IINV output from the inverter circuit 3, and a high frequency output voltage VINV generated on the load side by the high frequency output current IINV. To detect.

The phase difference detection control circuit 7 includes a high frequency voltage feedback signal of the high frequency output voltage VINV and a high frequency current feedback signal of the high frequency output current IINV detected by the high frequency voltage detecting transformer PT and the high frequency current detecting transformer CT. By detecting the phase difference (delay or lead) with the above, the operating frequencies of the switching elements S1 to S4 are controlled.

The phase trip circuit 8 detects the phase shift of the high frequency output current IINV with respect to the high frequency output voltage VINV based on the phase difference signal output from the phase difference detection control circuit 7, and controls the trip operation of the inverter circuit 3. Yes * The phase trip signal is output to the gate circuits GA to GD.

In this embodiment, the circuit connecting the switching element S1 is arm A and the circuit connecting the switching element S2 is arm B for each bridge connection circuit to which the switching elements S1 to S4 of the inverter circuit 3 are connected. , An arm C connecting the switching element S3 and a circuit connecting the switching element S4.

In the inverter circuit 3, each switching operation is controlled by the gate circuits GA to GD by the combination of the arms A and D and the arms B and C, and the switching operations are alternately performed at a predetermined high frequency (for example, 200 kHz). Then, a constant high frequency output current IINV is generated and supplied to the heating coil 5 serving as a load via the high frequency transformer 4.

Here, the circuit configuration of the phase difference detection control circuit 7 of FIG. 1 is shown in FIG.

In FIG. 2, the phase difference detection control circuit 7
Is a comparator 11 for shaping a high frequency current feedback signal input from the high frequency current detecting transformer CT and outputting a current phase signal, and a high frequency voltage detecting transformer P.
A comparator 12 that shapes the high frequency voltage feedback signal input from T and outputs a voltage phase signal, and 90 that inputs the high frequency voltage feedback signal after integrating them.
° The extraction width of the current phase signal input from the comparator 11 is set at the timing of the comparator 13 that outputs the determination signal for determining the phase difference based on the delay signal and the clock signal input from the VCO 24, and the extraction width is set. A signal shaping circuit 14 that shapes and outputs a current phase signal with a signal, an inverter 15 that inverts and outputs a high-frequency current feedback shaping signal that is input from the signal shaping circuit 14, an inverted output that is input from the inverter 15, and a comparator. An EXOR gate 16 that outputs a logical sum of the discrimination signal that is input from 13 and an EXOR that outputs a logical sum of the shaping signal that is input from the signal shaping circuit 14 and the square wave signal that is input from the comparator 12.
The gate 17, the EXOR gate 18 for outputting the logical sum of the shaping signal input from the signal shaping circuit 14 and the discrimination signal input from the comparator 13, and the phase monitoring signal input from the comparator 13 are inverted. An inverter 19 for outputting, and a phase difference signal by a logical product of the logical sum input from the OR gate 16, the logical sum input from the EXOR gate 17, and the inverted output of the phase monitoring signal input from the inverter 19 are output. AND gate 20, logical OR input from OR gate 17, logical OR input from OR gate 18, and inverter 1
An AND gate 21 that outputs a phase difference signal by logical product of the inverted output of the phase monitoring signal input from 9 and transistors TR1 and TR2 and resistors R1 to R3 are provided. Accordingly, the charging circuit 22 that charges the capacitor C and the transistor TR3
And an AND gate 21 composed of resistors R4 and R5.
Discharge circuit 23 that discharges the capacitor C in accordance with the logical product output of the above, and each switching element S1 to S of the inverter circuit 3 (not shown) according to the potential change due to charging and discharging of the capacitor C.
VC for outputting a clock signal for setting the operating frequency of 4
It is composed of O24.

The phase difference signals output from the AND gate 20 and the AND gate 21 are also output to the phase trip circuit 8.

FIG. 3 is a circuit diagram of the phase trip circuit 8.

The phase trip circuit 8 latches the input signal a by the phase difference signal input from the AND gates 20 and 21 in the phase difference detection control circuit 7 for a period of time constant set by the capacitor c1 and the resistor r1. Monostable multivibrator 3 which outputs the phase shift monitoring signal b
1, an inverter 33 that inverts an input signal a input through an integrating circuit 32 including a resistor r2 and a capacitor c2 and outputs a phase difference inverted signal c, and a phase shift monitoring input from a monostable multivibrator 31. A D flip-flop circuit 34 that monitors the signal width of the phase difference inversion signal c input from the inverter 33 based on the signal b and outputs a * phase trip signal d (where * indicates a negative logic signal). It consists of and.

Further, FIG. 4 is a circuit configuration diagram of the signal shaping circuit 14.

The signal shaping circuit 14 sets the fetch width of the current phase signal (above) b inputted from the comparator 11 at the timing of the clock signal a inputted from the VCO 24, and the current phase signal b at the fetch width. A monostable multivibrator 41 which latches the signal and outputs a latch signal c, and a shaped signal d is output by the logical sum of the latch signal c input from the monostable multivibrator 41 and the current phase signal (square wave signal) b. It is composed of an OR gate 42.

Next, the operation of this embodiment will be described.

First, the operation of the current supply type inverter 1 of FIG. 1 will be described.

In FIG. 1, the three-phase AC voltage input from the three-phase AC power supply (not shown) is the three-phase full-wave phase control rectifier circuit 2.
When rectified by and output as a DC voltage, the pulsating current component included in the output DC current is smoothed by the DC reactors LD1 and LD2 and supplied to the inverter circuit 3.

In the inverter circuit 3, the gate circuits GA ...
The switching operation of the switching elements S1 to S4 of the arms A to D is performed by the gate control signal input from the GD to the gate electrodes of the switching elements S1 to S4. B
The switching operation is controlled by each combination of the switching elements S2 and S3, and the constant high frequency output current IINV is supplied to the heating coil 5.

Further, in the phase difference detection control circuit 7 of FIG.
When the high frequency current feedback signal of the high frequency output current IINV and the high frequency voltage feedback signal of the high frequency output voltage VINV detected by the high frequency current detecting transformer CT and the high frequency voltage detecting transformer PT are input to the comparators 11 and 12, As shown in FIG. 5, (c) and (a) in FIG.
The current phase signal and the voltage phase signal shown in are generated.

Next, in the discrimination section set by the discrimination signal shown in FIG. 7B generated by the comparator 13, in the OR gate 16, the inversion current taken in by the signal shaping circuit 14 and inverted by the inverter 15 is inverted. The phase signal is output as shown in FIG. In the same determination section, the OR gate 18 outputs the current phase signal captured by the signal shaping circuit 14 as shown in FIG. Further, the OR gate 17 outputs a logical sum output of the current phase signal input from the comparator 11 and the voltage phase signal input from the comparator 12, as shown in FIG.

Next, in the EXOR gate 16, the inverter 15 outputs the discrimination signal in the discrimination section set by the discrimination signal shown in FIG. The logical sum output with the inverted signal which is inverted by is output as shown in FIG.

Similarly, the EXOR gate 18 outputs a logical sum output of the discrimination signal and the shaping signal as shown in FIG.

The EXOR gate 17 outputs a logical sum output of the shaping signal and the voltage phase signal input from the comparator 12 as shown in FIG.

In FIG. 5, the discrimination section shown in FIG.
The phase of the current phase signal shown by (c) in the figure is (a) in the figure.
The case where the phase is delayed with respect to the phase of the voltage phase signal shown by is shown, and as shown by (g) in the figure, only the phase difference signal showing the delay is output. This phase difference signal
When output to the charging circuit 22 shown in FIG. 2, the capacitor C is charged, the input potential of the VCO 24 is increased, and the frequency of the clock signal output from the VCO 24 is increased.

As a result, the operating frequencies of the switching elements S1 to S4 are increased and controlled so that the phase of the high frequency output current IINV advances, and the phase delay of the high frequency output current IINV with respect to the phase of the high frequency output voltage VINV is improved. .

Further, as shown in FIG. 6, as shown in FIG.
When the phase of the current phase signal shown in FIG. 5 (c) leads the phase of the voltage phase signal shown in FIG. 5 (a) in the discrimination section shown in FIG. 5 (d)-(f). As shown in FIG. 2B, the outputs from EXOR gates 16 to 18 in FIG. 2 are output. Therefore, as shown in FIG.
As shown in FIG. 7H, only the phase difference signal indicating the phase lead output from the AND gate 21 is output.

When this phase difference signal is output to the discharge circuit 23 shown in FIG. 2, the capacitor C is discharged and V
The input potential of the CO 24 is lowered, and the frequency of the clock signal output from the VCO 24 is lowered.

As a result, the operating frequencies of the switching elements S1 to S4 are lowered and controlled so that the phase of the high frequency output current IINV is delayed, and the phase advance of the high frequency output current IINV with respect to the phase of the high frequency output voltage VINV is improved. .

Therefore, AND gate 20 and AND
The phase difference signals output from the gate 21 are controlled so that the operating frequencies of the switching elements S1 to S4 are maintained within a predetermined range, and the phase of the high frequency output current IINV with respect to the phase of the high frequency output voltage VINV falls within the predetermined range. Controlled.

Further, in the present embodiment, the phase difference signal generated in the phase difference detection control circuit 7 is also output to the phase trip circuit 8 shown in FIG. 3, and the phase trip circuit 8 detects the phase difference. Large deviations are monitored.

That is, in the phase trip circuit 8,
Based on the phase difference signal or the phase difference signal output from the phase difference detection control circuit 7, the high frequency output current IIN
The phase shift of V with respect to the high frequency output voltage VINV is detected to control the trip operation of the inverter circuit 3 *
The phase trip signal is output to the gate circuits GA to GD.

The operation of the phase trip circuit 8 will be described with reference to the timing charts of the signals of the respective parts shown in FIGS.

In the phase trip circuit 8 of FIG. 3 described above, the phase difference signal output from the phase difference detection control circuit 7 or the input signal a shown in FIG. 7A by the phase difference signal is the capacitor of the monostable multivibrator 31. c1
The signal is latched for a time constant set by the resistor r1 and the resistor r1, and the phase shift monitor signal b is output from the Q terminal as shown in FIG. 7B. Further, the input signal a is the integration circuit 32.
And inverted by the inverter 33 and output as the phase difference inversion signal c shown in FIG.

Next, in the D flip-flop circuit 34, the signal width of the phase difference inversion signal c input from the inverter 33 is based on the monitoring width set by the phase shift monitoring signal b input from the monostable multivibrator 31. It is monitored, that is, the phase shift is monitored and the * phase trip signal d is output.

In FIG. 7, when the signal width of the phase difference signal a is shorter than the monitoring width set by the phase shift monitoring signal b, that is, the high frequency current feedback signal detected by the phase difference detection control circuit 7 described above. When the phase shift of is within the allowable range with respect to the phase of the high-frequency voltage feedback signal, the * phase trip signal d is held as "1" as shown in FIG. 7 (d). As a result, the * phase trip signal d is output and the gate circuit G in FIG.
Normal operation of A to GD is maintained.

Further, as shown in FIG. 8A, the signal width of the phase difference signal a is equal to the phase shift monitor signal b shown in FIG. 8B.
When the phase difference of the high frequency current feedback signal detected by the phase difference detection control circuit 7 is outside the permissible range with respect to the phase of the high frequency voltage feedback signal, , * The phase trip signal d is, as shown in FIG.
It is changed from "1" to "0". As a result, the * phase trip signal d is output.
~ Phase trip operation to stop the operation of GD is performed, and high frequency output current IINV and high frequency output voltage VINV
Output is stopped.

Here, specific examples of the operation of the signal waveform when an abnormality occurs in the load are shown in FIGS. 9 and 10.

FIG. 9 shows a specific example of the trip operation relationship among the high frequency current feedback signal when the load is released, the high frequency voltage feedback signal, and the * phase trip signal. In this figure, when the phase shift of the high frequency current feedback signal becomes large with respect to the phase of the high frequency voltage feedback signal due to the operation of the phase trip circuit 8 of the present embodiment, the * phase trip signal immediately changes from "1" to " It changes to 0 "and the high frequency output current I
It shows how the output of INV and the high frequency output voltage VINV is stopped.

FIG. 10 shows a specific example of the trip operation relationship between the high frequency current feedback signal and the high frequency voltage feedback signal when the load is short-circuited. Similarly, by the operation of the phase trip circuit 8, when the phase shift of the high frequency current feedback signal becomes larger than the phase of the high frequency voltage feedback signal, the * phase trip signal changes from "1" to "0", High frequency output current IIN
The figure shows that the output of V and the high frequency output voltage VINV is stopped.

Therefore, in the current supply type inverter 1 according to the present embodiment, the phase shift of the current phase signal detected by the phase difference detection control circuit 7 with respect to the voltage phase signal is promptly detected by the phase trip circuit 8 and gated. The operation of the circuits GA to GD is stopped, and the high frequency output current IINV
Also, since the phase trip operation in which the output of the high frequency output voltage VINV is stopped is performed, the switching elements S1 to
It is possible to prevent transient application of an overvoltage such as a spike voltage to S4, and to switch elements S1 to S4.
Can be prevented from being destroyed.

As a result, the reliability of the current supply type inverter can be improved.

Further, in the phase difference detection control circuit 7 of the present embodiment, the current phase signal output from the comparator 11 is shaped by the signal shaping circuit 14, and the signal shaping circuit 14 performs the shaping. The waveform shaping process will be described with reference to the timing chart of the signals of the respective parts shown in FIG.

In the signal shaping circuit 14, from the VCO 24 to the input terminal R of the monostable multivibrator 41, as shown in FIG.
When the clock signal a shown in (a) is input, the fetch width of the current phase signal () b shown in (b) in the figure, which is input from the comparator 11 to the input terminal A at the clock timing, is set. The current phase signal b is latched by the fetch width, and the latch signal c shown in FIG.

Next, when the latch signal c and the current phase signal b that does not pass through the monostable multivibrator 41 are input to the OR gate 42, the logical sum of the latch signal c and the current phase signal b is shown in FIG. It is output as the shaped signal d shown in d).

Therefore, as shown in FIG. 11B and the above-mentioned conventional FIG. 14B, when the current phase signal b output from the comparator 11 has a valley, the valley before and after the valley is separated. It is possible to avoid the situation of detecting as the current phase signal b, to accurately detect the phase difference of the high frequency current feedback signal in the phase difference detection control circuit 7, and to perform the phase control of the operating frequency and the phase trip. It is possible to prevent malfunction of operation.

As a result, the switching elements S1 to S1 in the phase difference detection control circuit 7 of the current supply type inverter 1 are
The phase control of the operating frequency of S4 and the phase trip operation in the phase trip circuit 8 can be reliably performed, and the reliability of the current supply inverter 1 can be further improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the circuit configurations of the phase trip circuit 8 and the signal shaping circuit 14 may be different circuit configurations.

[0073]

According to the first aspect of the present invention, the phase trip operation for quickly detecting the phase shift of the high frequency current phase signal or the high frequency voltage phase signal and stopping the output of the high frequency output current and the high frequency output voltage is performed. It is possible to prevent the transient application of an overvoltage such as a spike voltage to the switching element that constitutes the inverter circuit, and it is possible to prevent the switching element from being destroyed.

As a result, the reliability of the current supply type inverter can be improved.

According to the second aspect of the present invention, when the current phase signal has vibration, it is possible to avoid the situation that the vibration is detected as separate current phase signals.
It is possible to accurately detect the phase of the high frequency current feedback signal, and to prevent erroneous operation of the phase control of the operating frequency of the switching element and the phase trip operation.

As a result, the phase control of the operating frequency and the phase trip operation in the current supply type inverter can be reliably performed, and the reliability of the current supply type inverter can be further improved.

[Brief description of drawings]

FIG. 1 is an overall circuit configuration diagram of a current supply type inverter to which the present invention is applied.

FIG. 2 is a circuit configuration diagram of a phase difference detection control circuit in FIG.

FIG. 3 is a circuit configuration diagram of a phase trip circuit in FIG.

FIG. 4 is a circuit configuration diagram of a signal shaping circuit in FIG.

5 is a signal waveform diagram for explaining the operation of the phase difference detection control circuit of FIG. 2 when the current phase is delayed.

6 is a signal waveform diagram for explaining the operation of the phase difference detection control circuit of FIG. 2 when the current phase advances.

FIG. 7 is a signal waveform diagram for explaining the operation of the phase trip circuit of FIG.

8 is a signal waveform diagram for explaining an operation when a phase shift occurs in the phase trip circuit of FIG.

FIG. 9 is a diagram showing specific examples of a high-frequency current feedback signal, a high-frequency voltage feedback signal, and each waveform when a phase trip operation occurs when the load is released.

FIG. 10 is a diagram showing a specific example of each waveform of a high frequency current feedback signal and a high frequency voltage feedback signal when a phase trip operation occurs at the time of load short circuit.

FIG. 11 is a signal waveform diagram for explaining the operation of the signal shaping circuit of FIG.

FIG. 12 is a diagram showing a relationship between a circuit configuration and a signal waveform for explaining an operation in a conventional phase difference detection circuit.

13 is a diagram showing the relationship between the circuit configuration of the VCO circuit controlled by the phase difference signal output from the phase difference detection circuit of FIG. 12 and the signal waveform of the related art.

FIG. 14 is a diagram showing signal waveforms for explaining a conventional process of detecting a high-frequency current feedback signal.

[Explanation of symbols]

1 Current supply type inverter 2 3 phase full wave phase control rectifier circuit 3 inverter circuit 4 high frequency transformer 5 heating coils 6 DC current detection circuit 7 Phase difference detection control circuit 8 phase trip circuit 11-13 Comparator 14 Signal shaping circuit 15 inverter 16-18 EXOR gate 19 Inverter 20, 21 AND gate 22 Charging circuit 23 Discharge circuit 24 VCO 31 Monostable Multivibrator 32 integrating circuit 33 inverter 34 D flip-flop circuit 41 Monostable multivibrator 42 OR gate

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-5-103478 (JP, A) JP-A-5-64437 (JP, A) JP-A-3-86078 (JP, A) JP-A-59- 53020 (JP, A) JP-A-2-187278 (JP, A) JP-A-62-92725 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H02M 7/48 H02H 3 / 38

Claims (2)

(57) [Claims] 1. A unit for detecting a phase difference between a high-frequency voltage signal and a high-frequency current signal, based on feedback signals of the high-frequency voltage signal and the high-frequency current signal supplied from an inverter circuit composed of a switching element to a load side. A phase trip circuit for controlling a trip operation for stopping a switching operation in the inverter circuit by a phase difference detection signal output from a phase difference detection circuit, the high frequency voltage signal or the high frequency current signal based on the phase difference detection signal. Of the phase difference detection signal based on the phase deviation monitoring signal generated by the monitoring signal generation circuit and the phase deviation monitoring signal generated by the monitoring signal generation circuit. ,
And a trip signal generation circuit that generates a trip operation control signal that causes a trip operation to stop the switching operation in the inverter circuit when the phase delay or advance is detected, and outputs the trip operation control signal to the inverter circuit. Current supply type inverter phase trip circuit. 2. An inverter composed of a switching element.
High frequency voltage signal and high
Based on each feedback signal of the frequency current signal,
A signal shaping circuit for shaping a feedback signal of the high frequency current signal input to a phase difference detection circuit for detecting a phase difference between the high frequency voltage signal and the high frequency current signal , wherein a potential of the feedback signal of the high frequency current signal is set for a predetermined time. A latch circuit for latching and outputting, and a feedback signal output from this latch circuit,
The high-frequency current signal input without passing through this latch circuit
The phase calculation result of the issue feedback signal as a detection signal for detecting a phase difference between the high-frequency current signal
A signal shaping circuit for a current supply type inverter, comprising: an arithmetic circuit for outputting to a difference detection circuit.