JP3419902B2 - Method for manufacturing power semiconductor device - Google Patents

Description

Detailed Description of the Invention

The present invention relates to a method of manufacturing a power semiconductor device including a power semiconductor element such as an IGBT and a GTO.

[0002]

2. Description of the Related Art In recent years, an integrated circuit (IC) formed by integrating a large number of transistors, resistors and the like so as to achieve an electric circuit and forming them on one chip has been widely used in important parts of computers and communication equipment. ing. IC like this
Among them, a device including a power semiconductor element is called a power IC.

Since the power semiconductor element is required to have a large current carrying capacity, its area is larger than that of other semiconductor elements. For this reason, in the case of the conventional power semiconductor device, the repair method has been mainly the method of manually removing the defective portion or the insulating coating.

However, it is expected that as the power semiconductor elements become finer in the future, it will become difficult to carry out repair by hand and the efficiency of repair work will deteriorate. By the way, in an exposure process when a power semiconductor device, which is a large-area semiconductor device, is formed on a single wafer, an exposure apparatus that collectively exposes the entire surface of a wafer at a projection reduction ratio of 1: 1 (hereinafter referred to as 1: 1). The whole surface exposure device) is used.

The minimum size that can be exposed by the one-to-one whole surface exposure apparatus is about 5 μm, and the alignment margin is about 1 μm. This degree of accuracy was sufficient to manufacture conventional power semiconductor device.

However, in recent years, there is a strong demand for improving the functions of power semiconductor devices, and it has become necessary to form fine power semiconductor elements. For this reason, the exposure accuracy tends to become strict, and specifically, the exposure accuracy with a minimum exposure dimension of 1.0 μm and an alignment margin of about 0.5 μm is required.

In order to meet such a requirement, it is preferable to use a reduction projection type exposure apparatus (hereinafter referred to as a stepper exposure apparatus) having a projection reduction ratio of 5: 1 rather than a one-to-one whole surface exposure apparatus.

The maximum size that can be exposed with one shot by the stepper exposure apparatus is about 15 mm × 15 mm. Therefore, if one element is a power semiconductor element having a larger size, it is impossible to expose all the element regions on the wafer in one shot. Need to do. Therefore, in the case of the stepper exposure apparatus, although the exposure accuracy is high, there is a problem that the work efficiency is significantly reduced.

[0009]

As described above, in the conventional power semiconductor device, the area thereof is relatively large, so that repair by hand is the mainstream. However, as miniaturization of power semiconductor elements progresses in the future, it is expected that manual repair will become difficult, and the repair work efficiency will deteriorate.

Further, the conventional exposure process of the power semiconductor device is usually carried out by using a one-to-one whole surface exposure device. However, as the power semiconductor element is miniaturized, sufficient exposure accuracy can be obtained. Therefore, it is necessary to use a stepper exposure device. However, since the area that can be exposed by one shot of the stepper exposure apparatus is small, it is necessary to perform a plurality of shots in order to expose all the elements on the wafer, which causes a problem that work efficiency is significantly reduced.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a power supply capable of preventing a reduction in the exposure work efficiency even if the power semiconductor element is miniaturized.
An object of the present invention is to provide a method for manufacturing a semiconductor device for use.

[0012]

[0013]

[0014]

A method of manufacturing a power semiconductor device according to the present invention (claim 1 ) is directed to a power semiconductor element comprising a power semiconductor element region having a fine portion and a junction termination region.
In a method of manufacturing a power semiconductor device including a child chip, a resist pattern used for forming the fine portion is formed by step exposure, and a resist pattern used for forming the junction termination region is formed by one-to-one whole surface exposure. Is characterized by.

Here, the fine portion means that the size of the resist pattern used for forming the fine portion is a size which is difficult or impossible in the one-to-one whole surface exposure. Here, the step exposure is a projection reduction ratio, for example, 5: 1.
Exposure of a part of the wafer. Where one to one
The entire surface exposure is to collectively expose the entire surface of the wafer at a projection reduction ratio of 1: 1.

[0016]

[0017]

[0018]

[0019]

[0020]

[0021]

According to the present invention (Claim 1) , only the resist pattern used for forming the fine portion is formed by step exposure. ) It becomes possible to form a resist pattern.

[0022]

Embodiments will be described below with reference to the drawings. 1 is a schematic diagram showing a schematic configuration of a repair system for a power semiconductor device according to a first embodiment of the present invention.
This repair system is an example using a stepper exposure apparatus.

In the figure, 31 indicates a wafer, and a plurality of power semiconductor element chips 32 are formed on this wafer 31. This power semiconductor element chip 32 is a portion corresponding to one shot in a normal lithography process.

The power semiconductor device chip 32 is divided into a plurality of cell blocks 33 having the same pattern.
The cell block 33 is usually composed of 5 to 6 cell units. Further, in the figure, 34 indicates a cell block having a defective portion (defective cell block).

The wafer 31 is placed on a wafer stage (not shown) which constitutes a stepper system, and the wafer stage allows the wafer 31 to be moved stepwise in the X and Y directions.

An optical system of a stepper system is provided above the wafer 31. In the figure, reference numeral 35 denotes a light source thereof. The light 36 emitted from the light source 35 is
After focusing with a condenser lens (not shown), the mask pattern 3
7 and is irradiated onto the cell block 33 via the reduction projection lens 38. In this way, the fine pattern of the mask pattern 37 is exposed on the cell block 33.

The case where a turn-off thyristor with an insulated gate is used as a power semiconductor element will be specifically described below. 2 and 3 are process sectional views showing a repair method according to an embodiment of the present invention, FIG. 2 is a process sectional view showing a repair method for a normal cell block, and FIG. 3 is a repair method for a defective cell block. FIG.

FIG. 2A shows an element structure at a stage where the control electrode 11 and the cathode electrode 13 which are the first-layer main electrodes are formed by a known method. The device structure is as follows.

In FIG. 1, reference numeral 1 denotes a high resistance n-type base layer, and a low resistance p-type emitter layer 5 is formed on the back surface of the n-type base layer 1. A p-type base layer 2 is selectively formed on the surface of the n-type base layer 1, and an n-type emitter layer 3 and a high-concentration p-type diffusion layer 12 are selectively formed on the surface of the p-type base layer 2. Is formed in.

A gate electrode 8 is provided on the surface of the p-type base layer 2 sandwiched by the n-type base layer 1 and the n-type emitter layer 3 with a gate insulating film 7 interposed therebetween. Further, the n-type emitter layer 3 is provided with a cathode electrode 13, and the p-type diffusion layer 12 is provided with a control electrode 11. The gate electrode 8 and the cathode electrode 13 are insulated and separated by the insulating film 10.

At the stage when such an element structure is formed,
In order to determine a defect, for example, a short circuit between the gate electrode 8 and the cathode electrode 13, between the control electrode 11 and the cathode electrode 13, and between the gate electrode 8 and the control electrode 11 is measured. Instead of this short-circuit measurement, a defect determination may be made based on variations in turn-off ability.

Here, the unit for determining the defect may be a cell unit or a cell block. This is performed for all the cell blocks 34 in the power semiconductor element chip 32 to create mapping data of defective portions regarding the cell blocks as shown in FIG. Such mapping data is also created for the remaining power semiconductor element chips 32.

Next, as shown in FIG. 2B, a negative type insulating film 14 (eg, a negative type insulating film 14 functioning as a negative type resist) is formed on the entire surface.
After forming the polyimide film), the negative insulating film 14 is irradiated with light 36a as usual through the mask pattern 37a. That is, the portion of the insulating film 14 located on the control electrode 11 is selectively irradiated with the light 36a to be exposed.

This normal exposure is carried out by the system shown in FIG. 1 for each power semiconductor element chip 32 sequentially in one shot. Therefore, the normal cell block 3
Both the power semiconductor element chip 32 having No. 3 and the power semiconductor element chip 32 having the defective cell block 34 are subjected to the above exposure process.

After this, each power semiconductor element chip 32
Undergoes the following manufacturing process. That is, the repair system of FIG. 1 is programmed using the mapping data, and only the defective cell block 34 is sequentially and selectively exposed by using the programmed repair system as shown in FIG. 3A. . Selective exposure for such repair is performed for each power semiconductor element chip 3
Repeat for 2 sequentially.

Next, as shown in FIGS. 2C and 3B, the negative insulating film 14 is developed. That is, the negative insulating film 14 of the normal cell block is removed at the portions located on the gate electrode 8 and the cathode electrode 13, and the negative insulating film 14 of the defective cell block 34 is not patterned and is left as it is. .

Next, as shown in FIGS. 2D and 3C, the cathode electrode layer 15 is formed on the entire surface. At this time,
Since the negative insulating film 14 of the defective cell block 34 is not patterned as described above, only the cathode electrode 13 of the first layer of the normal cell block is in contact with the cathode electrode layer 15 of the second layer. Is formed.

In this way, the repair process is completed by insulating the second cathode electrode layer 15 in the defective cell block 34 from the defective cathode electrode 13. The second cathode electrode layer 15 on the defective portion
May be removed by using the above mapping data again.

As described above, according to the present embodiment, the cell block is selected as a repair unit. Therefore, by using the repair system of the stepper exposure apparatus, only the main electrode of the defective cell block can be selectively selected easily. It can be electrically separated from the main electrode of the normal cell block. Therefore, efficient mechanical repair is possible, and it is possible to prevent a decrease in repair work efficiency due to the progress of miniaturization of power semiconductor elements.

In this embodiment, the repair is carried out after forming the first main electrode, but it may be carried out in another process step. Further, in the present embodiment, the case of using the negative type insulating film has been described, but in the case of using the positive type insulating film,
For example, only the normal cell blocks may be selectively exposed to the normal pattern, and the defective cell blocks may be left unexposed. Alternatively, the positive type insulating film is exposed to the normal pattern, the positive type insulating film on all the main electrodes is patterned, then the negative type insulating film is applied, and then only the defective cell block is entirely exposed to the main electrode of the normal cell block. The negative insulating film above may be removed.

In order to perform more reliable repair, for example, as shown in the plan view of the stage where the first-layer main electrode of FIG. 5 is formed, the cell block gate pad 16,
The cell block control pad 17 and the cell block cathode pad 18 may be provided independently for each cell block.

By providing the various pads 16, 17 and 18 in this way, after forming the second cathode electrode layer, for a normal cell block, the cell block gate pad 16 is connected to the gate bus bar (other insulating layers). (Common gate wiring connected to the gate of the turn-off thyristor with gate)
19, the cell block control pad 17 is connected to the control bus bar (common control wiring that is also connected to the other control electrodes of the same) 20, and the cell block cathode pad 18 is connected to the cathode electrode of the second layer. As a result, normal electrical connection can be obtained.

On the other hand, with respect to the defective cell block, selective lithography is performed using the mask pattern for the defective cell block, and the second cathode electrode layer 15 is formed.
5, which is a sectional view taken along the line AA ′ of FIG. 5 and FIG. 7 is a sectional view taken along the line BB ′ of FIG.
Are both connected to the cell block cathode pad 18.
As a result, it is possible to prevent the pads 16 and 18 from being electrically connected to the busbars 19 and 20 through other power semiconductor elements, respectively, and more reliable repair can be performed.

Next, a repair method according to the second embodiment of the present invention will be described. 8A to 8D are process cross-sectional views showing a method of repairing a bipolar transistor with an insulated gate (IGBT). Here, the gate electrode 8 is assumed to be independent for each cell block.

First, as shown in FIG. 8A, after forming the source electrode 22 which is the main electrode by a well-known method, a defect measurement is performed to identify the defective cell block. Next, FIG.
As shown in (b), after the positive type resist 23 is applied to the entire surface, the positive type resist 23 on the defective cell block 34 is selectively and sequentially exposed using the repair system of FIG.

After that, the positive resist 23 is developed to form a resist pattern, and the source electrode 2 of the defective cell block 34 is formed using this resist pattern as a mask.
2 is selectively removed by etching.

Next, as shown in FIG. 8C, an insulating film 27 is deposited on the entire surface. As a result, only the portion of the defective cell block 34 where the source electrode 22 was present is the insulating film 27.
Is electrically separated from the source electrode 22 of the normal cell block.

After that, the gate electrodes of the normal cell block are connected to each other by bonding or the like to complete the chip. Further, if the source electrode 22 is made independent for each cell block as in the present embodiment, the gate electrode 8 and the source electrode 22 of the defective cell block are short-circuited and other elements are formed in the same manner as in the method of FIG. It can also be independent.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case of the turn-off thyristor with an insulated gate and the IGBT has been described.
It can also be applied to a one-layer main electrode structure element other than GBT.

Further, if, for example, an automatic defect measuring device (such as an auto prober), an insulating film coater and an exposure device are connected by an automatic transfer system and the measurement data of the automatic defect measuring device is automatically transferred to the exposure device, the work efficiency is improved. Can be improved by one layer.

Further, in the above embodiment, the stepper exposure device is used in the repair system, but a direct drawing exposure device may be used instead. FIG. 9 is a plan view of a wafer for explaining the exposure method according to the third embodiment of the present invention. In the figure, reference numeral 30 denotes a wafer.
A plurality of power semiconductor element chips 40 are formed in the.

FIG. 10 is a plan view showing details of the power semiconductor element chip 40. A square area 41 indicated by a broken line indicates an area (one shot area) that can be exposed by one shot of the stepper exposure apparatus. The exposure pattern within one shot is omitted.

A power semiconductor element region composed of a Schottky diode or the like is formed in each 1-shot region 41, and a junction termination region of the device is formed around 21 1-shot regions 41. .

FIG. 11 is a sectional view taken along line CC 'of the power semiconductor element chip 40 of FIG. 10, showing the power semiconductor element region and the junction termination region. In the figure, 42 indicates an n-type base layer, and an anode electrode 51 is formed on the n-type base layer 42 with a Schottky barrier metal layer 49 (for example, a molybdenum layer) interposed.

Further, fine p-type guard ring layers 46 are periodically formed on the surface of the n-type base layer 42. Specifically, the distance between the two p-type guard ring layers 46 is 2 μm.
m, and the width of the p-type guard ring layer 46 is 1 μm.
Is. These p-type guard ring layers 46 are for obtaining the breakdown voltage of the Schottky surface. On the surface of the n-type base layer 42 around the p-type guard ring layer 46, the p-type guard ring layer 4 for protecting the outer periphery of the Schottky surface is formed.
4 are selectively formed.

A p-type guard ring layer 45 for obtaining a high breakdown voltage is selectively formed around the p-type guard ring layer 44, that is, on the surface of the n-type base layer 42 in the junction termination region. An n-type channel stopper layer 47 is selectively formed on the surface of the n-type base layer 42 around the p-type guard ring layer 45, and an electrode 53 is provided on the n-type channel stopper layer 47. This electrode 53 is an insulating film 48.
Is insulated and separated from the anode electrode 51 and the like.

On the other hand, the entire back surface of the n-type base layer 42 has n
^{+ The} cathode electrode 52 is formed via the semiconductor layer 43. An exposure method for manufacturing such a power semiconductor device chip 40 is as follows.

That is, the resist pattern of the p-type guard ring layer 46 which is a fine semiconductor layer is formed by using a stepper exposure apparatus, and the resist pattern of the remaining portion is formed by using a one-to-one whole surface exposure apparatus.

In other words, the junction termination region is exposed using a 1: 1 overall exposure device, and the power semiconductor element region is exposed using a stepper exposure device and a 1: 1 overall exposure device. Either stepper exposure or one-to-one whole surface exposure may be performed first.

In the case of this embodiment, the stepper exposure apparatus is
Since it is used only for forming the resist pattern of the p-type guard ring layer 46, the alignment mark for the stepper is unnecessary. Therefore, as much as the alignment mark is unnecessary,
More area is available for device fabrication.

The alignment mark for the one-to-one whole surface exposure is prepared in the conventional manufacturing process of the element before exposure.
In order to prevent adverse effects on the element characteristics due to this alignment mark, for example, as shown in FIG.
4 may be covered with the insulating film 55.

As in this embodiment, a stepper device is used to form only a fine resist pattern that cannot be formed by a one-to-one whole surface exposure device, and other resist patterns are formed using a one-to-one whole surface exposure device. If it is created, it is possible to create a good (accurate) resist pattern while suppressing a decrease in work efficiency.

Incidentally, the power semiconductor element often has a pressure contact structure. In this case, for example, as shown in FIG. 13, an interlayer insulating film 56 and a pressure-bonding layer are formed by using a one-to-one whole surface exposure apparatus. The second anode electrode 57 may be formed.

In this embodiment, as shown in FIG. 9, 12 power semiconductor chips 4 are provided on one wafer 30.
Although the case of forming 0 has been described, the present invention can be provided even for a larger semiconductor device, for example, one power semiconductor device chip having a size of one wafer.

In other words, in this case, if the power semiconductor chip 40 shown by the solid line in FIG. 10 is read as one wafer, the above description is valid. 14
[FIG. 8A] is a plan view of a wafer for explaining an exposure method according to a fourth embodiment of the present invention. Further, FIG. 15 is a DD ′ cross-sectional view of the power semiconductor element chip 40 of FIG. 14.

A square area 81 indicated by a broken line shows an area (one shot area) which can be exposed by one shot of the stepper exposure apparatus. The exposure pattern within one shot is omitted.

The present embodiment is different from the previous embodiments in that an IGBT is formed in the power semiconductor element region instead of the Schottky diode. In FIG. 15, reference numeral 61 denotes an n-type base layer, and a p-type base layer 62 is selectively formed on the surface of the n-type base layer 61. An n-type source layer 63 is selectively formed on the surface of the p-type base layer 62.
A gate electrode 65 is formed on the p-type base layer 62 sandwiched between the n-type base layer 61 and the n-type base layer 61 with a gate insulating film 64 interposed therebetween.

The p-type base layer 62 and the n-type source 63 are provided with a first cathode electrode 68. This first
The cathode electrode 68 of the gate electrode 65 is formed by the insulating film 67.
It is insulated and isolated. A second cathode electrode 71 is provided on the first cathode electrode 68.

In the figure, reference numeral 66 indicates a gate wiring connected to the gate electrode 65.
The formation region of 6 is the gate wiring region 82 between the square region 81 shown by the broken line and the square region shown by the solid line in FIG. This gate wiring region 82 becomes a registration mark region for step exposure. That is, the alignment mark is formed in the gate wiring region 82.

A first extraction gate electrode 69 is provided on the extraction gate wiring 66, and a second extraction gate electrode 72 is provided on the first extraction gate electrode 69. The formation regions of these extraction gate electrodes 69 and 72 are the shaded regions in FIG. The extraction gate electrodes 69 and 72 are insulated and separated from the cathode electrodes 68 and 71 and the stopper electrode 43 by the interlayer insulating film 70.

On the other hand, a drain electrode 73 is provided on the back surface of the n-type base layer 61 via the p-type emitter layer 60. The junction termination region is the same as that of the previous embodiment, and the portions corresponding to the respective layers of the junction termination region in FIG. 11 are designated by the same reference numerals as those in FIG.

An exposure method for manufacturing such a power semiconductor device chip is as follows. That is, the p-type base layer 62 and the n-type source layer 6 which are fine semiconductor layers.
The resist pattern of No. 3 is formed by using a stepper exposure apparatus, and the resist pattern of the remaining portion is formed by using a one-to-one whole surface exposure apparatus.

In this embodiment, the stepper exposure device is
Since the p-type base layer 62 and the n-type source layer 63 are used to form a plurality of resist patterns, a stepper alignment mark is required. This alignment mark is formed in the gate wiring region 82 as described above.

When the opening of the insulating film is used as the alignment mark, the gate wiring 66 exposed on the bottom surface of the opening and the conductor such as an electrode formed in a later step come into contact with each other, and the device characteristics May deteriorate, so 1: 1
When the resist pattern of the insulating film is formed by the whole surface exposure apparatus, it is preferable to form a resist pattern so that the opening is covered with the insulating film and cover the opening with the insulating film.

Also in this embodiment, only a fine resist pattern, which cannot be formed by the 1: 1 whole surface exposure apparatus, is formed by using the stepper device, and other resist patterns are formed by the one to one whole surface exposure apparatus. Therefore, it is possible to form a good (accurate) resist pattern while minimizing a decrease in work efficiency.

In the present embodiment, the extraction gate electrodes 69 and 72 are formed outside the 21 one-shot areas, but as shown in FIG. 16, they are formed in the shaded areas 83 in the 20 one-shot areas. You may.

In this embodiment, when the one-shot areas of the stepper exposure apparatus are in contact with each other, that is,
Although the case where the one-shot areas 81 are in contact with each other has been described with reference to FIG. 14, for example, when the gate wiring area is small only in the alignment mark area 82 for stepper exposure, the interval between the one-shot areas of the stepper exposure apparatus is set. It only has to be separated by the desired distance.

FIG. 15 is a plan view for explaining an exposure method according to the fifth embodiment of the present invention. In the figure, 84 is 1
One semiconductor chip is shown, one shot area of the stepper exposure apparatus is shown by a broken line square, and the others are omitted.

The feature of this embodiment is that a part of one shot area of the stepper exposure apparatus is exposed by using a mask different from that of the other one shot area, and a plurality of different areas are formed on one large area semiconductor chip. The cell region is formed.

The one-shot area 85 in the figure is, for example, I
A region in which the GBT is formed, which is a one-shot region 86
Is a region in which an IGBT gate circuit is formed, 87 is a region in which a reverse conducting diode is formed, and 88 is a region in which an overvoltage / overcurrent protection circuit is formed. Although not shown, the junction termination region and the wiring region between one shot regions of the stepper exposure apparatus are formed by using a 1: 1 whole surface exposure apparatus. According to the present embodiment, it is possible to form a large area composite element in which the power portion and the logic portion are formed.

Although the Schottky diode and the IGBT are taken as the semiconductor elements in the third and fourth embodiments, the present invention is also effective in the case of other power semiconductor elements such as GTO and MOS thyristor. is there. Other,
Various modifications can be implemented without departing from the spirit of the present invention.

[0082]

[0083]

[0084]

According to the present invention (Claim 1 ), the object of step exposure is limited, and only the resist pattern used for forming the fine portion is formed by step exposure, so that the exposure work efficiency is reduced. While minimizing
It becomes possible to form a good (accurate) resist pattern.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a schematic configuration of a repair system for a power semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view showing a method of repairing a normal cell block according to the first embodiment of the present invention.

FIG. 3 is a process sectional view showing a method of repairing a defective cell block according to the first embodiment of the present invention.

FIG. 4 is a diagram showing mapping data of defective portions.

5 is a plan view showing a modification of the repair method shown in FIGS. 2 and 3. FIG.

6 is a sectional view taken along the line AA ′ in FIG.

7 is a sectional view taken along line BB ′ of FIG.

FIG. 8 is a process sectional view showing a repair method according to a second embodiment of the present invention.

FIG. 9 is a plan view of a wafer for explaining an exposure method according to a third embodiment of the present invention.

FIG. 10 is a plan view showing a part of the wafer of FIG. 9 in detail.

11 is a sectional view taken along the line CC ′ of the wafer of FIG.

FIG. 12 is a sectional view of an alignment mark portion.

FIG. 13 is a cross-sectional view showing an element structure when a crimping structure is used.

FIG. 14 is a plan view of a wafer for explaining an exposure method according to the fourth embodiment of the present invention.

15 is a cross-sectional view of the wafer of FIG. 14 taken along the line D-DC ′.

16 is a plan view showing a modified example of the wafer of FIG.

FIG. 17 is a plan view of a wafer for explaining an exposure method according to the fifth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... High resistance n-type base layer 2 ... p-type base layer 3 ... n-type emitter layer 5 ... p-type emitter layer 7 ... Gate insulating film 8 ... Gate electrode 10 ... 1st insulating film 11 ... Control electrode (1st layer Eye main electrode) 12 High concentration p-type layer 13 Cathode electrode (first layer main electrode) 14 Second insulating film (second layer main electrode) 15 Cathode electrode layer 16 Cell block Gate pad 17 ... Cell block control pad 18 ... Cell block cathode pad 19 ... Gate bus 20 ... Control bus 21 ... Insulating film 22 ... Source electrode (main electrode) 23 ... Positive resist 31 ... Wafer 32 ... Chip 33 ... Cell block 34 ... defective cell block 35 ... light source 36 ... light 37 ... mask pattern 38 ... reducing projection lens 30 ... wafer 40 ... semiconductor device chip 41 ... 1 shot area 42 ... n-type base layer 43 ... n ⁺ semiconductor power 44 ... P-type guard ring layer 45 ... P-type guard ring layer 46 ... P-type guard ring layer 47 ... N-type channel stopper layer 48 ... Insulating film 49 ... Schottky barrier metal layer 51 ... Anode electrode 52 ... Cathode electrode 54 ... Mark 55 ... Insulating film 56 ... Interlayer insulating film 57 ... Second anode electrode 60 ... P-type emitter layer 61 ... N-type base layer 62 ... P-type base layer 63 ... N-type source layer 64 ... Gate insulating film 65 ... Gate electrode 66 ... Gate wiring 67 ... Insulating film 68 ... 1st cathode electrode 69 ... 1st extraction gate electrode 70 ... Interlayer insulation film 71 ... 2nd cathode electrode 72 ... 2nd extraction gate electrode 81 ... 1 shot area 82 ... Gate wiring area

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification symbol FI H01L 29/74 J (72) Inventor Tsuneo Ogura 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center Co., Ltd. ( 72) Inventor Shinji Sato, No. 1, Toshiba-cho, Fuchu-shi, Tokyo Inside the Toshiba Fuchu factory (56) Reference JP-A-4-290270 (JP, A) JP-A-3-218643 (JP, A) JP 62-90931 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (9)

(57) [Claims] 1. A contact with a power semiconductor element region having a fine portion.
Equipped with a power semiconductor element chip consisting of a combined termination region
In the method for manufacturing a power semiconductor device, a resist pattern used for forming the fine portion is formed by step exposure, and a resist pattern used for forming the junction termination region is formed by one-to-one whole surface exposure. Of manufacturing semiconductor device for automobile. 2. The power semiconductor element chip is a single wafer.
A contract characterized by forming at least one or more inside
The method for manufacturing a power semiconductor device according to claim 1. 3. One of the power semiconductor device chips is a wafer.
The size of one sheet is described in claim 1.
Manufacturing method of the power semiconductor device of. 4. An alignment mark used in the step exposure
It is formed in the power semiconductor element region.
The method for manufacturing a power semiconductor device according to claim 1, wherein 5. An alignment mark used in the step exposure
The formation area is a wiring area.
A method of manufacturing the power semiconductor device described. 6. The alignment mark used in the step exposure
Claim that the formation region is a gate wiring region
Item 2. A method for manufacturing a power semiconductor device according to Item 1. 7. The alignment mark used in the step exposure
Cover the insulation layer with an insulating film during the 1: 1 overall exposure process.
7. The method according to claim 4, wherein
Method for manufacturing power semiconductor device. 8. A gate circuit is provided in the power semiconductor device region.
The power semiconductor device according to claim 1, comprising:
Manufacturing method. 9. The power semiconductor element region comprises a power section and a power section.
The battery according to claim 1, further comprising a jig portion.
Method for manufacturing a power semiconductor device.