JP3420092B2 - Semiconductor reliability evaluation device and its evaluation method - Google Patents
Semiconductor reliability evaluation device and its evaluation methodInfo
- Publication number
- JP3420092B2 JP3420092B2 JP34821698A JP34821698A JP3420092B2 JP 3420092 B2 JP3420092 B2 JP 3420092B2 JP 34821698 A JP34821698 A JP 34821698A JP 34821698 A JP34821698 A JP 34821698A JP 3420092 B2 JP3420092 B2 JP 3420092B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- pad
- under test
- constant current
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
- G01R31/2858—Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体信頼性評価
装置とその評価方法に係わり、特に、配線層のエレクト
ロマイグレーションを高精度に測定可能にした半導体信
頼性評価装置とその評価方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor reliability evaluation apparatus and an evaluation method thereof, and more particularly to a semiconductor reliability evaluation apparatus and an evaluation method thereof capable of highly accurately measuring electromigration of a wiring layer.
【０００２】[0002]
【従来の技術】従来、エレクトロマイグレーションの評
価を行うために、図４に示すように、被試験配線１を同
じ層の太い引き出し配線３Ａ，３Ｂを介して電流供給パ
ッド４Ａ，４Ｂに接続させていた。この方法では、被試
験配線１外からアルミニューム（Ａｌ）原子が流れ込
み、この為、被試験配線１の寿命が長くなる等精度良く
評価することができないため、最近では、図５に示すよ
うに、エレクトロマイグレーション寿命試験を行う配線
は、両側をビアホール（コンタクトホール）２Ａ，２Ｂ
で終端し、このビア２Ａ，２Ｂを下層あるいは上層配線
に形成された引き出し配線３Ａ，３Ｂを介して測定用の
パッドに接続している。この引き出し配線には4端子抵
抗測定のために、測定用のパッドとして、電流供給用の
パッド４Ａ，４Ｂと電圧測定用のパッド６Ａ，６Ｂとが
それぞれ両端に設けられている。2. Description of the Related Art Conventionally, in order to evaluate electromigration, as shown in FIG. 4, a wiring under test 1 is connected to current supply pads 4A, 4B through thick lead wirings 3A, 3B in the same layer. It was According to this method, aluminum (Al) atoms flow from the outside of the wiring to be tested 1 and therefore, the lifetime of the wiring to be tested 1 cannot be evaluated with high accuracy. Therefore, recently, as shown in FIG. The wiring for the electromigration life test has via holes (contact holes) 2A and 2B on both sides.
And the vias 2A and 2B are connected to the measurement pad via the lead-out wirings 3A and 3B formed in the lower layer or upper layer wiring. The lead wiring is provided with current supply pads 4A and 4B and voltage measurement pads 6A and 6B at both ends as measurement pads for four-terminal resistance measurement.
【０００３】さて、図４の場合、上記したように被試験
配線１外からＡｌ原子が流れ込み、この為、大きなリザ
ーバーがついているのと等価になるため、被試験配線１
の寿命が長くなり、高精度に評価できないという欠点が
あった。特に、ＡｌＴｉ合金層の存在する配線などでは
ＡｌＴｉ界面をＡｌ原子が流れやすいので、Ａｌ原子が
配線中に多く流れ込み、被試験配線１の寿命が長くな
り、配線中のＡｌ原子が増加して、抵抗が減少する場合
もある。In the case of FIG. 4, Al atoms flow from the outside of the wiring to be tested 1 as described above, which is equivalent to the fact that a large reservoir is attached.
However, it has a drawback that it cannot be evaluated with high accuracy. In particular, in a wiring having an AlTi alloy layer, since Al atoms easily flow in the AlTi interface, a large amount of Al atoms flow into the wiring, the life of the wiring under test 1 becomes long, and the Al atoms in the wiring increase. The resistance may be reduced.
【０００４】一方、図５の評価方法では、配線中でおこ
る不良を評価する前に配線端でのＡ１消失による不良が
起きてしまい、精度良い評価が出来ず、更に、配線膜中
の合金層の形成や覆っている絶縁膜の押え込みの効果な
どの評価もできないという欠点があった。On the other hand, in the evaluation method of FIG. 5, a defect due to A1 disappearance occurs at the end of the wiring before the defect occurring in the wiring is evaluated, and the evaluation cannot be performed accurately. However, there is a drawback in that it is not possible to evaluate the effect of the formation of the film or the pressing of the insulating film covering it.
【０００５】[0005]
【発明が解決しようとする課題】本発明の目的は、上記
した従来技術の欠点を改良し、特に、Ａｌのドリフト起
因による被試験配線の配線端からのＡｌ消失による抵抗
増大等による被試験配線の測定誤差を排除して、高精度
にエレクトロマイグレーションの評価を行えるようにし
た新規な半導体信頼性評価装置とその評価方法を提供す
るものである。SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of the prior art and, in particular, to increase the resistance of the wiring under test due to the disappearance of Al from the wiring end of the wiring under test due to the drift of Al. The present invention provides a novel semiconductor reliability evaluation apparatus and an evaluation method thereof, which eliminates the measurement error of (1) and enables highly accurate evaluation of electromigration.
【０００６】[0006]
【課題を解決するための手段】本発明は上記した目的を
達成するため、基本的には、以下に記載されたような技
術構成を採用するものである。即ち、本発明に係わる半
導体信頼性評価装置の第１態様は、被試験配線のエレク
トロマイグレーションを一対の定電流印加用のパッドと
一対の電圧測定用のパッドとを用いて評価する半導体信
頼性評価装置において、前記被試験配線と各定電流印加
用のパッドとの間には、前記被試験配線及び定電流印加
用のパッドの材料とは異なる材料を埋め込んだビアホー
ルがそれぞれ設けられ、前記一対の電圧測定用のパッド
は、二つの前記ビアホールに挟まれる位置に設けられ、
且つ、前記被試験配線と同じ層に形成されることを特徴
とするものであり、叉、第２態様は、被試験配線のエレ
クトロマイグレーションを一対の定電流印加用のパッド
と一対の電圧測定用のパッドとを用いて評価する半導体
信頼性評価装置において、前記被試験配線と各定電流印
加用のパッドとの間には、前記被試験配線及び定電流印
加用のパッドの材料とは異なる材料を埋め込んだ第１の
ビアホールがそれぞれ設けられ、前記被試験配線と各電
圧測定用のパッドとの間には前記被試験配線及び電圧測
定用のパッドの材料とは異なる材料を埋め込んだ第２の
ビアホールがそれぞれ設けられ、前記第２のビアホール
は、二つの前記第１のビアホールに挟まれる位置に設け
られ、且つ、前記一対の電圧測定用のパッドは、前記被
試験配線と異なる層に形成されることを特徴とするもの
であり、叉、第３態様は、前記被試験配線、定電流印加
用のパッド及び電圧測定用のパッドは第１の材料からな
り、前記ビアホール内のプラグは第２の材料からなり、
前記第１の材料と第２の材料とが異なることを特徴とす
るものであり、叉、第４態様は、前記被試験配線、定電
流印加用のパッド及び電圧測定用のパッドはアルミニウ
ムであり、前記プラグはタングステン、銅、チタン、コ
バルト、の何れかであることを特徴とするものである。In order to achieve the above-mentioned object, the present invention basically adopts the technical constitution as described below. That is, the first aspect of the semiconductor reliability evaluation apparatus according to the present invention is that the electromigration of the wiring under test is performed with a pair of pads for applying a constant current.
In a semiconductor reliability evaluation device for evaluating using a pair of pads for voltage measurement, between the wiring under test and each pad for constant current application, between the wiring under test and the pad for constant current application Via holes embedded with a material different from the material are respectively provided, the pair of pads for voltage measurement is provided at a position sandwiched between the two via holes,
In addition, the second aspect is characterized in that it is formed in the same layer as the wiring under test, and the second aspect is to perform electromigration of the wiring under test with a pair of pads for applying a constant current and a pair of voltages for voltage measurement. In the semiconductor reliability evaluation apparatus for evaluating using the pad and the pad under test, a material different from the material of the test wire and the pad for constant current application is provided between the test wire and each pad for constant current application. respectively provided a first via hole embedded, a material different from the material of the pads to be tested wiring and voltage measurement between the pads to be tested wiring and the conductive <br/> pressure measurement Embedded second via holes are respectively provided, the second via holes are provided at positions sandwiched by the two first via holes, and the pair of voltage measurement pads are connected to the wiring under test. Difference In the third aspect, the wiring under test, the pad for applying a constant current, and the pad for voltage measurement are made of the first material, and the inside of the via hole is formed. The plug is made of a second material,
The first material and the second material are different, and in the fourth aspect, the wiring under test, the pad for applying a constant current, and the pad for measuring voltage are aluminum. The plug is made of any one of tungsten, copper, titanium, and cobalt.
【０００７】叉、本発明に係わる半導体の信頼性評価方
法の第１態様は、被試験配線のエレクトロマイグレーシ
ョンを一対の定電流印加用のパッドと一対の電圧測定用
のパッドとを用いて評価する半導体信頼性評価方法にお
いて、前記被試験配線と各定電流印加用のパッドとの間
には、前記被試験配線及び定電流印加用のパッドの材料
とは異なる材料を埋め込んだビアホールをそれぞれ設け
ると共に、前記一対の電圧測定用のパッドを前記被試験
配線と同じ層に設け、電圧測定は、前記被試験配線上の
二つの前記ビアホールで挟まれた領域の電圧のみを測定
することを特徴とするものであり、叉、第２態様は、被
試験配線のエレクトロマイグレーションを一対の定電流
印加用のパッドと一対の電圧測定用のパッドとを用いて
評価する半導体信頼性評価方法において、前記被試験配
線と各定電流印加用のパッドとの間に、前記被試験配線
及び定電流印加用のパッドの材料とは異なる材料を埋め
込んだ第１のビアホールをそれぞれ設けると共に、被試
験配線と各電圧測定用のパッドとの間には前記被試験配
線及び電圧測定用のパッドの材料とは異なる材料を埋め
込んだ第２のビアホールをそれぞれ設け、前記第２のビ
アホールは、二つの前記第１のビアホールに挟まれる位
置に設けられ、前記一対の電圧測定用のパッドは、前記
被試験配線と異なる層に形成され、電圧測定は、前記被
試験配線上の二つの前記第１のビアホールで挟まれた領
域の電圧のみを測定することを特徴とするものである。In the first aspect of the semiconductor reliability evaluation method according to the present invention, the electromigration of the wiring under test is evaluated by using a pair of constant current application pads and a pair of voltage measurement pads. the semiconductor reliability evaluation method, the between the pads to be tested wiring and the constant current application, respectively provided with a bicycloalkenyl via holes embedding a material different from the material of the pads to be tested wiring and a constant current is applied
In addition, the pair of voltage measurement pads is
Provided on the same layer as the wiring, and measure the voltage on the wiring under test.
And characterized in that to measure only the voltage of the region sandwiched between the two previous millet via hole, or the second aspect, the
Test wiring electromigration with a pair of constant currents
Using a pad for voltage application and a pair of pads for voltage measurement
In the semiconductor reliability evaluation method to be evaluated,
Between the wire and each constant current application pad, the wiring under test
And fill the material different from the material of the pad for applying the constant current.
Each of the embedded first via holes is provided and tested.
Between the test wiring and each voltage measurement pad,
Fill with a different material than the material of the pads for line and voltage measurement
A second via hole is formed in each case, and the second via hole is formed.
The a hole is located between the two first via holes.
And a pair of pads for voltage measurement,
It is formed in a layer different from the wiring under test, and the voltage measurement
The area between the two first via holes on the test wiring
It is characterized in that only the voltage in the range is measured .
【０００８】[0008]
【発明の実施の形態】本発明に係わる半導体信頼性評価
装置は、被試験配線端をビアで終端し、ビアを介して被
試験配線端に電流を流すエレクトロマイグレーション試
験において、電圧測定用のパッドをビアと被試験配線端
との接続部よりも内側に設け、ビア接続部での抵抗変化
を排除して、配線中での抵抗変化のみを正確に測定する
ことを可能にしたものである。BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor reliability evaluation apparatus according to the present invention is a pad for voltage measurement in an electromigration test in which a wiring end to be tested is terminated by a via and a current is passed through the via to the wiring end to be tested. Is provided inside the connection portion between the via and the wiring end to be tested, and the resistance change at the via connection portion is eliminated, and only the resistance change in the wiring can be accurately measured.
【０００９】図１を用いて説明すると、エレクトロマイ
グレーション試験を行う被試験配線端１の両端にビア２
Ａ、２Ｂを設け、このビア２Ａ、２Ｂに接続する下層又
は上層配線層にパッド引き出し配線３Ａ、３Ｂを設け
る。このパッド引き出し配線３Ａ、３Ｂは、電流供給の
ためのパッド４Ａ、４Ｂに接続しており、このパッド４
Ａ、４Ｂから引き出し配線３Ａ、３Ｂ、ビア２Ａ、２Ｂ
を介して被試験配線１に定電流を流す。そして、電圧の
測定は、被試験配線１のビア接続部よりも被試験配線端
１の内側に入ったところに引き出し線５Ａ、５Ｂを設
け、この引き出し線５Ａ、５Ｂに電圧測定用パッド６
Ａ、６Ｂを接続する。Explaining with reference to FIG. 1, vias 2 are formed at both ends of a wiring end 1 to be tested for conducting an electromigration test.
A and 2B are provided, and pad lead-out wirings 3A and 3B are provided in the lower or upper wiring layer connected to the vias 2A and 2B. The pad lead-out wirings 3A and 3B are connected to pads 4A and 4B for supplying a current.
Lead wires 3A, 3B from A, 4B, vias 2A, 2B
A constant current is passed through the wiring 1 under test via. Then, the voltage is measured by providing lead lines 5A and 5B inside the wiring end 1 under test rather than the via connection portion of the wiring under test 1, and the voltage measuring pad 6 is provided on the lead lines 5A and 5B.
Connect A and 6B.
【００１０】このように構成した本発明の半導体信頼性
評価装置において、エレクトロマイグレーション試験の
ため、電流をパッド４Ａから流すと、通常は最初に陰極
側ビア２Ｂとの接続箇所である被試験配線端１の端部か
らボイドが発生する。本発明の装置ではビア２Ｂを含む
箇所の電圧は測定していないため、発生したボイドによ
る影響、例えば、抵抗増大などによる誤差を排除するこ
とができる。従って、その後に起こる配線中でのボイ
ド、ヒロック等でおこる不良による抵抗増大のみを観察
できるから、被試験配線１の状態を高精度に評価出来る
のである。In the semiconductor reliability evaluation apparatus of the present invention having the above-mentioned structure, when an electric current is passed from the pad 4A for the electromigration test, the wiring end under test which is usually the first connection point with the cathode side via 2B is first. A void is generated from the end portion of 1. Since the device of the present invention does not measure the voltage at the portion including the via 2B, it is possible to eliminate the influence of the generated void, for example, the error due to the increase in resistance. Therefore, it is possible to observe only the resistance increase due to defects caused by voids, hillocks, and the like in the wiring that occurs thereafter, so that the state of the wiring under test 1 can be evaluated with high accuracy.
【００１１】更に、図２に示すように、引き出し配線３
Ａ、３Ｂに引き出し配線７Ａ、７Ｂを設けておき、これ
に接続したパッド８Ａ、８Ｂで電圧測定すれば、配線端
からのドリフト起因のボイド発生による不良も評価でき
る。Furthermore, as shown in FIG.
If lead wires 7A and 7B are provided on A and 3B and the voltage is measured with the pads 8A and 8B connected to the lead wires 7A and 7B, defects due to voids caused by drift from the wire ends can be evaluated.
【００１２】[0012]
【実施例】以下に、本発明に係わる半導体信頼性評価装
置とその評価方法の具体例を図面を参照しながら詳細に
説明する。
（第１の具体例）図１は、本発明に係わる半導体信頼性
評価装置とその評価方法の具体例の構造を示す図であっ
て、図１には、被試験配線のエレクトロマイグレーショ
ンを定電流印加用のパッドと電圧測定用のパッドとを用
いて評価する半導体信頼性評価装置において、前記被試
験配線１と定電流印加用のパッド４Ａ、４Ｂとの間に
は、前記被試験配線１及び定電流印加用のパッド４Ａ、
４Ｂの材料とは異なる材料を埋め込んだビアホール２
Ａ、２Ｂが設けられ、電圧測定用のパッド６Ａ、６Ｂ
は、前記ビアホール２Ａ、２Ｂに挟まれるように設けら
れ、且つ、前記被試験配線１と同じ層に形成される半導
体信頼性評価装置が示されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific examples of the semiconductor reliability evaluation apparatus and the evaluation method therefor according to the present invention will be described in detail below with reference to the drawings. (First Specific Example) FIG. 1 is a diagram showing the structure of a semiconductor reliability evaluation apparatus and a specific example of the evaluation method according to the present invention. In FIG. In a semiconductor reliability evaluation apparatus for evaluating using a pad for application and a pad for voltage measurement, between the wiring under test 1 and the pads 4A, 4B for applying constant current, the wiring under test 1 and Pad 4A for applying constant current,
Via hole 2 filled with a material different from the material of 4B
A and 2B are provided, and pads 6A and 6B for voltage measurement are provided.
Shows a semiconductor reliability evaluation device which is provided so as to be sandwiched between the via holes 2A and 2B and which is formed in the same layer as the wiring under test 1.
【００１３】以下に、本発明を更に詳細に説明する。な
お、この具体例では上層配線に形成した被試験配線をエ
レクトロマイグレーション試験する場合に付いて説明す
る。下層の引き出し配線３Ａ、３Ｂは太さ２０μｍであ
り、例えば、ＴｉＮ／ＡｌＣｕ／ＴｉＮ／Ｔｉからな
り、電流供給パッド４Ａ、４Ｂに接続している。下層の
引き出し配線３Ａ、３Ｂとエレクトロマイグレーション
試験を行う上層の被試験配線１を接続するビア２Ａ、２
Ｂは、タングステン（Ｗ）プラグである。被試験配線１
は太さ８μｍで、例えば、ＴｉＮ／ＡｌＣｕ／ＴｉＮ／
Ｔｉからなる。The present invention will be described in more detail below. It should be noted that in this specific example, description will be made on the case where the wiring to be tested formed on the upper layer wiring is subjected to the electromigration test. The lower lead wires 3A and 3B have a thickness of 20 μm, are made of, for example, TiN / AlCu / TiN / Ti, and are connected to the current supply pads 4A and 4B. Vias 2A and 2 for connecting the lower-layer lead-out wirings 3A and 3B to the upper-layer wiring under test 1 for performing an electromigration test
B is a tungsten (W) plug. Wiring under test 1
Has a thickness of 8 μm, for example, TiN / AlCu / TiN /
It consists of Ti.
【００１４】被試験配線１のビア接続部から１０μｍ内
側に入ったところに電圧測定のための引き出し配線５
Ａ、５Ｂを設け、電圧測定のためのパッド６Ａ、６Ｂに
接続する。このように構成した半導体信頼性評価装置に
おいて、パッド４Ａから４Ｂに電流を流すと、ビア２
Ａ、２Ｂを介して試験配線１に電流が流れる。そして、
エレクトロマイグレーションにより陰極側のビア２Ｂと
の接続部から被試験配線１にボイドが生じる。このボイ
ド発生は、Ａｌ原子流が配線端のタングステン（Ｗ）プ
ラグ接続部で不連続となることで生じるドリフト起因に
よる不良である。A lead-out wiring 5 for measuring voltage at a position 10 μm inside from the via connection portion of the wiring 1 to be tested.
A and 5B are provided and connected to pads 6A and 6B for voltage measurement. In the semiconductor reliability evaluation apparatus configured as described above, when a current is passed from the pads 4A to 4B, the via 2
A current flows through the test wiring 1 via A and 2B. And
A void is generated in the wiring under test 1 from the connection portion with the via 2B on the cathode side due to electromigration. This void generation is a defect due to drift caused by the discontinuity of the Al atomic flow at the tungsten (W) plug connection portion at the wiring end.
【００１５】しかし、本発明では、電圧測定用パッド６
Ａ、６Ｂをビア２Ａ、２Ｂ接続部よりも被試験配線１の
内側に設けてあるため、このボイド発生による抵抗上昇
は測定されない。更に電流を流し続けていくと、配線中
でのボイドが発生し始める。この不良は配線中でのＡｌ
原子流の不連続によるものであり、ＡｌＣｕの粒界構造
や結晶性が原因となっている。この配線中の不良による
電圧変化が測定され、抵抗変化がモニタされる。However, in the present invention, the voltage measuring pad 6 is used.
Since A and 6B are provided on the inner side of the wiring under test 1 with respect to the vias 2A and 2B connection portions, the resistance increase due to the occurrence of the void is not measured. When the current is further applied, voids in the wiring start to occur. This defect is due to Al in the wiring
This is due to the discontinuity of the atomic flow, and is caused by the grain boundary structure and crystallinity of AlCu. The voltage change due to the defect in the wiring is measured and the resistance change is monitored.
【００１６】（第２の具体例）次に、本発明の第２の具
体例について、図３を用いて説明する。この具体例で
は、電圧測定用パッド６Ａ、６Ｂに接続する引き出し配
線５Ａ、５Ｂを被試験配線１に設けた第２のビア９Ａ、
９Ｂを介して接続するように構成している。第１の具体
例では、被試験配線と電圧測定用パッドとは同層であっ
たが、図３では、引き出し配線５Ａ、５Ｂは、被試験配
線１とは異なる層に形成されている。(Second Specific Example) Next, a second specific example of the present invention will be described with reference to FIG. In this specific example, the lead-out wirings 5A and 5B connected to the voltage measurement pads 6A and 6B are provided in the wiring 1 under test to form the second via 9A,
It is configured to be connected via 9B. In the first specific example, the wiring under test and the voltage measurement pad are on the same layer, but in FIG. 3, the lead wirings 5A, 5B are formed on a layer different from the wiring under test 1.
【００１７】第１の具体例で示したように構成すると、
引き出し配線５Ａ、５Ｂから被試験配線１にＡｌ原子が
流れ込む可能性がある。このような電流が流れていない
ところからもＡｌ原子が移動することは広く知られてい
る。被試験配線と引き出し配線の配線幅が明らかに異な
る（被試験配線幅＞引き出し配線幅）ときは問題ない
が、被試験配線１の幅が細くなり、引き出し配線５Ａ、
５Ｂの幅と同等あるいは細くなった場合には、この引き
出し配線からのＡｌ原子の流れ込みが無視できなくなる
場合がある。When constructed as shown in the first specific example,
Al atoms may flow into the DUT 1 from the lead wires 5A and 5B. It is widely known that Al atoms move from a place where such a current does not flow. When the wiring widths of the wiring under test and the lead-out wiring are obviously different (wiring width under test> leading-out wiring width), there is no problem, but the width of the wiring under test 1 becomes thin and the leading wiring 5A,
If the width is equal to or narrower than the width of 5B, the flow of Al atoms from the lead wiring may not be negligible.
【００１８】被試験配線がバンブー構造で、引き出し配
線が石垣状グレインの場合は、引きだし配線からのＡｌ
原子は粒界拡散となり、被試験配線中の格子拡散あるい
は界面拡散よりも起こりやすくなり、配線中へのＡｌ原
子の流入がおこる。従って、この具体例では、引き出し
配線５Ａ、５Ｂをビア９Ａ、９Ｂを介して接続するよう
にした。但し、被試験配線１にビアを設けると、配線の
膜質に影響を与えることもある。例えば、タングステン
（Ｗ）プラグの凹みや下地が異なることでＡｌＣｕの結
晶性が変わることがある。しかし、ＷＣＭＰなどを用
い、ＣＭＰ後、バリアメタルを引き直すことでそのよう
なことはなくなる。If the wiring under test has a bamboo structure and the lead-out wiring is a stone wall-shaped grain, Al from the lead-out wiring is used.
Atoms become grain boundary diffusion, which is more likely to occur than lattice diffusion or interface diffusion in the wiring under test, and Al atoms flow into the wiring. Therefore, in this specific example, the lead wirings 5A and 5B are connected via the vias 9A and 9B. However, providing a via on the wiring under test 1 may affect the film quality of the wiring. For example, the crystallinity of AlCu may change due to the difference in the depression or the underlying layer of the tungsten (W) plug. However, by using WCMP or the like and redrawing the barrier metal after CMP, such a thing is eliminated.
【００１９】従って、評価デバイスの配線構造や配線幅
によって、第１の具体例と第２の具体例とを使い分ける
ことで、より正確なエレクトロマイグレーション試験を
行うことができる。Therefore, a more accurate electromigration test can be performed by properly using the first concrete example and the second concrete example depending on the wiring structure and wiring width of the evaluation device.
【００２０】[0020]
【発明の効果】配線の陰極側の配線端からＡｌ原子がな
くなり、Ａｌ消失に至ること（Ａｌ原子のドリフト起
因）が最初に起きる不良の原因である。しかし、この他
にも配線中での粒界構造や結晶性、合金層（例えば、Ａ
ｌ3Ｔｉ）よってＡｌ原子の流れの不均一や配線を覆っ
ている膜応力なとがボイド及びヒロックによる不良原因
となる。EFFECTS OF THE INVENTION The fact that Al atoms disappear from the wiring end on the cathode side of the wiring and Al disappears (due to the drift of Al atoms) is the cause of the first defect. However, in addition to this, the grain boundary structure in the wiring, the crystallinity, the alloy layer (for example, A
l 3 Ti) Accordingly bets film stress covering uneven and wiring of the flow of Al atoms is failure cause by voids and hillocks.
【００２１】本発明に係わる半導体信頼性評価装置とそ
の評価方法では、Ａｌのドリフト起因による被試験配線
の配線端からのＡｌ消失による抵抗増大等による測定誤
差を排除するために、電圧測定用パッドを配線端より内
側から引き出すように構成したので、被試験配線に生じ
る配線端からのドリフト起因以外の不良を正確に評価で
きる。即ち、被試験配線以外からのＡｌ原子の流れ込み
がなく、且つ、配線中のＡｌ原子ドリフトに起因するも
の以外の不良による寿命を高精度に評価することができ
るという優れた効果を有する。In the semiconductor reliability evaluation apparatus and the evaluation method thereof according to the present invention, in order to eliminate the measurement error due to the resistance increase due to the disappearance of Al from the wiring end of the wiring under test due to the drift of Al, the voltage measurement pad is used. Since it is configured to be pulled out from the inside of the wiring end, it is possible to accurately evaluate defects other than those caused by drift from the wiring end that occur in the wiring under test. That is, there is an excellent effect that there is no inflow of Al atoms from other than the wiring under test, and the life due to defects other than those caused by Al atom drift in the wiring can be evaluated with high accuracy.
【図１】本発明に係わる半導体信頼性評価装置の第１の
具体例を示す図である。FIG. 1 is a diagram showing a first specific example of a semiconductor reliability evaluation apparatus according to the present invention.
【図２】図１の変形例を示す図である。FIG. 2 is a diagram showing a modification of FIG.
【図３】本発明の第２の具体例を示す図である。FIG. 3 is a diagram showing a second specific example of the present invention.
【図４】従来技術を示す図である。FIG. 4 is a diagram showing a conventional technique.
【図５】従来技術を示す図である。FIG. 5 is a diagram showing a conventional technique.
１ 被試験配線 ２Ａ、２Ｂ 第１のビアホール ３Ａ、３Ｂ 下層の引き出し配線 ４Ａ、４Ｂ 定電流供給パッド ５Ａ、５Ｂ 引き出し配線 ６Ａ、６Ｂ 電圧測定パッド ７Ａ、７Ｂ 第２の引き出し配線 ８Ａ、８Ｂ 第２の電圧測定パッド ９Ａ、９Ｂ 第２のビアホール 1 Tested wiring 2A, 2B First via hole 3A, 3B Lower layer lead wiring 4A, 4B constant current supply pad 5A, 5B Lead wiring 6A, 6B voltage measurement pad 7A, 7B Second lead wiring 8A, 8B Second voltage measurement pad 9A, 9B Second via hole
フロントページの続き (56)参考文献 特開 平５−90361（ＪＰ，Ａ) Ｂａｅｒｇ，Ｒｅｃｅｎｔ Ｐｒｏｂ ｌｅｍｓ ｉｎ Ｅｌｅｃｔｒｏｍｉｇ ｒａｔｉｏｎ Ｔｅｓｔｉｎｇ，Ａｎｎ ｕ．Ｐｒｏｃ．Ｉｎｔ．Ｒｅｌｉａｂ. Ｐｈｙｓ．Ｓｙｍｐ．，米国，1997年, Ｖｏｌ．35，ｐ．211−215 (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/66 ＪＩＣＳＴファイル（ＪＯＩＳ)Continuation of the front page (56) Reference JP-A-5-90361 (JP, A) Baerg, Recent Problems in Electromigration Testing, Ann u. Proc. Int. Reliab. Phys. Symp. , USA, 1997, Vol. 35, p. 211-215 (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/66 JISST file (JOIS)
Claims (6)
ンを一対の定電流印加用のパッドと一対の電圧測定用の
パッドとを用いて評価する半導体信頼性評価装置におい
て、 前記被試験配線と各定電流印加用のパッドとの間には、
前記被試験配線及び定電流印加用のパッドの材料とは異
なる材料を埋め込んだビアホールがそれぞれ設けられ、
前記一対の電圧測定用のパッドは、二つの前記ビアホー
ルに挟まれる位置に設けられ、且つ、前記被試験配線と
同じ層に形成されることを特徴とする半導体信頼性評価
装置。1. A semiconductor reliability evaluation apparatus for evaluating by using the pads for voltage measurement pad and a pair for applying a pair of constant current electromigration of the testing wiring, the tested wiring and the constant current application Between the pad for
Via holes filled with a material different from the materials of the wiring under test and the pad for applying a constant current are provided,
The semiconductor reliability evaluation device according to claim 1, wherein the pair of voltage measurement pads are provided between the two via holes and are formed in the same layer as the wiring under test.
ンを一対の定電流印加用のパッドと一対の電圧測定用の
パッドとを用いて評価する半導体信頼性評価装置におい
て、 前記被試験配線と各定電流印加用のパッドとの間には、
前記被試験配線及び定電流印加用のパッドの材料とは異
なる材料を埋め込んだ第１のビアホールがそれぞれ設け
られ、前記被試験配線と各電圧測定用のパッドとの間に
は前記被試験配線及び電圧測定用のパッドの材料とは異
なる材料を埋め込んだ第２のビアホールがそれぞれ設け
られ、前記第２のビアホールは、二つの前記第１のビア
ホールに挟まれる位置に設けられ、且つ、前記一対の電
圧測定用のパッドは、前記被試験配線と異なる層に形成
されることを特徴とする半導体信頼性評価装置。2. A semiconductor reliability evaluation apparatus for evaluating electromigration of a wiring under test using a pair of pads for applying a constant current and a pair of pads for measuring a voltage, wherein the wiring under test and each constant current application Between the pad for
Said first via hole with embedded material different from the material of the pad to be tested wiring and a constant current is applied are respectively provided, the device under test lines and between the pads for the voltage measurement and the test wiring second via holes are respectively provided with embedded material different from the material of the pads for voltage measurement, the second via hole is provided in a position sandwiched between two of said first via hole, and, of the pair Electric
The semiconductor reliability evaluation apparatus , wherein the pressure measurement pad is formed in a layer different from the wiring under test.
及び電圧測定用のパッドは第１の材料からなり、前記ビ
アホール内のプラグは第２の材料からなり、前記第１の
材料と第２の材料とが異なることを特徴とする請求項１
又は２記載の半導体信頼性評価装置。3. The wiring under test, the pad for applying a constant current, and the pad for voltage measurement are made of a first material, and the plug in the via hole is made of a second material. The material of claim 2 is different from the material of claim 2.
Alternatively, the semiconductor reliability evaluation apparatus according to item 2.
及び電圧測定用のパッドはアルミニウムであり、前記プ
ラグはタングステン、銅、チタン、コバルト、の何れか
であることを特徴とする請求項３記載の半導体信頼性評
価装置。4. The wiring under test, the pad for applying a constant current and the pad for measuring a voltage are made of aluminum, and the plug is made of any one of tungsten, copper, titanium and cobalt. 3. The semiconductor reliability evaluation device described in 3.
ンを一対の定電流印加用のパッドと一対の電圧測定用の
パッドとを用いて評価する半導体信頼性評価方法におい
て、 前記被試験配線と各定電流印加用のパッドとの間には、
前記被試験配線及び定電流印加用のパッドの材料とは異
なる材料を埋め込んだビアホールをそれぞれ設けると共
に、前記一対の電圧測定用のパッドを前記被試験配線と
同じ層に設け、電圧測定は、前記被試験配線上の二つの
前記ビアホールで挟まれた領域の電圧のみを測定するこ
とを特徴とする半導体の信頼性評価方法。 5. The semiconductor reliability evaluation method of evaluating by using the pads for voltage measurement pad and a pair of a pair of constant current application electromigration of the testing wiring, the tested wiring and the constant current application Between the pad for
Co Providing said to be tested wires and constant current application pad materials and a bi via holes embedding a material different from each
In addition, the pair of pads for voltage measurement and the wiring under test.
Provided in the same layer, the voltage measurement, the semiconductor reliability evaluation method characterized by measuring only voltages of the region sandwiched by two <br/> before millet via hole on the test line.
ンを一対の定電流印加用のパッドと一対の電圧測定用の
パッドとを用いて評価する半導体信頼性評価方法におい
て、 前記被試験配線と各定電流印加用のパッドとの間に、前
記被試験配線及び定電流印加用のパッドの材料とは異な
る材料を埋め込んだ第１のビアホールをそれぞれ設ける
と共に、被試験配線と各電圧測定用のパッドとの間には
前記被試験配線及び電圧測定用のパッドの材料とは異な
る材料を埋め込んだ第２のビアホールをそれぞれ設け、
前記第２のビアホールは、二つの前記第１のビアホール
に挟まれる位置に設けられ、前記一対の電圧測定用のパ
ッドは、前記被試験配線と異なる層に形成され、電圧測
定は、前記被試験配線上の二つの前記第１のビアホール
で挟まれた領域の電圧のみを測定することを特徴とする
半導体の信頼性評価方法。 6. Electromigration of wiring under test
A pair of constant current application pads and a pair of voltage measurement pads.
In the semiconductor reliability evaluation method evaluated using the pad
Between the wiring under test and the pads for applying each constant current.
Different from the material of the wiring under test and the pad for applying constant current.
First via holes with embedded materials
In addition, between the wiring under test and each voltage measurement pad
Different from the material of the wiring under test and the pad for voltage measurement.
Second via holes with embedded materials
The second via holes are two of the first via holes.
It is installed at a position sandwiched between
The pad is formed on a layer different from the wiring under test and is used for voltage measurement.
The two are the first via holes on the wiring under test.
Characterized by measuring only the voltage in the region sandwiched by
Semiconductor reliability evaluation method.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34821698A JP3420092B2 (en) | 1998-12-08 | 1998-12-08 | Semiconductor reliability evaluation device and its evaluation method |
| KR1019990055394A KR100346179B1 (en) | 1998-12-08 | 1999-12-07 | A reliability evaluation device of electromigration of a semiconductor device and method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34821698A JP3420092B2 (en) | 1998-12-08 | 1998-12-08 | Semiconductor reliability evaluation device and its evaluation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000174085A JP2000174085A (en) | 2000-06-23 |
| JP3420092B2 true JP3420092B2 (en) | 2003-06-23 |
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ID=18395538
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34821698A Expired - Fee Related JP3420092B2 (en) | 1998-12-08 | 1998-12-08 | Semiconductor reliability evaluation device and its evaluation method |
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| Country | Link |
|---|---|
| JP (1) | JP3420092B2 (en) |
| KR (1) | KR100346179B1 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10108915A1 (en) * | 2001-02-23 | 2002-09-12 | Infineon Technologies Ag | Electromigration test structure to measure reliability of wiring |
| KR100494116B1 (en) * | 2002-11-20 | 2005-06-10 | 매그나칩 반도체 유한회사 | Method for estimating reliability of metal line |
| US7858406B2 (en) | 2007-02-06 | 2010-12-28 | Infineon Technologies Ag | Semiconductor device test structures and methods |
| US7851237B2 (en) | 2007-02-23 | 2010-12-14 | Infineon Technologies Ag | Semiconductor device test structures and methods |
| CN104576613B (en) * | 2013-10-29 | 2017-08-25 | 中芯国际集成电路制造(上海)有限公司 | Electro-migration testing method and structure |
| CN108152699B (en) * | 2017-12-27 | 2020-07-10 | 中国电子产品可靠性与环境试验研究所 | Electromigration life time testing device and testing method of contact hole |
| CN110071053A (en) * | 2019-04-29 | 2019-07-30 | 上海华力微电子有限公司 | A kind of electro-migration testing structure |
| CN110620058B (en) * | 2019-09-23 | 2022-02-11 | 上海华力微电子有限公司 | Electromigration reliability test structure and electromigration reliability test method |
| CN114264926B (en) * | 2021-11-26 | 2024-06-21 | 中国电子科技集团公司第五十八研究所 | Single-through hole cross-layer electromigration test structure of single-side lead-out voltage test pad |
| CN117054857B (en) * | 2023-10-11 | 2023-12-22 | 江苏祥和电子科技有限公司 | Electromigration reliability test method and system for welding spots of vehicle-gauge-level packaging circuit |
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| JP2570155B2 (en) * | 1993-11-11 | 1997-01-08 | 日本電気株式会社 | Semiconductor device |
-
1998
- 1998-12-08 JP JP34821698A patent/JP3420092B2/en not_active Expired - Fee Related
-
1999
- 1999-12-07 KR KR1019990055394A patent/KR100346179B1/en not_active Expired - Fee Related
Non-Patent Citations (1)
| Title |
|---|
| Ｂａｅｒｇ，Ｒｅｃｅｎｔ Ｐｒｏｂｌｅｍｓ ｉｎ Ｅｌｅｃｔｒｏｍｉｇｒａｔｉｏｎ Ｔｅｓｔｉｎｇ，Ａｎｎｕ．Ｐｒｏｃ．Ｉｎｔ．Ｒｅｌｉａｂ．Ｐｈｙｓ．Ｓｙｍｐ．，米国，１９９７年，Ｖｏｌ．３５，ｐ．２１１−２１５ |
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| KR20000047955A (en) | 2000-07-25 |
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