JP3420698B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device composed of a Schottky junction device composed of a semiconductor and a barrier metal, and a method of manufacturing the same, and more particularly to suppressing power loss by suppressing a forward voltage drop. The present invention relates to a semiconductor device capable of reducing a reverse current and a manufacturing method thereof.

[0002]

2. Description of the Related Art It is generally known that when a metal and a semiconductor are brought into contact with each other, a potential barrier is generated to exhibit a rectifying action. A Schottky barrier diode utilizes this property, but the response current is extremely fast because only the majority carriers of the semiconductor are involved in the current flowing through this diode. Therefore, the diode is suitable for high-speed switching and high-frequency operation.

FIG. 7A is a basic cross-sectional structural view of a Schottky barrier diode, which is a basic structure of a Schottky barrier diode in which a barrier metal layer 102 is joined on an N− type semiconductor 101.

As a structure for reducing the reverse leakage current of such a Schottky barrier diode, for example, FIG.
(B) and FIG. 7 (c) are available.

FIG. 7B is a cross-sectional structural view of a Schottky barrier diode which is a first conventional example, in which an acceptor is diffused from the surface of the N-type semiconductor 101 to form a P + type region 103. is there.

In this diode, a plurality of P + diffusion layers 103 are formed in stripes on an N-epitaxial Si layer 101 grown on an N + Si substrate (not shown) at predetermined intervals. Furthermore, N-epitaxial Si
A Schottky barrier electrode 102 (anode side) is provided on the layer 101, and an ohmic electrode (cathode side) is provided below the N + Si substrate.

In the diode having such a structure, the Schottky barrier electrode 102 and the N-epitaxial Si are used.
Due to the Schottky barrier generated at the contact portion with the layer 101, the Schottky barrier electrode 102 and the ohmic electrode 7
When a forward voltage is applied between the two, the electrons in the N-epitaxial Si layer 101 having a high energy level are injected toward the Schottky barrier electrode 102 and a forward current flows, but the reverse voltage is applied. In some cases, the Schottky barrier electrode 102 causes N
-Electrons are prevented from moving to the epitaxial Si layer 101, and the reverse current becomes a constant minute amount regardless of the applied voltage. Thus, this diode has a rectifying function.

Next, a method of manufacturing the diode shown in FIG. 7B will be described.

N-epitaxial Si on N + Si substrate
After growing the layer 101, a Si oxide film is formed to a thickness of about 100 nm. Then, a stripe-shaped opening having a width of about 1 μm is formed in the Si oxide film by photolithography, and then impurities are ion-implanted so that the impurity distribution has a peak at a depth of about 200 nm. Then, a P + diffusion layer 103 having a depth of 2 μm is formed on the N− epitaxial Si layer 101 by heat treatment, the Si oxide film is removed, and N + S is removed.
The Schottky barrier electrode 102 is formed on the i substrate by N + Si.
An ohmic electrode is formed under the substrate.

However, when a diode is manufactured by the above-described manufacturing method, the diffusion of impurities into Si is usually performed in the lateral direction at a rate of about 0.8 times the depth direction, regardless of the type of impurities implanted. To proceed, P + diffusion layer 1
When the impurities are diffused to a depth of 2 μm in the formation of 03, they are laterally diffused by 1.6 μm each in the lateral direction, resulting in a lateral diffusion width of 3.2 μm.
That is, when the opening width of 1 μm is combined, the lateral diffusion width is 4.2 μm as a whole, which means that the diffusion proceeds by 4.2 times the ideal value of 1 μm, and the lateral width of the P + diffusion layer 103 becomes too large. was there.

In order to solve such a problem, a Schottky barrier diode having a structure as shown in FIG. 7C has been proposed.

FIG. 7C is a sectional view of a Schottky barrier diode which is a second conventional example. After forming a trench 110 on the surface of the N-type semiconductor 101, polysilicon including an acceptor is buried. P + type area 1 around it
11 is formed. According to this structure, the width of the P + diffusion layer can be reduced.

According to the structures of FIGS. 7B and 7C, N-epitaxial Si when a reverse voltage is applied is applied.
The depletion layer extending to the layer 101 side is closer to the pinch-off state than the structure of FIG. 7A, and as shown in FIG. 8, the effect of reducing the reverse leakage current is obtained as compared with the structure of FIG.

FIG. 8 is a graph showing the reverse leakage current characteristic of the above conventional example.

The horizontal axis represents the reverse voltage V and the vertical axis represents the leak current I. In the figure, Q1 is the characteristic curve of the diode having the structure shown in FIG. 7A, and Q2 is the characteristic curve of the diode having the structures shown in FIGS. 7B and 7C (first and second conventional examples).

As is apparent from the figure, when the reverse voltage is increased, the value of FIG.
The current I is suppressed in the structures (b) and (c), and the reverse leakage current is reduced.

As a Schottky barrier diode showing a concrete example of the above-mentioned first and second conventional examples, there is one disclosed in, for example, Japanese Patent Laid-Open No. 3-105975.

FIG. 9 is a sectional structural view of the Schottky barrier diode disclosed in the above-mentioned publication.

In order to reduce the loss of this diode, the P + type region 204 is formed in the Schottky junction at the interval and depth at which the depletion layer is pinched off to reduce the reverse leakage current. That is, the distance between the P + type regions 204 is W, the depth of the P + type regions 204 is D, and the N− semiconductor layer 2 is formed.
When the width of the depletion layer that spreads to the N− semiconductor layer 202 side due to the diffusion potential of the PN junction formed between the No. 02 and the P + type region 204 is Wo, P + satisfies the relationship of 2Wo <W ≦ 3D. A mold region 204 is formed. In the figure, 201 is an ohmic electrode, 202 is an N + semiconductor substrate, 2
Reference numeral 05 is a Schottky barrier electrode.

[0020]

However, in the Schottky barrier diode (FIG. 9) of the above-mentioned conventional publication including the above-mentioned first and second conventional examples, the Schottky junction area within the same chip area is reduced. Forward voltage loss increases. To suppress this, it is possible to expand the bonding area in the lateral direction, but this will increase the chip size and the price, and it will be mounted in small envelopes where needs are increasing. Becomes difficult.

The present invention has been made in order to solve the above-mentioned conventional problems, and an object thereof is to realize a semiconductor device which realizes reduction of forward loss and backward loss while suppressing the chip size, and manufacturing thereof. Is to provide a method.

[0022]

In order to achieve the above object, a feature of the first invention is that it has a semiconductor layer of the first conductivity type and electrodes sandwiching the semiconductor layer, and the semiconductor layer has a predetermined size. Recesses are formed in a plurality of regions of the
In a semiconductor device in which a conductive type buried layer and a second conductive type first diffusion layer are formed around the buried layer, a Schottky junction portion between the second conductive type first diffusion layers is recessed. This is because the trench portion to be shaped is provided.

According to the first aspect of the present invention, the Schottky junction area, which has been flat, is made concave to increase the Schottky junction area. As a result, forward loss is reduced.

A feature of the second invention is that, in the first invention, the second conductivity type second diffusion layer is provided in the first conductivity type semiconductor layer in the vicinity of the bottom end portion of the trench portion. is there.

According to the second aspect of the invention, the electric field strength is reduced and the reverse loss is reduced.

A feature of the third invention is that the first invention is provided on a semiconductor substrate.
A first step of forming a conductive type semiconductor layer; a second step of removing a plurality of predetermined regions of the first conductive type semiconductor layer to form a plurality of first recesses; The buried layer having a higher impurity diffusion rate than the semiconductor layer is formed in each of the first
After forming the recess of a third step of forming respectively a semiconductor layer of a second conductivity type surrounding the first recess by an impurity diffusion, the second between the semiconductor layer mutually the second conductivity type A fourth step of forming a second recess in the semiconductor layer region of the first conductivity type and a fifth step of forming a barrier metal in a form of filling the second recess on the surface of the semiconductor layer of the first conductivity type are performed. Especially.

A feature of the fourth invention is that, in the above-mentioned third invention, the sixth step of diffusing impurities at the bottom end of each of the second recesses is performed between the fourth step and the fifth step. To run into.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below.

FIG. 1 is a sectional view of a Schottky barrier diode according to the first embodiment of the present invention.

This diode is, for example, an N + Si substrate 1
1 has an N-epitaxial Si layer 12 epitaxially grown thereon, and a barrier metal 22 (on the anode side) is further formed on the N-epitaxial Si layer 12.

An ohmic electrode 23 (cathode side) is formed on the opposite surface side of the N + Si substrate 11.
Further, the N− epitaxial Si layer 12 is provided with a plurality of recesses 15, and the P + diffusion layer 17 is provided around the recesses 15.
Is formed, and poly-Si is embedded in the recess 15.

Further, a trench portion 19 is formed in the N− type semiconductor region between the P + type regions 17, and a barrier metal layer 22 is provided thereon. A P + diffusion region 21 is formed around the lower end of the trench 19 so as to project from the bottom end of the trench 19 to the N− epitaxial Si layer 12.

As described above, in this embodiment, the Schottky junction area is increased by making the N − type semiconductor regions between the P + type regions 17 into a concave shape by forming a trench structure, thereby increasing the Schottky junction area, which will be described later with reference to FIG. It is possible to reduce the forward voltage drop as shown in.

On the other hand, the bottom end of the trench 19 is formed at a relatively acute angle, which may cause concentration of an electric field in the reverse bias state. In order to avoid this, the P + type region 21 is formed so as to reduce the electric field strength.
The depth of the trench portion 19 is shallower than each P + type region 17 (for example, 1/2) so that the reverse leak current is not increased.

According to the diode of this embodiment,
N-type epitaxial Si layer 12 at Schottky junction
At a distance and depth at which the depletion layer is pinched off.
In the Schottky barrier diode having the + type region 17, the Schottky junction portion between the P + type regions 17 is formed in a concave shape (trench portion 19) to increase the junction area, thereby reducing the forward loss. be able to.

Further, P + is also formed at the bottom end of the trench portion 19.
A type region 21 is formed to reduce the electric field strength at the time of reverse bias, and the depth of the trench portion 19 is set to each P + type region 17
Since it is formed shallower than the above, the reverse leakage current can be reduced.

Next, a method of manufacturing the above-mentioned diode shown in FIG. 1 will be described with reference to FIGS. 2, 3 and 4.

First, as shown in FIG. 2A, N + Si
An N-epitaxial Si layer 12 is grown on the substrate 11.

Next, as shown in FIG. 2B, the oxide film 13 formed on the N-epitaxial Si layer 12 is patterned by a photolithography technique, and further, the N-epitaxial Si layer is used as a mask with the ugly film 13 as a mask. 12
Is dry-etched to form the trench portion 14. In this case, the trench portion 14 has a depth of 4 μm and a width of 1
μm, the distance from the bottom of the trench 14 to the upper surface of the N + Si substrate is 4 μm, and the distance between the trenches 14 is 5 μm.
And

Next, as shown in FIG. 2C, the poly-Si layer 15 is CVD (Che) so that the trench portion 14 formed in the N-epitaxial Si layer 12 is completely filled.
It is deposited by a method such as a medical vapor deposition method.

Next, as shown in FIG. 3D, until the surfaces of the poly-Si layer 15 buried in the trench portion 14 and the N-epitaxial Si layer 12 are aligned and flattened, the poly-S layer is formed.
The i layer 15 is dry-etched, and a P-type impurity 16 such as boron (B) is added to the poly S by an ion implantation technique.
Implantation is performed near the surface of the buried layer 15. At this time, since the oxide film 13 serves as a mask for ion implantation, impurities 16
Will be implanted only in the poly-Si buried layer 15.

Next, as shown in FIG. 3E, poly-Si is used.
P-type impurities 16 implanted near the surface of the buried layer 15
Is diffused into the poly-Si embedded layer 15 by heat treatment,
The P + diffusion layer 17 is formed. At this time, since the impurity diffusion rate of poly-Si is higher than that of Si, most of the implanted P-type impurities 16 will first have the poly-Si burying layer 1.
5 and then diffuses into the N− epitaxial Si layer 12 around the trench 14 to form the P + diffusion layer 17.

After that, as shown in FIG. 3F, the oxide film 13 is removed and a new oxide film 18 is formed on the wafer.
Further, as shown in FIG. 4G, recesses (trench grooves) 19 are formed between the P + diffusion regions 17 by the photography technique. Then, the P-type impurity 20 is implanted using the oxide film 18 as a mask to form the P + diffusion region 21 at the bottom of each recess 19.

Finally, a barrier metal 22 is formed on the upper surface of the wafer so as to fill the recesses 19, and an ohmic electrode 23 is deposited on the bottom surface of the wafer to obtain a Schottky diode having the structure shown in FIG. .

FIG. 5 is a graph showing the forward voltage drop characteristics comparing the structures of FIGS. 7B and 7C of the conventional example with the structure of FIG. 1 of the present embodiment.

The ordinate represents the forward current I and the abscissa represents the forward voltage V. P1 in the figure is a characteristic curve of the present embodiment,
P2 is a characteristic curve of the conventional example. As is apparent from the figure, when the voltage is increased in the forward direction, the forward current I is increased and the forward voltage drop is reduced in the present embodiment as compared with the conventional example. .

FIG. 6 is a sectional view of a Schottky barrier diode according to the second embodiment of the present invention.

In the diode of this embodiment, a plurality of trench portions 31 are formed in the N− type semiconductor region between the P + type regions 17 in the first embodiment, and the bottom end portion of each trench portion 31 is further formed. N-epitaxial S around
P + type regions 32 are formed in the i layer 12, respectively.

As a result, the Schottky junction area can be further increased and the forward voltage drop can be greatly reduced.

In the present invention, as the barrier metal electrode 22, a material that forms a barrier against the majority carrier of the semiconductor substrate, such as Al, Mo, Au, Ti, V, etc., is used, which is shown in FIG. Such a one-layer structure may be used, or two or more types of structures made of different types of materials may be used. Here, in the case of two or more types of structures,
Since materials having different barrier heights are used, it has an effect of easily obtaining desired characteristics, particularly forward characteristics, as compared with the one-layer structure.

[0051]

As described in detail above, according to the first aspect of the present invention, since the Schottky junction portion between the first diffusion layers of the second conductivity type has the trench portion having the concave shape, The Schottky junction area is increased by making the flat Schottky junction portion concave. This makes it possible to reduce the forward loss.

According to a second aspect of the invention, in the first aspect of the invention, the second conductivity type second diffusion layer is provided in the first conductivity type semiconductor layer around the bottom end portion of the trench portion. The strength is reduced, and it is possible to reduce the reverse loss. Therefore, it is possible to reduce both the forward loss and the reverse loss, and it is possible to realize a semiconductor device having a lower loss than the conventional technique.

According to the third and fourth inventions, the semiconductor device of the first and second inventions can be manufactured simply and accurately.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a Schottky barrier diode according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the diode of FIG.

FIG. 3 is a continuation of FIG. 2.

FIG. 4 is a continuation of FIG. 3.

FIG. 5 is a graph showing a forward voltage drop characteristic in which the structure of FIGS. 7B and 7C of the conventional example is compared with the structure of FIG. 1 of the present embodiment.

FIG. 6 is a sectional view of a Schottky barrier diode according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional structure diagram of a conventional Schottky barrier diode.

FIG. 8 is a graph showing a reverse leakage current characteristic of a conventional example.

FIG. 9 is a cross-sectional structure diagram of the Schottky barrier diode disclosed in the above-mentioned publication technique.

[Explanation of symbols]

11 N + Si substrate 12 N-Epitaxial Si layer 15 recess 17 P + diffusion layer 19,31 Trench part 21,32 P + diffusion area 22 Barrier metal 23 Ohmic electrode

Claims (4)

(57) [Claims] 1. A semiconductor layer having a first conductivity type and electrodes sandwiching the semiconductor layer, recesses are formed in a plurality of predetermined regions of the semiconductor layer, and second conductivity is provided inside the recesses. A semiconductor device in which a buried layer of the second conductivity type and a first diffusion layer of the second conductivity type are formed around the buried layer, the Schottky junction between the first diffusion layers of the second conductivity type has a concave shape. A semiconductor device having a trench portion to be formed. 2. The semiconductor device according to claim 1, wherein a second diffusion layer of a second conductivity type is provided in the semiconductor layer of the first conductivity type in the vicinity of the bottom end portion of the trench portion. 3. A first step of forming a semiconductor layer of a first conductivity type on a semiconductor substrate, and a plurality of predetermined regions of the semiconductor layer of the first conductivity type are removed to form a plurality of first recesses. And a second step, in which a buried layer having an impurity diffusion rate higher than that of the semiconductor layer of the first conductivity type is formed in each of the first recesses, and then impurity diffusion is performed to perform a second conductivity around each of the first recesses. a third step of forming type semiconductor layer, respectively, a fourth step of forming a second recess in the semiconductor layer region of the first conductivity type between the semiconductor layer mutually the second conductivity type, said first And a fifth step of forming a barrier metal in such a manner that the second recess is filled in the surface of the conductive type semiconductor layer. 4. The sixth step of diffusing impurities into the bottom end of each of the second recesses is performed between the fourth step and the fifth step. Manufacturing method of semiconductor device.