JP3420924B2 - Multiplex conversion method and apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex conversion method and apparatus, and can be used, for example, in a method and apparatus used for multiplex conversion of input data according to a bit width required by a subsequent circuit.

[0002]

2. Description of the Related Art A conventional multi-conversion operation executed when multi-converting 4-bit width input data into 16-bit width output data will be described with reference to FIG.

Incidentally, in FIG. 2, FIG. 2A shows a clock signal given to a device for executing the multiple conversion processing.
FIG. 2B shows the state of the input data latched at the timing synchronized with the clock signal. Further, FIG. 2C shows a frame signal for identifying the head position which falls to the logic "L" level at the head position of the input data.

In the conventional method, 4
When input data having a bit width (FIG. 2B) is input, first, the data value of the input data is sequentially delayed by one clock, and four types of clock shift data D1 to D4 (FIG. 2D).
.. (G)), each of the data values of these four types of clock shift data D1 to D4 is converted into an enable signal (FIG.
(H)) is simultaneously latched and output at the timing when it rises to logic "H", thereby converting it into 16-bit width output data (FIG. 2 (I)).

In this example, the enable signal is
It is necessary to rise to the logic "H" at every 4th clock after the frame signal (FIG. 2C) falls from the logic "H" to the logic "L", which is why it is inputted in one frame. The condition is that the number of bits of input data is a multiple of 4 and a multiple of 16 (for example, 432).

[0006]

However, in the case of such a conventional method, there is no choice for the latch timing given by the enable signal (FIG. 2 (H)) and the frame signal (FIG. 2 (C)) is not selected. It is limited to a single timing obtained from the falling timing.

That is, in the case of the conventional method, the frame phase required by the subsequent stage circuit of the apparatus for executing the multiplex conversion process as its processing timing does not match the frame phase of the input data related to the multiplex conversion. Also the enable signal (see FIG. 2) according to the processing timing of the subsequent circuit.
Since it is not possible to adjust the timing of (H)), it is unavoidable that the processing timing deviates.

Further, in the case of the conventional method, it is essential that there is a multiple relationship between the bit width of input data and the bit width of output data, and the input / output relationship that can be converted is limited.

The present invention has been made in consideration of the above problems, and it is an object of the present invention to propose a multiplex conversion method and apparatus which are superior in flexibility in both operation timing and input / output relation as compared with the prior art.

[0010]

To solve Means for Solving the Problems] Such issues, multiplex conversion how according to the first invention, the input of the N-bit width
Force data is converted to output data of M (M> N) bit width
In the multiple conversion method described above, when an input frame signal indicating the start position of the input data is input, the input frame signal has a reference conversion cycle of the reference conversion period determined from the relationship between the N bit width of the input data and the M bit width of the output data. According to the reference conversion cycle, by determining what phase it is in
A set of delay data to be used for multiplex conversion is set from the delay data string prepared for the number of X (X> M) bits, and the set of delay data is set independently of the input frame signal. Latch at a predetermined latch timing.

The multiplex conversion apparatus according to the second invention is
Output N-bit wide input data with M (M> N) -bit width
In multiplex conversion unit for converting the data, (1) successively delay the input data, X (X> M) bits corresponding to the reference conversion period determined from the relationship between the M-bit width of N-bit wide output data of the input data The shift register stage that outputs a delayed data string for several minutes and (2) determine which phase of the reference conversion cycle the input frame signal indicating the start position of the input data is located, and delay based on the result of the determination. Input frame phase determination means for setting a set of M-bit continuous delay data used for multiplex conversion from the data sequence, and (3)
In the delay data string output from the shift register stage,
Output data output means for latching the data of the delay data set set by the input frame phase determination means at a predetermined latch timing determined independently of the input frame signal and outputting the latch result as output data. Be prepared.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION A multiplex conversion method and apparatus according to the present invention will be described below for each embodiment with reference to the drawings.

(A) First Embodiment In the first embodiment, the case where the input data of 4 bit width is converted into the output data of 16 bit width is used as an example, and the multiple conversion is performed by the multiple conversion method according to the first embodiment. The configuration of the multiplex conversion device to be executed and its operation content will be described.

(A-1) Configuration of the First Embodiment First, the configuration of the multiplex conversion apparatus according to the first embodiment will be described with reference to FIG. This multiplexer includes a shift register stage 1, a frame phase selection circuit 2 and a multiplexer (MUX) 3.

The shift register stage 1 is constructed by connecting seven shift registers D1 to D7 in series. In this shift register stage 1, each shift register D1 to D7 is
The 4-bit wide delay data, which is shifted from 1 clock to 7 clocks, is bundled into one and output as 28-bit wide delay data.

The frame phase selection circuit 2 requires the timing at which a significant level (here, "L" level) appears in the frame signal (hereinafter referred to as "input frame signal") indicating the start position of the input data and the subsequent circuit. It is means for detecting a phase relationship existing between the processing timing and instructing a combination of an appropriate output timing corresponding to the phase relationship and delay data output as output data.

Therefore, the frame phase selection circuit 2 has 4
The enable signals EA to ED of the types are used for detecting the phase relationship, and it is determined which of the four types of enable signals EA to ED the input frame signal matches.

It should be noted that preparing four types of enable signals requires 4 clocks to convert 4-bit width input data into 16-bit width output data, and the "L" level of the input frame signal is This is because it always appears in any of the four states in which the four clocks are one set.

Therefore, these four types of enable signals E
As each of A to ED, a signal in which a logical "H" level period appears in a 4-clock cycle, and the "H" level appearance period is shifted by one clock from each other is used.

When the frame phase selection circuit 2 detects the timing at which the input frame signal becomes a significant level ("L" level) by using these four enable signals EA to ED, the frame phase selection circuit 2 determines the optimum timing according to the timing. The combination of the delay data is instructed to the multiplexer 3 by setting one of the four types of selection signals SA to SD to the “L” level and the other three signals to the “H” level.

The frame phase selection circuit 2 is also provided with a function of giving the head position of the output data, which is determined according to the detected phase relationship, to the subsequent circuit as an output frame signal.

The multiplexer 3 comprises a shift register stage 1
From the 28 signal lines input from, select 16 signal lines corresponding to the set of delay data indicated by the selection signal, and output the delay data input via the 16 signal lines. It is a means for outputting as data.

Here, the selection signal SA corresponds to a total of 16 signal lines from the 27th signal line to the 12th signal line, and the selection signal SB
Corresponds to a total of 16 signal lines from the 15th signal line to the 0th signal line, the selection signal SC corresponds to a total of 16 signal lines from the 19th signal line to the 4th signal line, and the selection signal SD is No. 23 signal line ~
It corresponds to the 8th signal line.

The multiplexer 3 has an enable signal EA.
Is input as the latch timing, and the data value of the selected signal line is latched by the clock input when the enable signal EA is at the “H” level, and output at the next clock. In this embodiment, the latch timing is given by the enable signal EA regardless of the difference in the detected phase relationship.
This is because the multiplexer 3 selects a set of delay data that has been extra delayed by a time corresponding to the phase difference between the input frame signal and the enable signal EA.

(A-2) Operation of First Embodiment Next, the conversion operation in the multiplex conversion apparatus having the above configuration will be described with reference to FIGS.

Incidentally, FIG. 3 shows the case where the phase of the input frame signal matches the phase of the enable signal EA, FIG. 4 shows the case where it matches the phase of the enable signal EB, and FIG. 5 shows the case where it matches the phase of the enable signal EC. , FIG. 6 shows the conversion operation when the phase of the enable signal ED matches.

Here, the conversion operation in each of these cases will be described.

First, the case where the phase of the input frame signal matches the phase of the enable signal EA (FIG. 3) will be described.

At this time, the frame phase selection circuit 2 outputs 4
Among the selection signals SA to SD of the types, only the selection signal SA is set to the “L” level, and the output of the shift registers D1 to D4 that outputs the delayed data delayed by 1 clock to 4 clocks with respect to the input data should be selected. Multiplexer 3
Instruct.

In response to the instruction, the multiplexer 3 receives the data value input from the signal lines (the 27th signal line to the 12th signal line) corresponding to the shift registers D1 to D4, and the enable signal EA is "H". The data is latched at the level timing (in FIG. 3, the input data is "4", "8", "12" ...) And output as 16-bit output data at the next clock timing.

In this case, when the contents of the output data are represented by the numbers of the input data, "0, 1, 2, 3", "4, 5, 6,"
7 "," 8, 9, 10, 11 "...

Next, a case where the phase of the input frame signal matches the phase of the enable signal EB (FIG. 4) will be described.

At this time, the frame phase selection circuit 2 outputs 4
Among the selection signals SA to SD of the types, only the selection signal SB is set to the “L” level, and the output of the shift registers D4 to D7 that outputs delayed data delayed by 4 to 7 clocks with respect to the input data should be selected. Multiplexer 3
Instruct.

In response to the instruction, the multiplexer 3 receives the data value input from the signal lines (15th signal line to 0th signal line) corresponding to the shift registers D4 to D7, and the enable signal EA is "H". It is latched at the level timing (in FIG. 4, the input data is "7", "11", "15" ...) And is output as 16-bit output data at the next clock timing.

Also in this case, when the contents of the output data are represented by the numbers of the input data, "0, 1, 2, 3", "4,5,
"6, 7", "8, 9, 10, 11" ...

When the phase of the input frame signal matches the phase of the enable signal EC (FIG. 5), the operation is as follows.

At this time, the frame phase selection circuit 2 outputs 4
Among the selection signals SA to SD of the types, only the selection signal SC is set to the “L” level, and the output of the shift registers D3 to D6 that outputs delayed data delayed by 3 to 6 clocks with respect to the input data should be selected. Multiplexer 3
Instruct.

In response to the instruction, the multiplexer 3 receives the data value input from the signal lines (the 19th signal line to the 4th signal line) corresponding to the shift registers D3 to D6, and the enable signal EA is "H". It is latched at the level timing (in FIG. 5, the input data is "6", "10", "14" ...) And is output as 16-bit output data at the next clock timing.

Also in this case, when the contents of the output data are represented by the numbers of the input data, "0, 1, 2, 3", "4,5",
"6, 7", "8, 9, 10, 11" ...

When the phase of the input frame signal matches the phase of the enable signal ED (FIG. 6), the operation is as follows.

At this time, the frame phase selection circuit 2 outputs 4
Among the selection signals SA to SD of the types, only the selection signal SD is set to the “L” level, and the output of the shift registers D2 to D5 that outputs the delayed data delayed by 2 to 5 clocks from the input data should be selected. Multiplexer 3
Instruct.

In response to the instruction, the multiplexer 3 receives the data value input from the signal lines (23rd signal line to 8th signal line) corresponding to the shift registers D2 to D5, and the enable signal EA is "H". It is latched at the timing of the level (in FIG. 6, the input data is "5", "9", "13" ...) And is output as 16-bit output data at the next clock timing.

Also in this case, when the contents of the output data are represented by the numbers of the input data, "0, 1, 2, 3", "4,5,
"6, 7", "8, 9, 10, 11" ...

(A-3) Effects of the First Embodiment As described above, according to the multiplex conversion device of the first embodiment, the significant (“H” level) period of the enable signal EA that gives the latch timing is obtained. Can be set to an arbitrary phase independent of the phase of the input frame signal, and the content of the output data output at the latch timing can always be fixed to the same content regardless of the phase relationship of the input frame signal. As a result, it is possible to realize a multiplex conversion method and apparatus having a significantly higher degree of freedom in design than the conventional method.

(B) Second Embodiment In the first embodiment described above, a case has been described in which input data is multiplexed and converted into output data having a bit width that is an integral multiple of the bit width. An example of an embodiment in the case of executing the multiple conversion when such a multiple relationship does not hold will be described.

Here, a case will be described in which input data of 16-bit width is multiplexed and converted to output data of 72-bit width. However, also in this embodiment, the number of bits of data that appears in one frame must be a multiple of both the bit width of input data and the bit width of output data.

(B-1) Configuration of the Second Embodiment The basic configuration of the multiplexer according to the second embodiment is the same as that of the first embodiment. That is, the shift register stage 1 and the frame phase selection circuit 2
And a multiplexer (MUX) 3 as a basic configuration.

Differences in configuration are that the number of stages of shift registers constituting the shift register stage 1 is 13, that 9 types of enable signals EA to EI are used, and that the multiplexer 3 is used for setting latch timing. This is that there are two types of enable signals.

In this embodiment, the enable signal is set to 9
The type needs 4.5 clocks to convert 16-bit wide input data to 72-bit wide output data, but the latch timing is always limited to the rising edge of the clock. In this case, the latch timing must be alternately set to 4 clocks or 5 clocks from the previous latch timing. Therefore, the “L” level of the input frame signal is one of 9 states in which the 9 clocks are set. This is because it will always appear in either.

Therefore, these nine types of enable signals E
As each of A to EI, a signal in which a period of logic "H" level appears in 9 clock cycles and the period of appearance of the "H" level is deviated by 1 clock from each other is used.

In this embodiment, the multiplexer 3 uses the enable signals EA and EE as the two types of enable signals that give the latch timing. This is because the enable signal EE is 4 with respect to the enable signal EA.
This is because it is the clock, and the enable signal EA seen from the enable signal EE is in the relationship of the fifth clock.

(B-2) Operation of the Second Embodiment Next, the conversion operation of the multiplex conversion apparatus having the above configuration will be described with reference to FIGS. 7 to 9. By the way, Fig. 7
8 shows the conversion operation when the phase of the input frame signal matches the phase of the enable signal EA, and FIG. 8 shows the conversion operation when it matches the phase of the enable signal EF. Note that FIG. 9 shows the relationship between the phase of the input frame signal and the combination of delay data selected as output data.

The "L" level portion of the input frame signal indicating the start position of the input data always matches any one of the nine types of enable signals EA to ED, but here, two cases are taken as an example. The basic conversion operation is explained in.

First, the case where the phase of the input frame signal matches the phase of the enable signal EA (FIG. 7) will be described.

At this time, the frame phase selection circuit 2 outputs 9
Among the selection signals SA to SI of the types, only the selection signal SA is set to the “L” level, and the output of the shift registers D5 to D9 that outputs delayed data delayed by 5 to 9 clocks with respect to the input data should be selected. Multiplexer 3
Instruct.

In response to the instruction, the multiplexer 3 receives the data value input from the signal lines corresponding to the shift registers D5 to D9, at the timing when the enable signal EA is at "H" level and the timing when the enable signal EE is at "H". (In FIG. 7, the input data is "9", "13", "1".
8 "," 22 "," 27 "... Timing).

When the enable signal EA is latched as the latch timing, the multiplexer 3 latches only the upper 8 bits of the 16-bit delay data input from the shift register D5. When the enable signal EE is latched as the latch timing, only the lower 8 bits of the 16-bit delay data input from the shift register D9 are latched.

This is because the total number of bits of the 64-bit data latched from another shift register is 72 bits, and the content of the data output as the output data is duplicated or partially duplicated. This is to prevent omission.

In this case, when the contents of the output data are represented by the numbers of the input data, “0, 1, 2, 3, 4 (upper 8 bits)”, “4 (lower 8 bits) 5, 6, 7, 8 ",
"9, 10, 11, 12, 13 (upper 8 bits)",
"13 (lower 8 bits), 14, 15, 16, 17" ...
Becomes

Next, the operation when the phase of the input frame signal matches the phase of the enable signal EF (FIG. 8) will be described.

At this time, the frame phase selection circuit 2 outputs 9
Only the selection signal SF of the selection signals SA to SI of the type is set to the “L” level, and 9 clocks to 13 for input data
The multiplexer 3 is instructed that the outputs of the shift registers D9 to D13 that output delayed data delayed by the clock should be selected.

Upon receipt of the instruction, the multiplexer 3 receives the data value input from the signal lines corresponding to the shift registers D9 to D13, at the timing when the enable signal EA is at "H" level and the timing when the enable signal EE is at "H". (In FIG. 8, the input data is "13", "17", "2".
2 ”,“ 26 ”... Timing).

Also in this case, when the enable signal EA is latched as the latch timing, the multiplexer 3 latches only the upper 8 bits of the 16-bit delay data input from the shift register D9. When the enable signal EE is latched at the latch timing, only the lower 8 bits of the 16-bit delay data input from the shift register D13 are latched.

As a result, when the contents of the output data are expressed by the numbers of the input data, the contents of "0, 1, 2, 3, 4 (upper 8 bits)", "4 (lower 8 bits) 5, 6," , 7,
8 "," 9, 10, 11, 12, 13 (upper 8 bits) "," 13 (lower 8 bits), 14, 15, 16,
17 ”...

The above is the multi-conversion operation when the phase of the input frame signal matches the enable signal EA and when it matches the enable signal EF. However, the phase of the input frame signal is another type of enable signal. The operation in the case of coincidence with is the same, and the content of the data output as the output data is also the same.

The combination of which shift register uses the delay data in each case is as shown in FIG.

(B-3) Effects of the Second Embodiment As described above, also in the case of the multiplex conversion device according to the second embodiment, the enable for giving the latch timing is provided as in the case of the first embodiment. Significance of signal EA ("H" level)
The period can be set to an arbitrary phase independent of the phase of the input frame signal, and the content of the output data output at the latch timing is always fixed to the same content regardless of the phase relationship of the input frame signal. it can.

Moreover, in the case of the second embodiment,
Since the multiple conversion operation in which the bit width of the output data does not have an integer multiple of the bit width of the input data is possible, it is possible to realize a multiple conversion method and apparatus having a higher degree of freedom in design.

(C) Other Embodiments In the above-described first embodiment, the case where the bit width of the input data is 4 bits and the bit width of the output data is 16 bits, and the above-described second embodiment is used. In the embodiment, the case where the bit width of the input data is 16 bits and the bit width of the output data is 72 bits has been described, but the multiple conversion method and apparatus of the present invention can be applied without being limited to such a case.

Further, in the above-mentioned first embodiment,
Although the latch timing is fixed to the enable signal EA, and the latch timing is fixed to the enable signals EA and EE in the above-described second embodiment, the latch timing is not limited to these. When other enable signals are used for the latch timing, the phase relationship selected by the frame phase selection circuit 2 naturally changes.

Further, in the above-mentioned embodiment, the case where the parallel data is converted into the parallel data having a higher multiplicity has been described. However, the present invention is not limited to this, and the case where the serial data is converted into the parallel data is also described. Applicable.

[0072]

As described above, according to the first and second aspects of the present invention, the input frame signal has any phase of the reference conversion cycle determined by the relationship between the bit width of the input data and the bit width of the output data. Based on the determination result, set the delay data set used for multiple conversion from the delay data sequence prepared for the number of stages according to the reference conversion cycle, and set this as the input frame signal. Since the data is latched at a predetermined latch timing determined independently of the above, it is possible to realize a multiple conversion method and apparatus in which the latch timing is not limited by the input frame signal.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an exemplary embodiment of a multiplex conversion device.

FIG. 2 is a timing chart showing a conventional example of a multiplex conversion operation.

FIG. 3 is a timing chart showing an example (part 1) of the multiplex conversion operation according to the first embodiment.

FIG. 4 is a timing chart showing an example (No. 2) of the multiplex conversion operation according to the first embodiment.

FIG. 5 is a timing chart showing an example (No. 3) of the multiplex conversion operation according to the first embodiment.

FIG. 6 is a timing chart showing an example (No. 4) of the multiplex conversion operation according to the first embodiment.

FIG. 7 is a timing chart showing an example (1) of the multiplex conversion operation according to the second embodiment.

FIG. 8 is a timing chart showing an example (No. 2) of the multiplex conversion operation according to the second embodiment.

FIG. 9 is a chart showing a phase relationship of input frame signals and a selection relationship of delay data in the multiplex conversion operation according to the second embodiment.

[Explanation of symbols]

1 ... Shift register stage, 2 ... Frame phase selection circuit, 3
... multiplexer (MUX), D1 to D7 ... shift register.

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03M 9/00 H04J 3/00

Claims (2)

(57) [Claims] 1. N-bit width input data is M (M> N)
In the multiple conversion method to convert to output data of bit width
Then, when an input frame signal indicating the start position of the input data is input, the input frame signal is positioned at any phase of the reference conversion cycle determined by the relationship between the N bit width of the input data and the M bit width of the output data. By determining whether or not to do so, a set of M-bit continuous delay data used for multiple conversion is set from the delay data string prepared for X (X> M) bits according to the reference conversion cycle, A multiplex conversion method, characterized in that the set delay data set is latched at a predetermined latch timing determined independently of an input frame signal. 2. Input data having an N-bit width is M (M> N)
In the multiple conversion device that converts to output data of bit width
Shift to delay the input data sequentially and output a delayed data string of X (X> M) bits corresponding to a reference conversion cycle determined from the relationship between the N- bit width of the input data and the M- bit width of the output data. It is determined which phase of the reference conversion cycle the register stage and the input frame signal indicating the start position of the input data are located in, and based on the result of the determination, M which is used for multiple conversion from the delay data string is selected. Input frame phase determining means for setting a set of delay data having consecutive bits, and a delay data string output from the shift register stage,
Output data output means for latching the data of the delay data set set by the input frame phase determination means at a predetermined latch timing determined independently of the input frame signal and outputting the latch result as output data. A multiplex conversion device comprising: