JP3425580B2 - Test signal generation circuit for semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test signal generating circuit for a semiconductor integrated circuit, and more particularly to a test signal generating circuit for a test by forcibly inputting a test signal to an output terminal. The present invention relates to a technology that does not require a terminal. FIG. 4 shows a conventional test signal input circuit for a semiconductor integrated circuit. The input terminal 25 is connected to the D input of a first flip-flop 26, and the output of this flip-flop is connected to the D input of a second flip-flop 27 and the input of a two-input AND gate 28. The output of the flip-flop 27 is connected to the other input of the two-input AND gate 28. Further, a clock signal from the internal terminal 30 is input to a clock input terminal of the two flip-flops. Input terminal 25
Input the signal to set the test mode through
A clock whose cycle is longer than expected external noise is applied to the internal terminal 30. It is assumed that a low level is normally applied to the input terminal 25 and a high level is applied when setting the test mode. When a high level is applied to the input terminal 25, the Q of the first flip-flop 26
The output changes to high in synchronization with the clock applied from the clock internal terminal 30. The Q output of the first flip-flop 26 is connected to the input of the second flip-flop 27, and the Q output of the second flip-flop 27 changes to a level in synchronization with a clock of the next cycle. The AND of the Q output of flip-flops 26 and 27 is output from internal terminal 12 as a test signal and transmitted to the internal circuit as a test signal. However, in this conventional example, the input terminal 25 is drawn out, and various noises are superimposed on the original signal. In order to prevent malfunction due to the influence of this noise, the test signal from the input terminal 25 must be
By passing through the flip-flops 26 and 27 synchronized with s, the noise of one cycle or less of the clock is ignored, and the influence of the noise is prevented. On the other hand, in this conventional example, one terminal is required exclusively for inputting a test signal, and it takes a maximum of two clocks for the test signal to be transmitted from the input terminal 25 to the internal circuit. There are drawbacks. Next, another conventional example is shown in FIG. This conventional example is proposed in Japanese Patent Laid-Open Publication No. Sho 61-80068, and an internal signal 4s derived inside the semiconductor integrated circuit is connected to a first inversion buffer 1 and a first two-input AND gate 2 is connected. Connected to input. A first output signal of the first inversion buffer 1 is connected to a first output terminal 3 of the semiconductor integrated circuit and to an input of a first two-input AND gate 2. The other input of the first two-input AND gate is connected to the internal input terminal 4. The output signal of the first two-input AND gate 2 is supplied from the first internal output terminal 12 to the internal gate of the semiconductor integrated circuit as a test signal 12s. Normally, the signal is output from the first output terminal 3 to the outside via the first inversion buffer 1. Now, temporarily,
It is assumed that when the internal input terminal 4 is at a high level and a low level is output from the first output terminal 3, a high level is forcibly applied to the first output terminal 3 from the outside as a test signal. At this time, the high level is transmitted to the internal circuit via the first internal output terminal 12 via the AND gate 2. The conventional example has an advantage that it is not necessary to provide a dedicated terminal for applying a test signal. However, when noise is externally superimposed on the signal output from the first output terminal 3 as shown in the time chart of FIG. 6, a waveform like a signal 15 appears and falls below the threshold voltage 14, and the first The output of the 2-input AND gate 2 has a drawback that an erroneous test signal is output as in the output waveform 17. A test circuit for improving test efficiency is essential. On the other hand, in order to reduce costs, it is necessary to reduce the number of terminals as much as possible. However, as described above, the conventional test signal input circuit requires a dedicated terminal, and has a disadvantage of malfunction due to noise. In the above-described conventional test signal input circuit of a semiconductor integrated circuit, a test circuit for improving test efficiency is indispensable. On the other hand, it is desirable that the number of terminals be as small as possible for cost reduction. However, as described above, the conventional test signal input circuit has a disadvantage that a dedicated terminal is required and a malfunction occurs due to noise. Accordingly, it is an object of the present invention to provide a test signal input circuit of a semiconductor integrated circuit which does not require a dedicated terminal for inputting a test signal by forcibly inputting a test signal to an output terminal. Another object is to reduce malfunction due to noise. A test signal generating circuit for a semiconductor integrated circuit according to the present invention has a first internal input terminal connected to a first inversion buffer and a first two-input AND gate,
The output of the first inversion buffer is connected to a first output terminal and the first output terminal.
Connected to the other input of the two-input AND gate of
Next, the second internal input terminal is connected to the input of the second inverting buffer and the input of the first two-input NOR gate, and the output of the second inverting buffer is connected to the second output terminal and the first two inputs. The output of the first two-input AND gate is connected to the other input of the NOR gate, and the output of the first two-input NOR gate is connected to the input of the second two-input AND gate . , The output of the second two-input AND gate is connected to the first internal output terminal, and the output of the third two-input AND gate is connected to the second internal output terminal. Connected, then the second 2
The first internal input terminal and the first input terminal are connected to the input of an input NOR gate.
Inverted connected its output to the output of the buffer is connected to the third two-input AND gates, further, a fourth two-input AND of the inverting buffer each of the second internal input terminal and the second to the input of the gate output And its output is the third 2
The input AND gate is connected to the other input. Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of an embodiment of a test signal generation circuit of the present invention. In the present embodiment, the first internal input terminal 4 is connected to the inputs of the first inversion buffer 1 and the first two-input AND gate 2, and the output of the first inversion buffer is connected to the first output terminal 3 The first two
The second internal input terminal 10, which is connected to the other input of the input AND gate 2, is connected to the inputs of the second inverting buffer 5 and the first two-input NOR gate 6, and the second inverting buffer Is connected to a second output terminal 9 and the other input of the first two-input NOR gate 6. The output of the first two-input AND gate 2 and the output of the two-input NOR gate 6 are the second two. The output of the second two-input AND gate, which is connected to the input of the input AND gate 11, is connected to the first internal output terminal 12. The first internal signal 4s outputs a low level from the first output terminal 3 through the first inversion buffer 1.
Here, when a high level is forcibly applied to the first output terminal 3 from the outside, the output of the first AND gate 2 is at a high level because the first internal input terminal 4 is at a high level. On the other hand, the second internal signal 10 s outputs a high level from the second output terminal 9 through the second inversion buffer 5. Here, when a low level is forcibly applied to the second output terminal 9 from the outside, the second internal input terminal 10 is at a low level.
The output of the first NOR gate 6 goes high. Since the outputs of the first AND gate 2 and the NOR gate 6 both go high, the output of the second two-input AND gate 11 goes high, and the test signal 1
It is supplied to the internal circuit as 2s. As described above, in this embodiment, the test signal is not transmitted to the internal circuit unless a test signal is applied to both the first output terminal 3 and the second output terminal 9. Therefore, even if noise is superimposed on only one of the first and second output terminals 3 and 9, no erroneous test signal is generated. However, in general, external noise is often superimposed on all terminals. FIG. 2 shows a time chart in such a case. FIG. 2 shows an output waveform 15 from the first output terminal 3 and an output waveform 1 from the second output terminal 9.
3 shows a case where noise is superimposed. When the noise rises and exceeds the threshold voltage 14, a high-level pulse appears in the output waveform 17 of the first two-input AND gate 2. However, since the second output terminal 9 is originally at the high level, the output of the first two-input NOR gate 6 does not change, so that the output waveform 18 of the second two-input AND gate 11 remains at the low level. . Here, it is assumed that the threshold voltages of the first two-input AND gate 2 and the two-input NOR gate 6 are the same. On the other hand, when the noise falls and the threshold voltage 14 is interrupted, a high-level pulse appears in the output waveform 16 of the first two-input NOR gate 6. However, since the first output terminal 3 is originally at a low level, the first two-input AND gate 2
Does not change, and the output waveform 18 of the second two-input AND gate 11 remains unchanged at a low level. As described above, according to the present invention, even if noise is superimposed on the output terminals 3 and 9 individually or simultaneously, no erroneous test signal is generated. FIG. 3 shows another embodiment of the present invention. In this embodiment, the first internal input terminal 4 is connected to the inputs of the first inversion buffer 1 and the first two-input AND gate 2, and the output of the first inversion buffer 1 is connected to the first output terminal 3 and the first output terminal 3. The second internal input terminal 10 is connected to the other input of the first two-input AND gate 2, and then to the input of the second inverting buffer 5 and the input of the first two-input NOR gate 6. The output of the second inverting buffer 5 is connected to a second output terminal 9 and the other input of the first two-input NOR gate 6, and the output of the first two-input AND gate 2 is the second
Is connected to the input of a two input AND gate 11, the first output of the two-input NOR gate 6 is connected to the input of a second two-input AND gate 11, the second two-input AND gates 11 Is connected to the first internal output terminal 12, and the output of the third two-input AND gate 23 is connected to the second internal output terminal 24.
And said first internal input terminal 4 to the input of a two input NOR gate 19 first connected to its output to the output of the inverting buffer 1 is connected to the input of a third two-input AND gate 23, further, the 4 and a second internal input terminal 10 and a second inverting buffer 5, respectively.
And the output is connected to the other input of the third two-input AND gate 23. When the first output terminal 3 outputs a low level and the second output terminal 9 outputs a high level, the high level is applied to the first output terminal 3 from the outside and the second output terminal 9 is forcibly applied. , A test signal can be obtained at the first internal output terminal 12. Conversely, when the first output terminal 3 outputs a high level and the second output terminal 9 outputs a low level,
By forcibly applying a low level to the first output terminal 3 and a high level to the second output terminal 9 from the outside, a test signal can be obtained at the third internal output terminal 24. Since each operation is the same as that of the first embodiment, detailed description is omitted. In the present embodiment, two test signals can be obtained using the two output terminals 3 and 9 without increasing the number of terminals. As described above, the test signal input circuit of the present invention does not require a dedicated terminal for inputting a test signal by forcibly inputting a test signal to two normal output terminals. In addition, malfunction due to external noise can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a test circuit diagram of a semiconductor integrated circuit showing a configuration of a first embodiment of the present invention. FIG. 2 is a time chart waveform diagram of an embodiment of the selection delay circuit according to the first embodiment. FIG. 3 is a test circuit diagram of a semiconductor integrated circuit according to a second embodiment. FIG. 4 is a test signal input circuit diagram of a conventional semiconductor integrated circuit. FIG. 5 is a test signal input circuit diagram of a semiconductor integrated circuit showing another conventional embodiment. FIG. 6 is a time chart in a test signal input circuit of another conventional semiconductor integrated circuit. [Description of Signs] 1 First inversion buffer 2 First two-input AND gate 3 First output terminal 4 First internal input terminal 5 Second inversion buffer 6 First two-input NOR gate 9 Second output Terminal 10 Second internal input terminal 11 Second two-input AND gate 12 First internal output terminal 13 Output waveform 14 from second output terminal 9 Threshold voltage 15 Output waveform 16 from first output terminal 3 Output waveform 17 of first 2-input NOR gate 6 Output waveform 18 of first 2-input AND gate 2 Output waveform 19 of second 2-input AND gate 11 Second 2-input NOR gate 22 Fourth 2-input AND gate 23 Third two-input AND gate 24 Second internal output terminal 25 Input terminals 26 and 27 Flip-flop 30 Internal terminal 4s Internal signal 10s Internal signal 12s Test signal 30s Clock Signal

Claims (1)

(57) Claims 1. A first internal input terminal is connected to a first inversion buffer and a first two-input AND gate, and an output of the first inversion buffer is a first output. Terminal and the other input of the first two-input AND gate.
Are connected to the input of the second inversion buffer and the first 2
The output of the first two-input AND gate is connected to the input of the input NOR gate, and the output of the second inverting buffer is connected to the second output terminal and the other input of the first two-input NOR gate. It is connected to the input of a second two-input aND gates, an output of said first two-input NOR gate before
The output of the second two-input AND gate is connected to the first internal output terminal, and the output of the third two-input AND gate is connected to the second internal AND terminal.
Of being connected to the internal output terminal, then connected to its output to an output of the first internal input terminal to the input of a second 2-input NOR gate and the first inverting buffer coupled to the third two-input AND gates Further, a second internal input terminal and an output of a second inverting buffer are connected to the inputs of the fourth two-input AND gate, respectively, and the output is connected to the other input of the third two-input AND gate. And a test signal generation circuit for a semiconductor integrated circuit.