JP3425855B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction field effect transistor (hereinafter referred to as "F") formed on a GaAs substrate which is a high electron mobility transistor which has been put into practical use in recent years.
Called ET. ) Device structure, especially InGaA for power
The present invention relates to an element structure of sFET.

[0002]

2. Description of the Related Art InGaA formed on a GaAs substrate
As shown in FIG. 9, the sFET includes a GaAs substrate 1, an undoped GaAs layer 2 as a buffer layer, an undoped InGaAs layer 6 as a channel layer, an undoped AlGaAs layer 5 as a spacer layer, and a Si-doped AlGaAs layer 4 as a donor supply layer. , Si as cap layer
Doped GaAs layer 9, source electrode 10, drain electrode 1
1 and the gate electrode 13. This was initially put into practical use as a transistor for low noise. In recent years, proposals have been made for practical use of this InGaAs FET as a power element.

When this InGaAs FET is used for power, for the purpose of enhancing its current driving capability, as shown in FIG. 10, AlGaAs doped with Si as donor supply layers above and below the undoped InGaAs layer 6, respectively.
The layer 4 is provided. The AlGaAs layer 4 generally has an Al mixed crystal ratio of 0.2 to 0.3. Incidentally, 3 is undoped AlGa as a buffer layer interposed between the GaAs layer 2 as a buffer layer and the AlGaAs layer 4.
It is an As layer. The characteristic of this crystal structure is that the InGaAs layer 6 is provided with AlGaAs layers 4 above and below the InGaAs layer 6.
To supply electrons (which are called two-dimensional electrons because these electrons are two-dimensionally distributed in the InGaAs layer 6). Therefore, according to this structure, one layer of AlG is formed on the InGaAs layer 4 shown in FIG.
Compared to the structure in which electrons are supplied only from the aAs supply layer 4, the InGa has an electron concentration of about 3 to 5 × 10 ¹² cm ⁻² .
There are electrons in the As layer 6. Thus, this structure enhances the current driving capability of the transistor and can be used as a power transistor rather than a small signal application such as low noise.

One of the requirements for the performance of this power transistor is that it has a high reverse gate / drain breakdown voltage. Normally, a reverse breakdown voltage of 10 V or higher is required for stable operation as a power transistor. Therefore, the AlGaAs layer 4 in contact with the gate electrode 13 has a donor concentration gradient of InG.
The device is devised so that it is lowered from the aAs layer 6 toward the gate electrode 13. As a method different from this structure, as shown in FIG.
As shown in FIG. 1, the planar structure of Si is used for the donor structure of the AlGaAs layer 5 ′ as the donor supply layer in contact with the gate electrode 13, and the A in contact with the gate electrode 13 is used.
It has been proposed that the 1GaAs layer 5 ′ is intentionally made undoped without doping impurities. In FIG. 11, the broken line shows the state of planar doping of Si.

Further, as shown in FIG. 12, the InGaAs FET described in Japanese Patent Laid-Open No. 3-70145 has an undoped AlGaAs layer 5 as a spacer formed on a Si-doped AlGaAs layer 4 as a donor supply layer.
An undoped InGaAs layer 6 as a channel layer formed on the AlGaAs layer 5 and the InG
It has a non-doped GaAs layer 14 as a barrier layer formed on the aAs layer 6 and a gate electrode 13 formed on this GaAs layer 14. In this figure,
Portions equivalent to those in FIGS. 9 and 10 are denoted by the same reference numerals. In this structure, it is the undoped GaAs layer 14 that exists between the gate electrode 13 and the InGaAs layer 6, and this GaAs layer 14 is not a donor supply layer but a barrier layer for the gate Schottky junction potential. .

In this publication, as an example, 1 × 1 is provided between the gate electrode 13 and the InGaAs layer 6.
A case where a Si-doped GaAs layer of 0 ¹⁷ cm ^-3 is used is also shown, but with such a donor concentration, the two-dimensional electron concentration in the InGaAs layer 6 cannot be sufficiently increased, and this Si-doped GaAs layer is It is used as a barrier layer.

Therefore, the InG disclosed in this publication is
In aAsFET, InG as a channel layer
The two-dimensional electrons supplied to the aAs layer are the InGaAs
Since it is supplied only from the AlGaAs layer as a donor supply layer below the layer, the two-dimensional electron concentration is usually 2 × 10 ¹²
The upper limit is / cm ² . This means that the InGaAs FET disclosed in this publication can be used as a transistor for small signals such as low noise, but cannot be used as a transistor for power as shown in FIGS.

[0008]

Problems to be Solved by the Invention I shown in FIGS.
In the nGaAs FET, the gate electrode 13 is formed on the AlGaAs layers 4 and 5 ', and the AlGaAs layer is used as the gate Schottky layer and I
It also functions as a donor layer that supplies electrons to the nGaAs layer 6.

The AlGaAs layers 4 and 5'are formed by supplying Al and Ga as group III elements simultaneously with As of the group V element during crystal growth. This crystal growth is generally performed by a molecular beam epitaxy method (MBE) or a metal organic chemical vapor deposition method (MOCVD). In this AlGaAs layer, when the Al composition ratio approaches 0.3 (Al composition x is 0.3), when a donor is added to the crystal, an impurity center called a DX center is formed and added. It is known to make the concentration of electrons supplied by a donor unstable, and there is a problem in that crystal growth must always be done with great care.

The gate electrode 13 is made of this AlGaA.
It is in contact with the s layers 4 and 5'by a Schottky junction. Al
Since the element itself is very easily oxidized and the element is a constituent element of a crystal forming a Schottky junction, many surface levels are formed in AlGaAs immediately below the gate electrode 13, and moreover, this surface level Since the formation process is currently unknown, the formation of this surface state is inevitably unstable, which makes the Schottky characteristics of the gate electrode and AlGaAs unstable. ing. In fact, in the InGaAs FET formed on the GaAs substrate formed by the conventional technique, A is used as the gate electrode.
When 1 is used, the ideal factor (n value) indicating the quality of the Schottky characteristic is about 2 to 4. This is because the ideal factor (n value) of MESFET in which Al gate electrode is formed in normal GaAs is 1 to 1.
Compared with being around 3, it will be a considerably large value. Further, in the InGaAs FET formed on the GaAs substrate formed by the conventional technique, even if a slight reverse gate current flows through the gate electrode, the pinch-off voltage of the transistor fluctuates slightly before and after the gate current, but is unstable. There is a problem that is causing the operation.

In the FET disclosed in the above publication, the above

As described in "Prior Art", there is a problem that it is not suitable for power.

In view of the above problems, the present invention provides a semiconductor device having a high electron mobility capable of stabilizing the gate Schottky characteristic while sufficiently maintaining the element characteristic of the FET for power use. With the goal.

[0013]

The semiconductor device of the present invention comprises:
An AlGaAs layer , which is a first semiconductor layer to which an n-type impurity is added, formed on a GaAs substrate, and has a stronger electron affinity than the first semiconductor layer formed on the first semiconductor layer and has a forbidden band. The width is small and the electron density is 3 × 10 ¹²
an InGaAs layer which is a second semiconductor layer having a cm ⁻² or more ,
A non-doped GaA that is a third semiconductor layer added with an n-type impurity having an electron affinity lower than that of the second semiconductor layer formed on the second semiconductor layer and having a large forbidden band width.
The layer s-layer is planarly doped, the source electrode and the drain electrode facing the third semiconductor layer formed on the third semiconductor layer at an ohmic junction, the third semiconductor layer and the shot. And a gate electrode facing each other at a key junction .

The semiconductor device of the present invention is preferably the third one.
The planar doping of the semiconductor layer is 1 × 10 ¹² cm ^-2
Not less than 4 × 10 ¹² cm ^{-2 and} less n-type impurities
It

The semiconductor device of the present invention is preferably the first
The semiconductor layer of Si is doped with Si as an n-type impurity,
2 is an electron supply layer for supplying electrons to the second semiconductor layer.

The semiconductor device of the present invention is preferably the first
Is a Si-doped AlGaAs layer,
The n-type impurity of the third semiconductor layer is Si.

[0017]

The operation of the present invention will be described below. Conventionally, G
In a GaAs power FET using an InGaAs layer as a channel layer as an FET formed on an aAs substrate, AlGaA using Si-doped AlGaAs as a donor supply layer on both sides of the InGaAs layer is used.
The combination of s / InGaAs / AlGaAs has been developed from the viewpoint of donor supply. In spite of that, the present invention uses GaAs / InGaAs /
It was created by studying the combination of AlGaAs, repeatedly examining whether GaAs can supply a donor that can withstand practical use as a power FET, and demonstrating that a sufficient donor can be supplied. Therefore, in the present invention, a GaAs layer is used as a donor supply layer for a power FET. Furthermore, GaAs is Al
A stable Schottky junction is formed with respect to the gate electrode as compared with GaAs, and stable operation as an FET can be realized. Also, GaAs has a gate breakdown voltage of AlG
It is advantageous over aAs.

The semiconductor device of the present invention has a first semiconductor layer and a third semiconductor layer as donor supply layers on both sides of the second semiconductor layer, and the third semiconductor layer is a gate electrode and a Schottky. Since it is a GaAs layer to which the n-type impurity is added, the donor of the second semiconductor layer can be present at a concentration necessary for power,
Further, in principle, the contact between the gate electrode and the AlGaAs layer as the donor layer, which is very unstable as a crystal, is eliminated at the Schottky junction, and stable gate Schottky characteristics can be obtained on the GaAs layer. It is possible to obtain a semiconductor device which operates stably while maintaining the characteristics as an element.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device of the present invention will be described below.

Reference Example FIG. 1 is a sectional view schematically showing a semiconductor device. Ga
Undoped Ga as a buffer layer on the As substrate 1
As layer 2, undoped AlGaAs as buffer layer
Layer 3, Si-doped AlGaAs layer 4 as a donor supply layer, undoped AlGaAs layer 5 as a spacer layer,
An undoped InGaAs layer 6 as a channel layer, an undoped GaAs layer 7 as a spacer layer, and a Si-doped GaAs layer 8 as a donor supply layer are laminated in this order. Si on the GaAs layer 8 as a cap layer
A source electrode 10 and a drain electrode 11 are laminated on the doped GaAs layer 9 and the cap layer 9, respectively. A gate electrode 13 is laminated on the GaAs layer 8.

The manufacture of this semiconductor device will be described below with reference to FIGS. The GaAs substrate 1 is degreased with an organic solvent such as acetone. After that, the GaAs substrate 1 is loaded into an MBE apparatus (an apparatus that carries out a molecular beam epitaxy method), and the substrate is subjected to 50
Baking is performed at 0 ° C. for 30 minutes to remove the moisture adhering to the surface of the GaAs substrate 1. Then, the temperature of the GaAs substrate 1 is raised to 570 ° C., and the undoped GaAs layer 2 is heated to 5 ° C.
The AlGaAs layer 3 is successively grown to a thickness of 00 nm to a thickness of 200 nm. These are formed as a buffer layer.

After that, further, on the AlGaAs layer 3, an AlGaAs layer 4 doped with Si of 2 × 10 ¹⁸ cm ^-3 as a donor supply layer with a thickness of 20 nm and an undoped AlGaAs layer 5 as a spacer layer are further formed. At 2 nm,
It grows in this order. An undoped InGaAs layer 6 having a thickness of 10 is formed as a channel layer on the AlGaAs layer 4.
nm, and undoped G as a spacer layer thereon
The aAs layer 7 has a thickness of 2 nm, and the GaAs layer 8 doped with Si at 1 × 10 ¹⁸ cm ⁻³ has a thickness of 20 n as a donor supply layer.
m is 2 × 10 ¹⁸ cm for forming the cap layer.
^{A -3} doped GaAs layer 9 is grown in this order with a thickness of 50 nm (see FIG. 2). Here, the composition ratio of Al in AlGaAs is 0.25 (Al composition x is 0.25),
The composition ratio of In in InGaAs is 0.2 (In composition y
Is 0.2).

Thereafter, the elements are separated through a normal photo-etching step, and further, a normal photo-etching and alloying steps are performed, followed by Au / Ni as shown in FIG.
A source electrode 10 and a drain electrode 11 made of / Au are formed.

Thereafter, as shown in FIG. 4, a resist pattern 12 is formed, and the GaAs layers 8 and 9 are etched using this resist pattern as an etching mask. At this time, the value of the current flowing between the source electrode 10 and the drain electrode 11 is measured to measure the end of the etching.
The value of the current when V is applied is set to 300 to 600 mA / mm.

After that, the G exposed by this etching
A gate electrode 13 is formed on the aAs layer 8 as shown in FIG. The material of the gate electrode 13 is Al, T
i / Pt / Au or the like is used. After that, lift-off with an organic solvent is performed to obtain a transistor having a structure in which the gate electrode 13 shown in FIG. 1 is dug (so-called recess gate structure).

In the transistor of the first embodiment, 3 × 10 ¹² c which is necessary as a current driving capability for power is used.
It became possible to stabilize the gate Schottky characteristics while maintaining the channel electron concentration of m ^-1 or more. In particular, in this transistor, a gate reverse breakdown voltage of -14 V and an ideal factor (n) value of the gate electrode of 1.1 were obtained at a drain current density of 300 mA / mm.

FIG. 6 shows the relationship between the donor concentration in the GaAs layer 8 serving as the donor supply layer and the two-dimensional electron concentration in the InGaAs layer 6 serving as the channel layer of the transistor of this structure.
Shown in. To obtain this, at the stage of crystal growth up to the structure shown in FIG. 7, that is, at the stage of crystal growth up to the GaAs layer 8 in FIG. 2, the donor concentration N of the GaAs layer 8 and its layer thickness d are shown in Table 1 below. A sample was used.

[0029]

[Table 1]

The characteristics of FIG. 6 show the results of experimentally confirming the two-dimensional electron concentration by Hall measurement using the crystal structure of FIG. From this FIG. 6, the electron density required as a power transistor is 3 × 10 ¹² c
In order to obtain m ⁻² or more, GaA as a donor supply layer is used.
It is understood that the donor concentration of the s layer 8 needs to be 5 × 10 ¹⁷ cm ⁻³ or more. The upper limit of the donor concentration can be determined by considering the upper limit of the donor addition to GaAs, and can be set to 2.5 × 10 ¹⁸ cm ⁻³ . The electron concentration of the InGaAs layer 6 is 4 × 10 ¹² cm
It can be set to ^-2 , and the current driving force can be large.

[0031] (Embodiment) FIG. 8 is a cross-sectional view illustrating the shape condition of the present invention schematically. In FIG. 8, the same parts as those in the reference example are denoted by the same reference numerals. In place of the GaAs layer 8 as the donor supply layer in the reference example , Si was added at 1 × 10 ¹² cm ⁻²
Then, the undoped GaAs layer 8'is planarly doped to form a donor supply layer. In FIG. 8, the situation of planar doping is indicated by a broken line. The donor supply layer can be formed by using a planar doping method instead of the growth step of the GaAs layer 8 in the reference example .

In this structure, since the gate electrode 13 forms a Schottky junction with the undoped GaAs layer 8 ', the junction characteristics are different from those in the case where the Schottky junction is formed with AlGaAs. As in the case of No. 1, it is possible to obtain a power transistor which is stable and has stable characteristics. Further, this configuration can increase the gate reverse withstand voltage as compared with the first embodiment, and is suitable for applications in which a higher withstand voltage is required.

In this embodiment, the planar doping amount of Si is 1 × 10 ¹² cm ⁻² , but it is possible to increase Si to at least 4 × 10 ¹² cm ⁻² . Doping is possible up to the upper limit of donor addition, and the current driving force can be further increased.

In the above-described embodiment, the example in which Si is used as the donor has been described, but it is also possible to use an atom of group IV, which is in the same group as Si, such as Ge. Also,
In the above-described embodiment, an example of a so-called recess gate structure has been described.
The gate layer 13 and the source electrode 1 are omitted by omitting the cap layer 9.
1 and the drain electrode 12 may be formed on the GaAs layer 8.

[0035]

In the semiconductor device of the present invention, the gate electrode is G
Since it has a Schottky junction with aAs, the gate Schottky characteristic can be stabilized, and the GaAs layer which is joined to the gate electrode is doped with n-type impurities and serves a great role as an electron supply layer for the channel, so that a current Channel electron concentration required as driving force, eg 3
X10 ¹² cm ^-2 can be maintained and further 4x10 ¹²
It can be set to cm ^−2, and a stabilized power transistor with excellent high frequency characteristics can be provided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view schematically illustrating the configuration of a semiconductor device .

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a semiconductor device .

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a semiconductor device .

FIG. 4 is a cross-sectional view illustrating the manufacturing process of the semiconductor device .

FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor device .

FIG. 6 is a Ga of electron concentration in a channel layer of a semiconductor device .
It is a figure explaining the donor concentration dependence characteristic in an As layer.

FIG. 7 is a cross-sectional view illustrating the configuration of a hole measuring sample of a semiconductor device .

The form status of the implementation of the semiconductor device of the present invention; FIG is a cross-sectional view illustrating schematically.

FIG. 9 is a cross-sectional view schematically illustrating the configuration of a conventional semiconductor device.

FIG. 10 is a cross-sectional view schematically illustrating another configuration of the conventional semiconductor device.

FIG. 11 is a sectional view schematically explaining another configuration of the conventional semiconductor device.

FIG. 12 is a cross-sectional view schematically illustrating still another configuration of the conventional semiconductor device.

[Explanation of symbols]

1 GaAs Substrate 2 GaAs Layer 3 Undoped AlGaAs Layer 4 Si Doped AlGaAs Layer 5 Undoped AlGaAs Layer 6 Undoped InGaAs Layer 7 Undoped GaAs Layer 8 Si Doped GaAs Layer 8'Si Doped GaAs Layer 9 Si Doped GaAS Layer 10 Source Electrode 11 Drain Electrode 12 Photoresist 13 Gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 29/778 H01L 29/812

Claims (4)

(57) [Claims] 1. An AlGaAs layer , which is a first semiconductor layer to which an n-type impurity is added, formed on a GaAs substrate, and has an electron affinity higher than those of the first semiconductor layer formed on the first semiconductor layer. Strong and narrow band gap,
Which is the second semiconductor layer with a degree of 3 × 10 ¹² cm ^-2 or more
The GaAs layer and the non-doped GaA which is the third semiconductor layer added with the n-type impurity having the electron affinity weaker than that of the second semiconductor layer formed on the second semiconductor layer and having a large band gap.
The layer s-layer is planarly doped, the source electrode and the drain electrode facing the third semiconductor layer formed on the third semiconductor layer in ohmic contact, the third semiconductor layer and the shot. A semiconductor device having a gate electrode facing each other at a key junction. 2. A planar dopin for the third semiconductor layer .
Grayed is, 1 × 10 ¹² cm ^-2 or more, the semiconductor device according to claim 1, characterized in that it contains 4 × 10 ¹² cm ^-2 or less of n-type impurity. Wherein said first semiconductor layer is doped with Si as an n-type impurity, according to claim 1 or 2, characterized in that an electron supply layer supplying electrons to the second semiconductor layer Semiconductor device. Wherein a AlGaAs layer, wherein the first semiconductor layer is doped with Si, the semiconductor device according to claim 1 or 2 n-type impurity of the third semiconductor layer is characterized in that it is a Si .