JP3425916B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a circuit for precharging bit lines.

[0002]

2. Description of the Related Art Dynamic Random Access Memory (DRAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Onl (Electrically Erasable Programmable Read Onl)
y Memory: EEPROM, Static Random Access Memory: SRA
In the semiconductor memory device using M) or the like, by controlling the memory cell via the word line and connecting to the bit line, the external data input from the write amplifier is transmitted via the bit line during data writing. When writing data to a memory cell and reading data, the data stored in the memory cell is read to a bit line and output to the outside via a sense amplifier.In this case, before reading or writing, the bit line is previously written. Power supply voltage Vcc or 1 /
After precharging to 2 Vcc, the memory cell is connected to a bit line to output data or write external data. The reason why the precharge is necessary in this way is that the memory cell is composed of a flip-flop, and if the potential of the bit line is floating, the content of the memory cell may be rewritten due to power supply noise or the like. Therefore, the occurrence of such a phenomenon is prevented by setting the bit line to a predetermined potential in advance and connecting the memory cells in this state to perform reading or writing. In general, the precharge potential of the bit line is precharged to the power supply potential in SRAM, 1/2 of the power supply potential in DRAM, and the read potential of about 1 V in ROM. In addition, at this time, in order to enable high-speed reading and prevent erroneous reading and erroneous writing, an equalizing operation is performed in which the bit lines are set to the same potential simultaneously with precharging. In this case, if the bit line has a defect that leaks between the bit line and a wiring adjacent to the bit line, for example, a wiring for grounding or a semiconductor substrate due to a manufacturing defect or the like, a current is supplied with respect to the ground potential every precharge. Since it flows, the precharge current increases. In particular, when precharging is performed even during the standby period, the power consumption due to the precharging increases, so that in the case of a portable device or the like, the period of use of the battery becomes short, which is a serious problem. In the following description, the SRAM
Taking as an example, a conventional technique for such a semiconductor memory device will be described.

FIG. 23 is a diagram showing a configuration of a cell array in a semiconductor memory device of Conventional Example 1, and FIG. 24 is a diagram showing a configuration of a word line activation signal and bit line precharge signal generating circuit of Conventional Example 1. 25 is a diagram showing operation waveforms in the semiconductor memory device of Conventional Example 1. FIG. As shown in FIG. 23, the semiconductor memory device of the conventional example 1 has memory cells 2 ₀ , 2 ₁ , 2 ₂ , ... _, 2 _i that form each column between each bit line pair 1 a and 1 b. In addition, the precharge transistors 3a and 3b are provided between the bit lines 1a and 1b and the power supply, and the equalizing transistor 3c is provided between the bit lines 1a and 1b. Precharge transistor 3 for each bit line pair
The bit line precharge signal / PBL is supplied to the a and 3b and the equalizing transistor 3c for each section including a plurality of columns. Further, the word lines 4 ₀ , 4 ₁ , 4 ₂ , ... _, 4 _{i of} each row (row) are connected to the memory cells 2 ₀ , 2 ₁ , 2 ₂ , ... _, 2 _i of each column. Further, each bit line pair 1a, 1b is
Each column of Y switch _{7 0,} 7 1, _..., via the _{7 j,} in parallel to each section, via the data lines 8a, the 8b, is connected to the write amplifier 9 and the sense amplifier 10.

Next, referring to FIG. 23, the semiconductor device of Conventional Example 1
The outline of the operation in the body storage device will be described. Each memory cell
Le 2₀, 2₁, 2_Two、…_，Two_iRespectively
Connected to the word line signals WL0, WL1, WL2
..., depending on the high level of WLi
One row is selected and bit line selection signals Y0, Y1,
..., Y switch depending on the high level of Yj
7₀, 7₁、…_，7 _jOne of them is on
The corresponding one column is selected,
One memory cell at the intersection of the selected row and column
The write amplifier is ready for writing or reading.
Data Din is input via 9 and sense amplifier 10
The data Dout is output via. At this time, a bit
Line precharge signal / PBL (/ is a low active signal
No. (Below omitted)
Channel MOS (Metal Oxide Semiconductor) transistor
Pre-charge transistor consisting of
Each bit line pair 1a, 1b via the transistors 3a, 3b.
The power supply voltage (Vcc) is supplied to the
Equalize transistor consisting of PMOS
Both bit lines 1a and 1b are equalized by the switch 3c.
Will be raised.

A word line activation signal and bit line precharge signal generation circuit in a conventional semiconductor memory device includes inverters INV1 and INV2, as shown in FIG.
It consists of a NAND circuit NAND1 and an inverter I
A signal obtained by inverting the chip enable signal / CE via NV1 and the one-shot pulse OS are supplied to the NAND circuit NAN.
A NAND operation is performed in D1 to obtain a word line activation signal / X.
E is generated and the NAND circuit NAN is generated by the inverter INV2.
The output signal of D1 is inverted to generate the bit line precharge signal / PBL.

Next, referring to FIGS. 23 and 25, in the semiconductor memory device of Conventional Example 1, for example, a Y switch YS is used.
One bit line / BL1 of a bit line pair connected to W1
In the following, operation waveforms of respective parts when there is a leak path between the ground potential and the resistor RL will be described. An address transition detector (A) (not shown) is generated by changing the active-standby of the chip enable signal / CE and the change of the address Add.
One-shot pulse OS is generated by TD).
As a result, the word line activation signal generating circuit shown in FIG. 24 outputs the word line activation signal / XE = / (OS * C
E) (* indicates an AND operation, which will be omitted hereinafter) occurs. Now, if the word line WLi is selected,
The word line WLi is selected when the chip enable signal / CE and the one-shot pulse OS are active. At this time, the bit line precharge signal generation circuit shown in FIG. 24 outputs the bit line precharge signal / PBL = OS.
* CE is generated, whereby precharge is performed during the low level period of the one-shot pulse OS during the active period of the chip enable signal / CE, the remaining period is held and reading is performed, and again during the standby period. Precharge is performed. At this time, in any case, in the defective bit line having a leak, after the precharge period is completed, it is discharged rapidly and the potential is lowered. In particular, since the leaking bit line is also precharged during the standby period, the precharge current (standby current: ISB) in the standby period increases as indicated by a.

The reason why the bit line is precharged during the standby period is to prevent the bit line from floating during the standby period.
In other words, being electrically floating is equivalent to connecting to the power supply via a capacitance, so if the power supply potential fluctuates, the high frequency component superimposed on the power supply is also transmitted to the floating bit line. Therefore, the potential of the bit line also changes. For example, if the fluctuation speed of the power supply is high in the rising direction and low in the falling direction and continues to fluctuate periodically, the potential of the floating bit line is gradually boosted, but Is
Since the PMOS transistor of the bit line precharge signal line is connected, it is not boosted above the threshold voltage | Vtp | of this PMOS transistor, but the potential may rise to Vcc + | Vtp | due to high frequency components. This indicates that the bit line and the drain of the transistor connected to the bit line may exceed the maximum power supply voltage, which is a problem in device reliability. On the other hand, on the contrary, assuming that the fluctuation speed of the power supply is low in the rising direction and high in the falling direction, the potential of the bit line gradually decreases, and finally the N-channel MOS transistor of the memory cell ( Hereinafter, the threshold value of the transfer transistor, which is made up of abbreviated as NMOS), becomes equal to or lower than the threshold value, the word line is turned on, and the held data may be rewritten. As described above, if there is no means for fixing the potential of the bit line to the power source potential or the ground potential, the potential of the floating bit line is Vcc + |
Since there is a risk of transition to Vtp | or −Vtn (Vtn is the threshold voltage of NMOS), which is a problem in terms of device reliability and data retention, conventionally, precharging of the bit line during the standby period is performed. I was going to do it. In the case of SRAM, a high resistance or a PMOS transistor is connected to the power supply potential side of the flip-flop,
The charge stored in the bit line (precharged) is N
Since the ability to supply charges to the bit line by the PMOS transistor or the high resistance is lower than the ability to extract it by the MOS transistor, it is usually precharged to the power supply potential.

FIG. 26 is a diagram showing the configuration of a cell array in the semiconductor memory device of the second conventional example, and FIG. 27 is a diagram showing operation waveforms in the semiconductor memory device of the second conventional example. In the semiconductor memory device of Conventional Example 2, as shown in FIG. 26, fuses F0, F1, ..., Fj are provided in the supply line of the bit line precharge signal / PBL for each bit line pair in the cell array of Conventional Example 1. Is different. In the semiconductor memory device of the conventional example 2, when it is detected that there is a leak in the bit line / BL1 at the manufacturing stage, the semiconductor memory device is inserted into the supply line of the bit line precharge signal / PBL connected to the bit line. Fuse F1
Is cut with a laser beam, and this line has a high resistance R
It is fixed at a high level by connecting to the power supply potential via S.

Next, referring to FIGS. 26 and 27, in the semiconductor memory device of the second conventional example, for example, a Y switch YSW is used.
One of the bit line pairs connected to 1 / BL1
In the following, operation waveforms of respective parts when there is a leak from the ground potential through the resistor RL will be described. The operation of the normal bit line in which there is no bit line leakage in the case of the conventional example 2 is not different from that of the conventional example 1 shown in FIG.
In a defective bit line having a leak path, the bit line is not precharged regardless of the active period and the standby period. Therefore, the leaked bit line is fixed to the ground potential as shown in FIG. The line is
Since the cell is in a high-level read state when a word is selected and is in a floating state during standby, the standby current does not increase by precharging a defective bit line having a leak.

FIG. 28 is a diagram showing a configuration of a bit line precharge signal generating circuit in the semiconductor memory device of the conventional example 3, and FIG. 29 is a diagram showing operation waveforms in the semiconductor memory device of the conventional example 3. The configuration of the cell array in the semiconductor memory device of the conventional example 3 is similar to that of the conventional example 1 shown in FIG. 23, but of the bit line precharge signal generation circuit for supplying the precharge signal to each bit line pair. The composition is different. As shown in FIG. 29, the bit line precharge signal generation circuit in the case of the conventional example 3 has a NOR circuit NOR.
1 and an inverter INV3, the NOR circuit NOR1 performs a NOR operation on the one-shot pulse OS and the chip enable signal / CE, and the output is inverted by the inverter INV3, whereby the bit line precharge is performed. Generate signal / PBL. Next, FIG.
With reference to, the operation waveforms of the respective parts in the semiconductor memory device of Conventional Example 3 will be described. In the case of Conventional Example 3, the selected word line W
The operation up to the selection of the normal cell in Li is the same as in the case of Conventional Example 1. However, in Conventional Example 3, the timing of the bit line precharge signal is the same as that in Conventional Example 1.
Unlike the above case, the precharge is not performed in the standby period. As described above, since the precharge is turned off during the standby period, the non-defective bit line having no leakage is in a floating state as shown in b. On the other hand, the defective bit line having a leak is precharged during the active period of the chip enable signal / CE, but after the end of the precharge period, the potential sharply decreases to the ground potential as shown in c. Therefore, normal reading cannot be performed. However, since the precharge is not performed during the standby period, the standby current does not increase due to the presence of the defective bit line having the leak.

FIG. 30 shows the structure of a cell array in the semiconductor memory device of Conventional Example 4, and shows a simplified structure of the semiconductor memory device including a plurality of sub-arrays.
In Conventional Example 4, as shown in FIG. 30, the cell array is divided into a plurality of sub-arrays including sections Sect1 to Sect4, and precharge transistors QA and QB are provided for each pair of bit line pairs in each sub-array.
And an equalize transistor QC are provided to connect each bit line to a power source for precharging for each sub-array according to the bit line precharge signals / φP1 to / φP4, and to correspond to each bit line pair. , MCi are provided, and reading is performed by selecting via the word line of each corresponding row.

Next, the operation of the semiconductor memory device of Conventional Example 4 will be described with reference to FIG. The operation of each sub-array in the case of the conventional example 4 is the same as in the case of the conventional example 1 shown in FIG. 23. In the initial period of the active period, the bit line is precharged and then the selected word line is set to the high level. By setting the level to read the data of the memory cell to the bit line, and during the standby period, the bit line precharge signals / φP1 to / φP4 are set to the low level to precharge all the bit lines of all the sub-arrays. Prevent it from floating.
At this time, for example, in the sub-array of the section Sect4, if the bit line / BL1 has a leak path through the resistor RL, the leaking bit line is also precharged during the standby period, so that the standby current increases.

[0013]

In the semiconductor memory device shown in Conventional Example 1, all bit line pairs are precharged during the standby period. Therefore, the bit line (/ BL1) having a leak (RL) is also precharged during this period, and the standby current ISB increases. In LPSRAM (Low Power SRAM) used for mobile phones,
In order to save power consumption, it is required to reduce current consumption as much as possible during standby. Therefore, an extremely slight increase in standby current is also a big problem.
When the semiconductor memory device is actually used, the memory cell including the leaking bit line is not used for data storage and is replaced with a redundant memory cell (not shown). Data is read and written to. As described above, the semiconductor device having the redundancy means can be made to function as a non-defective product even if a part thereof has a defect. On the other hand, in the semiconductor memory device shown in the second conventional example, a fuse element is provided in the supply line of the bit line precharge signal / PBL, and the fuse of the defective bit line having the leak is selectively cut off. Since the defective bit line having the leak is not precharged during the standby period, the standby current can be prevented from increasing. The conventional example 2 is also similar to the conventional example 1,
A defective bit line having a leak is replaced with a redundant memory cell, and thus functions as a good product. However, it is difficult to miniaturize the size of the fuse element with respect to the design standard of the bit line pitch, so that there is a problem that the chip size increases significantly and the layout becomes difficult. Further, in the semiconductor memory device shown in Conventional Example 3, all the bit lines are left floating without precharging during the standby period.
The defective bit line with the leak is lowered to the ground potential, but the presence of the defective bit line with the leak does not increase the standby current. However, since the bit line is in a floating state, the bit line may be at or above the power supply voltage Vcc or below the ground potential due to fluctuations in the power supply potential, leading to malfunction of memory cells or destruction of stored data. There is a problem of fear. Further, in the semiconductor memory device shown in Conventional Example 4, all the bit line pairs are precharged in all the sub-arrays during the standby period. Therefore, if there is a leak in the bit line, this bit line is also precharged during this period, which causes a problem that the standby current increases. Further, as in the case of the conventional example 2, a fuse is provided in the path for supplying the precharge signal so that the sub-array Sec having the leak is present.
By preventing the precharge signal from being supplied at t4, the sub-array Sect4 does not perform the precharge operation, and the standby current can be prevented from flowing. However, since the sub-array Sect4 is not precharged, the sub-array Sect4 must be replaced with the redundant memory cell array in units of sub-arrays having a large storage capacity, resulting in poor replacement efficiency. For example, if the redundant memory cell array has only one sub-block, if two sub-blocks have a defect, they cannot be replaced and must be discarded as a defective product. If the redundant memory cell array is provided for a large number of sub-blocks, even if the two sub-blocks have a defect, they can be replaced, but the area of the redundant memory cell array becomes large and the chip size increases, High chip cost.

The present invention has been made in view of the above circumstances, and in a semiconductor memory device that requires precharging of bit lines, the presence of leaking bit lines may increase the standby current. Not again
Provided is a semiconductor memory device in which there is no risk of operation failure or destruction of memory cells due to fluctuations in power supply potential, and further, in order to avoid such problems, increase in chip size and difficulty in layout do not occur. The purpose is to do.

[0015]

In order to solve the above-mentioned problems, the invention according to claim 1 comprises a plurality of data holding memory cells, and a plurality of bit lines in which the plurality of memory cells are arranged on a bit line. , A plurality of word lines that select the memory cells of each bit line in the row direction and control connection to the bit lines during the operation period, and precharge each bit line to a predetermined potential before reading data from the memory cells And a precharge unit for precharging means for each bit line, which is connected to a bit line according to a potential fixing signal only in a standby period and fixes the potential of the bit line to a ground potential or a power supply potential. It is characterized in that a potential fixing means is provided.

According to a second aspect of the present invention, a plurality of data holding memory cells, a plurality of bit lines in which the plurality of memory cells are arranged on a bit line, and a memory cell of each bit line during an operation period. A cell array having a plurality of word lines for controlling connection to bit lines by selecting in the row direction, and dividing the cell array into a plurality of sub-arrays, each sub-array being connected to each bit line according to a potential fixing signal. A semiconductor memory device comprising: a potential fixing means for fixing the potential of a line to a ground potential or a power supply potential; and a precharge means for precharging each bit line to a predetermined potential before reading data from the memory cell. Therefore, in all normal sub-arrays, all the bit lines are precharged by the precharge means in the standby period, and While the constant means inoperative,
A sub-array including a bit line having a leak path is characterized in that the potential fixing means is operated only in the standby period without precharging by the precharging means during the standby period.

The invention according to claim 3 relates to the semiconductor memory device according to claim 1 or 2, wherein the potential fixing means comprises a dummy memory cell provided for each bit line, and each dummy memory cell. Is connected to the corresponding bit line by a dummy word line during the standby period,
The dummy memory cell is configured to hold and fix the potential of the bit line.

The invention according to claim 4 relates to the semiconductor memory device according to claim 1 or 2, wherein the potential fixing means comprises two dummy memory cells provided for each of a plurality of bit line pairs. In the standby period, the two dummy memory cells are connected to each one of the two bit lines forming the corresponding bit line pair by the dummy word line, and the potential of each of the bit line pairs is increased. Is held and fixed by the two dummy memory cells.

The fifth aspect of the present invention relates to the semiconductor memory device according to any one of the first to fourth aspects, wherein the potential fixing means is a full CMOS flip-flop.

[0020]

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

According to the structure of the present invention, a plurality of data holding memory cells, a plurality of bit lines in which a plurality of the memory cells are arranged on the bit lines, and a memory cell of each bit line in the row direction in the operation period. In a semiconductor memory device including a plurality of word lines that are selectively connected to bit lines and a precharge unit that precharges each bit line to a predetermined potential before reading data from the memory cell, each bit line For each of them, the potential fixing means connected to the bit line in accordance with the potential fixing signal in the standby period to fix the potential of the bit line to the potential of the leak path is provided.
During the standby period, all the bit lines are not precharged, so even if there is a bit line with a leak path, the standby current does not increase during this period, and each bit line has a potential of a dummy memory cell. Is fixed, there is no possibility of causing malfunction of memory cells or destruction of stored data due to fluctuations in power supply potential or the like.

Further, according to another structure of the present invention, a plurality of data holding memory cells, a plurality of bit lines in which the plurality of memory cells are arranged on a bit line, and a memory cell of each bit line during an operation period. A cell array having a plurality of word lines connected to the bit lines by selecting in the row direction, and each sub array is connected to each bit line according to a potential fixing signal. In a semiconductor memory device comprising a potential fixing means for fixing the potential of the above to the potential held therein and a precharge means for precharging each bit line to a predetermined potential before reading data from the memory cell, In all sub-arrays, all the bit lines are precharged by the precharge means in the standby period and the potential is fixed. In the sub-array including the bit lines having the leak path with the stages inoperative, the potential fixing means is configured to operate without precharging during the standby period by the precharge means. In the sub-array including the bit line included therein, the precharge is not performed in the standby period, so that the standby current of the semiconductor memory device does not increase, and the precharge current (operating current) in the active period is a bit having a leak path. Although the number of sub-arrays including lines increases, it is possible to suppress an increase in operating current in a short cycle as compared with a semiconductor memory device in which all non-selected sub-arrays are not precharged.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using the embodiments. In the following description, an example of such a semiconductor memory device will be described by taking an SRAM as an example. First Embodiment FIG. 1 is a block diagram showing the overall configuration of a semiconductor memory device to which the present invention is applied, and FIG. 2 is a diagram showing the configuration of a cell array in the semiconductor memory device according to the first embodiment of the present invention. 3 is a diagram showing a configuration example of a memory cell in this embodiment, FIG. 4 is a diagram showing a configuration example of a Y switch in this embodiment, and FIG. 5 is a configuration example of a one-shot pulse generation circuit in this embodiment. 7 is a diagram showing a configuration example of a word line activation signal generation circuit in the present embodiment, FIG.
FIG. 8 is a diagram showing a configuration example of a dummy word generation circuit in this embodiment, FIG. 8 is a diagram showing a configuration example of a word line selection circuit in this embodiment, and FIG. 9 is a diagram showing an operation of the semiconductor memory device of this embodiment. It is a waveform diagram shown. As shown in FIG. 1, a semiconductor memory device to which the present invention is applied has a memory cell array 10
1, the address buffer 102, the one-shot pulse generation circuit 103, the word line activation signal generation circuit 104, the word line selection circuit 105, the dummy word generation circuit 106, the bit line selection circuit 107, Y It has a schematic configuration including a switch 108, a write amplifier / sense amplifier 109, an input / output circuit 110, a bit line precharge signal generation circuit 111, and a precharge circuit 112.

Next, the operation of the semiconductor memory device to which the present invention is applied will be described with reference to FIG. The memory cell array 101 has, for each bit line pair BL, / BL, memory cells corresponding to the word lines WL0, WL1, ..., WLi and dummy memory cells corresponding to the dummy word line DW. . The address buffer 102 receives addresses A0 to An, row addresses AX0 to AXm, and column addresses AY0 according to the address input Add.
Generate AYk. One-shot pulse generation circuit 10
3 is an address A0-An or a chip enable signal /
The one-shot pulse OS is generated according to the change of CE. The word line activation signal generation circuit 104 generates the word line activation signal / XE according to the one-shot pulse OS and the chip enable signal / CE. When receiving the word line activation signal / XE, the word line selection circuit 105 generates the word line signals WL0, WL1, ..., WLi according to the row addresses AX0 to AXm. The dummy word generation circuit 106 includes a one-shot pulse OS,
A dummy word line signal DW is generated according to the chip enable signal / CE. The bit line selection circuit 107 generates bit line selection signals Y0 to Yj according to the column addresses AY0 to AYk. The Y switch 108 corresponds to the bit line pair B corresponding to the bit line selection signals Y0 to Yj.
L and / BL are connected to the write amplifier / sense amplifier 109. The write amplifier / sense amplifier 109 amplifies the input data and outputs it to the data lines DL, / DL at the time of writing, and detects the potential of the bit line pair BL, / BL at the time of reading and outputs it to the data lines DL, / DL. Generate output data. The input / output circuit 110 supplies the input data Din to the data lines DL and / DL and generates the output signal Dout from the signals on the data lines DL and / DL. The bit line precharge signal generation circuit 111 includes a one-shot pulse OS,
A bit line precharge signal / PBL is generated according to the chip enable signal / CE. Precharge circuit 11
2 supplies a precharge potential to each bit line pair in response to the bit line precharge signal / PBL.

As shown in FIG. 2, the cell array in the semiconductor integrated circuit device of the first embodiment has a bit line pair 1 in each row.
Memory cells 2 forming each column between a and 1b
₀ , 2 ₁ , 2 ₂ , ... _, 2 _i are provided, and
Corresponding to both bit lines BL and / BL, precharge transistors 3a and 3b are provided between the bit lines BL and / BL, and both bit lines 1 and
An equalizing transistor 3c is provided between a and 1b. Precharge transistor 3 of bit line pair in each row
The bit line precharge signal / PBL is supplied to the a and 3b and the equalizing transistor 3c for each section including a plurality of columns. This section corresponds to a range in which one word line (or sub word line) can be selected, for example. In addition, the memory cell ₂ 0 of each column,
2 _{1, 2} 2, _..., the _{2 i,} word lines _{4 0,} 4 _1, 4 2 of each row (row), _{..., 4 i} are connected. In addition, the dummy memory cells ₅₀ ,
A dummy word line 6 is connected to 5 ₁ , ... _, 5 _j . Further, the bit line pair 1a, 1b in each row is connected in parallel for each section via the Y switches 7 ₀ , 7 ₁ , ... _, 7 _j in each column, through the data lines 8a, 8b, and then through the write amplifier 9 and the sense amplifier. Connected to 10.

Next, referring to FIG. 2, the semiconductor memory of this example will be described.
The outline of the function of the storage device will be described. In the following,
Mainly describes functions related to reading.
It Each memory cell 2₀, 2₁, 2_Two、…_，Two
_iAre word line signals WL0, W connected to each
One of L1, WL2, ..., WLi goes high
To select the corresponding row and
Any of the line selection signals Y0, Y1, ..., Yj is high level.
Y switch 7₀, 7 ₁、…
_，7_jOne of them is turned on and the corresponding one
Column is selected, at the intersection of the selected row and column,
A state in which one memory cell performs writing or reading
And the data Din is input via the write amplifier 9.
The data Dout is output via the sense amplifier 10.
Be done. At this time, the bit line precharge signal / PBL
Depending on the level, the precharge transistor consisting of PMOS
Each bit line pair 1a, 1b via the transistors 3a, 3b.
Is supplied with the power supply voltage Vcc to perform precharge.
Together with the equalizing transistor 3 consisting of PMOS
Both bit lines BL and / BL are equalized to the same potential by c.
Is ized. The above operation is the same as the conventional example 1 shown in FIG.
The same as in the case of, but with the dummy word line signal D
When W becomes high level, the dummy memory cell
5₀, 5₁、…_，5_jEach bit line pair
The difference is that they are connected in between.

As shown in FIG. 3, the memory cell in this example has a full CMOS flip-flop composed of PMOS Q1 and Q2 and NMOS Q3 and Q4, and an NMOS Q.
It has a configuration in which it is connected to the bit lines BL and / BL via a transfer transistor made of Q5 and Q5. PM
OSQ1, NMOSQ3 and PMOSQ2, NMOSQ
4 is connected in series between the power supply Vcc and the ground potential, the respective gates are connected in parallel, and the connection points of the respective drains are mutually connected to the gates on the other side, so that either If the drain of becomes high level, the other drain becomes low level,
It operates as a flip-flop and changes the state of the connection point of each drain to the transfer transistors NMOSQ5 and Q6 when the word line WL is driven to the high level.
To the bit lines BL and / BL. The dummy memory cell is similar in structure to the memory cell shown in FIG. 3, except that the gate of the transfer transistor is connected to the dummy word line DW.

As shown in FIG. 4, the Y switch in this example has PMOS Q7, NMOS Q8 and PMOS Q9.
, And NMOS Q10 by connecting their drains and sources in parallel, and controlling the gates of the NMOS and PMOS in parallel by the bit line selection signal Yj and its inverted signal via INV4.
The BL and the data lines DL and / DL are bidirectionally connected.

The one-shot pulse generation circuit in this example has a plurality of ATD circuits 11 and N, as shown in FIG.
It has a configuration including a PMOS Q12 with respect to the MOS Q11. Each ATD circuit 11 has a plurality of inverters INV5, inverters INV6, INV7, and NAND circuits NAND2, NAND3, NAND4, and inputs addresses A0, A1, ..., An and a chip enable signal / CE, respectively. As a result, a NAND operation of the input signal and a signal obtained by inverting the input signal by the inverter INV7 is performed by the NAND circuit NAND3, a signal obtained by delaying the input signal by the inverter INV5 and a signal obtained by inverting the input signal by the inverter INV6. The NAND operation of
Depending on the result of the NAND circuit NAND2, NMO
By controlling the on / off of the SQ11, the output from the power supply through the PMOS Q12 is controlled to generate the one-shot pulse OS which becomes the low level for a certain period of time after the change of the input signal and thereafter becomes the high level. .

As shown in FIG. 6, the word line activation signal generating circuit in this example has an inverter INV8 and a NAND circuit NAND5, a one-shot pulse OS, and
A NAND operation is performed with the signal obtained by inverting the chip enable signal / CE to generate the word line activation signal / XE.

The dummy word generation circuit in this example is
As shown in FIG. 7, it has a NAND circuit NAND6 and an inverter INV9, and inverts the signal of the NAND operation result of the one-shot pulse OS and the chip enable signal / CE to generate the dummy word line signal DW.

The word line selection circuit in this example is shown in FIG.
As shown in FIG. 3, the address decoder 12 has a plurality of NAND circuits NAND7 and a plurality of NOR circuits NOR1. The address decoder 12 has row addresses AX0 to AX.
The NAND circuit calculates the combination of the decoded signals, and the NOR circuit performs the NOR operation on the operation result signal and the word line activation signal / XE to obtain the word line signal W.
L0, WL1, ..., WLi are generated.

The configuration of the bit line precharge signal generation circuit in this example is similar to that of the conventional example 3 shown in FIG.

Next, the operation of the semiconductor memory device of this example will be described with reference to FIGS. At the time of reading, the chip enable signal / CE becomes low level (active period), and if the address Add changes in this state, the AT in the one-shot pulse generation circuit 103 is changed.
The D circuit detects this and a one-shot pulse OS is generated. As a result, the bit line precharge signal generation circuit 104 generates the bit line precharge signal / PBL, the bit line pair is charged to the level of the power supply voltage, and then the word line signal of the selected word line WLi is generated. The high level causes the data in the selected memory cell to be read out to the corresponding bit line. Next, when the chip enable signal / CE becomes high level (standby period), the one-shot pulse generation circuit 10
In 3, the one-shot pulse OS is generated again by detecting this. At this time, in the bit line precharge signal generation circuit 111, since the chip enable signal / CE is at high level, the bit line precharge signal / PBL remains fixed at high level,
No precharge is performed on the bit line pair. Also,
The selected word line WLi is reset and fixed at the low level. On the other hand, at this time, the dummy word line D
Since W becomes high level, high level or low level is given to both bit lines forming the bit line pair depending on the state of the dummy cell. At this time, if a leak path RL exists on one of the bit lines / BL1 as shown in FIG. 2, the bit line / BL1 is suddenly brought to the ground potential as shown by A in FIG. 9 after the end of precharge. As the dummy word line is selected during the standby period, the bit lines BL1, / BL
The dummy cell connected to 1 is stable in a state in which a low level is written on the bit line / BL1 side and a high level is written on the opposite bit line BL side. If the bit line BL1 has a leak path, this relationship is reversed.

As described above, in the semiconductor memory device of this example, all the bit line pairs are not precharged during the standby period. Therefore, even if there is a bit line having a leak path, the precharge current is generated during this period. It does not increase. Further, each bit line pair is not precharged either in a normal state or in the case where any one of the bit lines has a leak path. Instead of being precharged, a constant potential is applied by the dummy cell, so that during the standby period. The bit line never floats. Note that FIG.
In B, the bit line may be in a floating state in the middle of the normal cell selection state and the dummy cell selection state during the standby period, but this period is short, so there is little problem. The above example
The case where the bit line is precharged to the power supply potential and there is a path leaking to the ground potential has been described. However, in the present embodiment, the bit line is precharged to the ground potential, and the power supply potential, or ½ of the power supply potential It can also be applied to the case where there is a path leaking to the electric potential or the electric potential of 1V. Also, there is a high possibility that a leak path will occur between adjacent wiring,
At the stage of designing the mask layout, it is possible to predict which potential will leak. If the potential after the leak occurs is expected to be half the power supply voltage or 1 V, the power supply voltage of the flip-flop connected to the dummy word line is changed to the bit line after the leak occurs. May be set to a potential at which the voltage converges, that is, a potential at the leak path destination. The term "adjacent wiring" includes not only the case where the wiring is adjacent to the front, rear, left, and right in the same layer but also the case where the wiring is adjacent to the upper / lower layer wiring or the semiconductor substrate.

◇ Second embodiment FIG. 10 shows a semiconductor memory device according to the second embodiment of the present invention.
11 is a diagram showing the configuration of the cell array in FIG.
It is a figure which shows the structural example of the dummy memory cell in an example.
The cell array in the semiconductor integrated circuit device of this example is shown in FIG.
As shown in 10, between the bit line pairs 1a and 1b in each row,
Memory cells 2 that make up each column₀, 2₁，
Two_Two、…_，Two_iBoth bit lines B
Corresponding to L and / BL, precharge transistor between power supply
Between the bit lines 1a and 1b having the transistors 3a and 3b.
And has an equalizing transistor 3c. Of each line
Bit line pair precharge transistors 3a, 3b and
The equalizing transistor 3c has a plurality of columns.
Bit line precharge signal / PB for each section
L is supplied. In addition, the memory cell 2 of each column₀, 2
₁, 2_Two、…_，Two_iThere is a word for each row
Line 4₀, 4₁, 4_Two、…_，Four_iIs connected
The bit line pairs 1a and 1b in each row are the Y switches in each column.
7₀, 7₁、…_，7 _jThrough the section
In parallel with and through the data lines 8a and 8b, a write amplifier
9 and the sense amplifier 10. Configuration above
Is similar to the case of the first embodiment shown in FIG.
The dummy memory cells in each row are both bit lines in each row.
Two dummy memory cells 5 connected to 1a and 1b_0a
And 5_0b, 5 _1aAnd 5_1b,…_，5_jaAnd 5_jbOr
The points that are commonly connected to the dummy word line 6
Is different.

The configuration of the Y switch, the one-shot pulse generation circuit, the word line activation signal generation circuit, the dummy word generation circuit, the word line selection circuit, and the bit line precharge signal generation circuit in this example is shown in FIG. This is similar to the case of the first embodiment. As shown in FIG. 11, the dummy memory cell 5 in this example has PMOSs Q13 and Q14.
And a full CMOS flip-flop composed of NMOS Q15 and Q16 is connected to the bit line BL via a transfer transistor composed of NMOS Q17, and a PMOS
It has a configuration in which a full CMOS flip-flop consisting of Q18 and Q19 and NMOS Q20 and Q21 is connected to the bit line / BL via a transfer transistor consisting of NMOS Q22. Each of the full CMOS flip-flops is connected between the power supply Vcc and the ground potential, and when the dummy word line DW is driven to the high level, the transfer transistors NMOSQ17, Q2.
The circuit state determined according to the potential input via 2 is held. Then, when the dummy word line DW is driven to the high level next time, the transfer transistor NMOS
Via Q17 and Q22, the held potential is changed to the bit line B
Output to L, / BL.

Next, the operation of the semiconductor memory device of this example will be described with reference to FIGS. In the semiconductor memory device of this example, the operation when there is no leak in the bit line is the same as in the case of the first embodiment shown in FIG. Now, as shown in FIG. 10, both bit lines BL1, / B
If the leak paths RLA and RAB are present in L1, respectively, the bit lines BL1 and / BL1 are drastically lowered to the ground potential after the end of precharge, so that the dummy word line DW is selected during the standby period. , The dummy cells 5 _1a and 5 _1b connected to the bit lines BL1 and / BL1 respectively have bit lines BL1 and / 1
It becomes stable when a low level is written on the BL1 side.
If a leak path exists on one of the bit lines BL1 and / BL1, the dummy cell connected to the bit line having the leak path has a low level on the bit line side, but on the bit line on the side where the leak path does not exist. The connected dummy cell becomes stable in a state where the bit line side is written with a level determined by the immediately preceding bit line potential.

As described above, in the semiconductor memory device of this example, all the bit line pairs are not precharged during the standby period. Therefore, even if there is a bit line having a leak path, the precharge current is generated during this period. It does not increase. In addition, each bit line pair is not normally precharged, whether it is normal, either one has a leak path, or both bit lines have a leak path. Since the constant potential is applied, the bit line does not float during the standby period.

Third Embodiment FIG. 12 is a diagram showing the configuration of a cell array in a semiconductor memory device according to the third embodiment of the present invention, and FIG. 13 is a diagram showing a configuration example of a section decoder circuit according to the present embodiment.
FIG. 14 is a diagram showing a configuration example of a word line activation signal generation circuit in this embodiment, FIG. 15 is a diagram showing a configuration example of a dummy word generation circuit in this embodiment, and FIG. 16 is a semiconductor as a reference example. FIG. 17 is a diagram showing a structure of a cell array in the memory device, FIG. 17 is a diagram showing a timing chart (A) for explaining a difference in operation between this embodiment and the reference example, and FIG. 18 is operation between this embodiment and the reference example. FIG. 19 is a timing chart (B) for explaining the difference between FIG. 19 and FIG. 19 for explaining the change in the bit line potential between the bit line pair having a leak path and the bit line pair having no leak path in the case of the reference example. Figure,
FIG. 20 is a diagram for explaining a change in bit line potential between a bit line pair having a leak path and a bit line pair having no leak path in the case of the present embodiment, and FIG. 22 is a diagram showing a timing chart (C) for explaining the difference in the operation of FIG. 22, and FIG. 22 is a diagram showing a timing chart (D) for explaining the difference in the operation between the present embodiment and the reference example.

As shown in FIG. 12, the cell array in the semiconductor integrated circuit device of this example is formed by dividing the cell array into a plurality of sub-arrays including sections Sect1 to Sect4, and pre-processing the bit line pairs in a plurality of columns in each sub-array. Charge transistors QA and QB and an equalize transistor QC are provided, and each sub-array is provided in accordance with bit line precharge signals / φP1 to / φP4.
Each bit line is connected to a power source to be precharged, and a plurality of memory cells MC0, MC1, ..., MCi are provided corresponding to each bit line pair, and selected via the word line of each corresponding row. Thus, the configuration for reading is the same as that of the conventional example 4 shown in FIG.
A dummy memory cell DMC is provided between each bit line pair for each sub-array of t1 to Sect4, and each dummy memory cell is connected via dummy word lines DW1 to DW4.
The bit line precharge signal generation circuits 16 _{1 to} 16 are connected to the dummy word generation circuits 15 ₁ to 15 _{4 and} are connected to the sub-arrays of the sections Sect ₁ to Sect ₄ respectively.
₄ are provided, and bit line precharge signals / φP1 to //
The difference is that φP4 is supplied.

Bit line precharge signal generation circuit 16
_{1-16 4} each, the NAND circuit NAND 8,
NAND9, inverters INV10, INV11,
When the fuse F is not cut, a high level output is generated from the power supply Vcc through the fuse F, and when the fuse F is cut, it is grounded through the resistor RS. By connecting to the electric potential, a low level output is generated. Then, the NAND operation of the signal obtained by inverting this output by the inverter INV10 and the chip enable signal / CE is performed by the NAND circuit NAND.
8 and outputs the logical product signal of the section selection signals SS1 to SS4 and the word line activation signal XE to the inverter IN.
The signal inverted through V11 and the NAND circuit NAND8
The NAND circuit NAND9 performs a NAND operation with the output of the bit line precharge signal to generate bit line precharge signals / φP1 to / φP4.

As shown in FIG. 13, the section decoder circuit in this example has inverters INV12 to INV.
It is composed of V17 and NAND circuits NAND10 to NAND13. FIG. 13 corresponds to the case where the cell array is divided into four sections, and two column addresses AYk, AYk + 1 and an inverter INV12,
From the respective inversion signals via INV13, 2 ² = 4 by NAND circuits NAND10 to NAND13.
In addition to creating individual signals, the inverter INV14-
The section selection signals SS1 to SS4 and / SS1 to / SS4 for the four sections are generated by creating respective inverted signals via the INV17.

As shown in FIG. 14, the word line activation signal generating circuit in this example comprises a NAND circuit NAND14, which performs a NAND operation on the one-shot pulse OS and the section selection signal SSs to execute the word operation for each section. Generate a line activation signal / XEs.

The dummy word generation circuit in this example is
As shown in FIG. 15, the NAND circuit NAND15 has an NAND circuit NAND15 and an inverter INV18.
Then, the NAND operation of the one-shot pulse OS and the inverted section selection signal / SSs is performed, and the operation result is inverted by the inverter INV18 to generate the dummy word line selection signal DWs for each section.

The operation of the semiconductor memory device of this example will be described below with reference to FIGS. In this example, a bit line having a leak path is not included, for example,
In the sub-arrays of sections Sect1 to Sect3,
Bit line precharge signal generation circuit 16 _{1 to} 16 ₃
In the above, since the fuse F is not cut, the operation of each sub-array becomes the same as that of the conventional example 1 shown in FIG. 23, and each bit line precharge signal generation circuit 16
Based on the operation of _{1 to} 16 ₃ during the standby period,
The bit line precharge signals / φP1 to / φP3 become low level, and precharge is performed in the sub-arrays of the sections Sect1 to Sect3. In the selected sub-array in the active period, the word line is selected and the data is read after the pre-charge is performed by the one-shot pulse. On the other hand, at the manufacturing stage, for example, the bit line of the sub-array of the section Sect4 /
When it is detected that BL1 has a leak path through the resistor RL, a relief program circuit (not shown)
Thereby replacing a defective bit line in the spare bit line is connected to the subarray sections Sect4, the bit line precharge signal generation circuit 16 ₄ is cut using a fuse F laser light. by this,
The subarray sections Sect4, as in the first embodiment, based on the operation of the bit line precharge signal generation circuit 16 _4, during the standby period, the bit line precharge signal / FaiP4 high illustrated in FIG. 2 It becomes the level, and only the sub-array of section Sect4 does not precharge the bit line.
In the dummy word generating circuit 15 _4, signal of the dummy word line DW4 becomes high level, the dummy memory cell is operational. At the end of the standby period, after the precharge is performed by the one-shot pulse, the word line is selected and the data is read.

As described above, in the semiconductor memory device of this example, the bit line precharge signal generating circuit is provided in each section so that the subarray having the leak path and the normal subarray can be operated separately. By providing the bit line precharge signal, the bit line is precharged during the standby period and the dummy memory cells are not operated when there is no leak path in the bit line. When this is detected, the fuse F is cut in the bit line precharge signal generation circuit to stop the supply of the bit line precharge signal, precharge is not performed during the standby period, and the dummy memory cell Is working.

On the other hand, without distinguishing between a sub-array having a leak path and a normal sub-array, all the non-selected sub-arrays in the standby period are not precharged with the bit lines, and the dummy memory cells are used. While fixing the potential of the bit line, during the active period,
It is possible to consider a semiconductor memory device in which the bit lines of all the non-selected sub-arrays are not precharged but only the bit lines of the selected sub-array are precharged before reading. Hereinafter, such a semiconductor memory device will be referred to as a reference example.

In the semiconductor memory device of the reference example, as shown in FIG. 16, the cell array is divided into sections Sect1 to Sect.
4 is divided into a plurality of sub-arrays, and pre-charge transistors QA and QB and an equalizing transistor QC are provided for each bit line pair in a plurality of columns in each sub-array, and in accordance with the bit line pre-charge signals / φP1 to / φP4. , For each sub-array, each bit line is connected to a power source for precharging, and a plurality of memory cells MC0, MC1, ..., M corresponding to each bit line pair.
It is similar to the case of the conventional example 4 shown in FIG. 30 that the reading is performed by providing Ci and selecting via the word line of each corresponding row, but each bit is Dummy memory cells DMC are provided in the line pairs, and the dummy memory cells are connected to the dummy word lines DW1 to DW.
4 is different in that it is connected to a dummy word generation circuit (not shown) through the line 4.

Next, the operation of the semiconductor memory device of the reference example will be described with reference to FIG. During the active period,
The bit lines of all non-selected sub-arrays are not precharged, only the bit lines of the selected sub-array are precharged before reading, then the selected word line is set to high level and the memory cell data is transferred to the bit line. And the bit line precharge signals / φP1 to / φP4 are set to the high level during the standby period to prevent all the bit lines of all the sub-arrays from being precharged. On the other hand, during the standby period, the signals of all the dummy word lines DW1 to DW4 are set to the high level to activate the dummy memory cells in all the sub-arrays to fix the potential of the bit lines. In this case, for example, in the sub-array of section Sect4, the bit line /
Even if BL1 has a leak path through the resistor RL, the standby current does not increase during the standby period because the bit line is not precharged.

As described above, the semiconductor memory device of the third embodiment in which the sub-array having the leak path and the normal sub-array are separately operated, and the sub-array having the leak path and the normal sub-array are not distinguished. The semiconductor memory device of the reference example to be operated is similar in that the increase of the standby current can be prevented and the bit line potential can be fixed during the standby period, but the address switching when the memory read cycle becomes short There is a difference in the magnitude of the operating current.

Next, referring to FIGS. 17 to 22, when the memory read cycle time changes in the semiconductor memory device of this example and the semiconductor memory device of the reference example,
The change in operating current will be described. 17 and 18 show
FIG. 17 shows a case where the address is changed for each section in the continuous read state, and FIG. 17 shows a case where the memory read cycle time is long (long cycle).
18 shows the case where the memory read cycle time is short (short cycle). In each figure, (a) shows the case of the reference example, and (b) shows the case of this example. In either case, section S
= 2 includes a bit line pair having a leak path.

In the case of the reference example shown in FIGS. 17A and 18A, by accessing sections 1 to 4, the bit lines of each section are precharged at the beginning of the memory read cycle time. After that, reading is performed. At this time, in each bit line pair of sections 1, 3 and 4 which does not include a bit line having a leak path, both bit lines are precharged to the power supply potential Vcc within a predetermined precharge period. , The potential of the bit line gradually decreases. On the other hand, in the bit line pair of section 2 including the bit line having the leak path, the change state of the bit line potential is different from the cases of sections 1, 3 and 4. FIG. 19 corresponds to FIG.
(A), changes in the bit line potential (solid line) in the portion indicated by (1) in FIG. 18A in the case of a non-defective bit line pair having no leak path and in the case of a defective bit line pair having a leak path The change of the bit line potential (broken line) is shown separately and enlarged, and in the case of the non-defective bit line pair shown in (A), the potential of the bit line is set to a predetermined precharge period. Inside, as indicated by a, the power supply potential Vc
Although it is precharged to c and rises, it gradually decreases as indicated by b, while in the case of a defective bit line pair having a leak path shown in (B), the power supply voltage Vc
The bit line c having a leak path decreases slightly due to the influence of the bit line having a leak path at the time of precharge, and the bit line having a leak path has a slower rise in potential due to precharge, and the bit line c has a power supply voltage as shown by d. It does not rise to Vcc, and at the time of reading, due to leakage,
As shown by e, it is shown that the potential rapidly drops to the ground potential GND.

On the other hand, in the case of this example shown in FIGS. 17 (b) and 18 (b), in each bit line pair of sections 1, 3 and 4 which does not include a bit line having a leak path,
Reading is done in the active period and then
Although the potential of the bit line gradually decreases, precharge is performed when the read cycle time is over and the non-selected state is reached. On the other hand, in the bit line pair of the section 2 including the bit line having the leak path,
The change state of the bit line potential is different from that in the sections 1, 3 and 4. FIG. 20 shows FIG. 17 (b) and FIG.
A change in bit line potential (solid line) in the case of a non-defective bit line pair having no leak path and a change in bit line potential in the case of a defective bit line pair having a leak path ((2) in (b)) (Dashed line) and
In the case of the non-defective bit line pair shown in (A), it is pre-charged to the power supply potential before the access is started, and after reading is performed in this state,
Although the potential gradually decreases as shown by f, in the case of the defective bit line pair shown by (B), it is precharged (equalized) to an intermediate level as shown by g due to leakage. From the state in which the read mode is entered, the power supply potential Vc suddenly increases as indicated by h and i.
It is shown that the potentials are fixed to c and the ground potential GND and precharged to an intermediate level again by the end of the read cycle time.

21 and 22 show the case where the address is changed for each section in the read state including the standby period. FIG. 21 shows the case where the memory read cycle time is long (long cycle). 22), and FIG. 22 shows a case where the memory read cycle time is short (short cycle). In each figure,
(A) shows the case of a reference example, (b) has shown the case of this example.

In the case of the reference example shown in FIGS. 21A and 22A, since the precharge is not performed in the standby period, the change state of the bit line potential is as shown in FIGS.
This is similar to the case of continuous reading shown in (a). In the case of this example shown in FIGS. 21B and 22B, each bit line pair of sections 1, 3 and 4, which does not include a bit line having a leak path, is precharged in the active period. After that, reading is performed, and then the potential of the bit line gradually decreases. However, since the bit line is precharged during the standby period, the potential of the bit line is kept at the power supply potential thereafter. . On the other hand, in the bit line pair of the section 2 including the bit line having the leak path, the non-selected state is precharged (equalized) to the intermediate level based on the leak, and the standby period is changed. By entering, the power supply potential and the ground potential are applied to the bit line by the dummy memory cell, and then the bit line potential gradually decreases. Next, when the selected state is entered, the bit line is gradually precharged in the active period and then read, and then the potential of the bit line gradually decreases. A power supply potential and a ground potential are applied to the bit line, and then the bit line potential gradually decreases. After that, the process of applying the power supply potential and the ground potential to the bit line by the dummy memory cell in the active level in the non-selected state and the dummy memory cell in the standby period, and the subsequent decrease of the bit line potential are It will be repeated until.

As is clear from the above description, in the case of the reference example, the bit lines of the non-selected sub-array are not precharged while the other sub-arrays are selected, and the bit lines of the non-selected sub-arrays are not precharged by the read data from the dummy memory cells. Since the potential is determined, when the address is switched between the sub-arrays, it is necessary to flow a pre-charge current that changes the potential of the bit line determined during the non-selection period to the power supply voltage. Therefore, the operating current increases during the short cycle operation in which the address switching frequency between the sub-arrays is high. On the other hand, in the case of this example, since the defective bit line having the leak path is not precharged during the standby period, the defective bit line having the leak path becomes the ground potential due to the leak, but the standby current does not increase. At this time, the sub-array that does not perform pre-charge in the standby period is only the one including the defective bit line having the leak path, and the pre-charge is performed in the other sub-arrays, so that the bit line potential difference is small even in the short cycle. The increase in operating current is small.

As described above, according to the semiconductor memory device of this example, in the sub-array including the bit line having the leak path, the precharge is not performed during the standby period, so that the standby current of the semiconductor memory device increases. There is no. Further, the operating current in the active period increases by the amount of the sub-array including the bit line having the leak path, but the operating current in the short cycle increases as compared with the semiconductor memory device of the type in which all non-selected sub-arrays are not precharged. Can be suppressed. Further, unlike the conventional example 4, even if there is a leak defect in the sub-array Sect2, the pre-charge current is supplied, so that a slight leak current flows in the sub-array Sect2 during the pre-charge operation, but no standby current flows. You can Therefore, the redundant memory cell array can be replaced with a unit smaller than the sub-array unit, and the replacement efficiency does not deteriorate. For example, even if the redundant memory cell array has only one sub-block, if it can be replaced in units of 1/10 of one sub-block, one sub-block can be used for a plurality of sub-arrays.
Bit line defects up to 0 unit can be relieved. Therefore, even if the area of the redundant memory cell array is small, the defect remedy rate can be increased, the chip size is not increased, and the chip cost can be reduced.

The embodiment of the present invention has been described in detail above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and there are design changes and the like within the scope not departing from the gist of the present invention. However, it is included in this invention. For example, in the case of the first or third embodiment, a memory cell for holding data is used instead of the dummy memory cell and is connected to a bit line having a leak path controlled by the word line of the memory cell. You may do it. Further, in the case of the third embodiment, as in the case of the second embodiment, it is also possible to use two one-sided open dummy memory cells as the dummy memory cells. In each of the embodiments, only the case where there is a leak path with respect to the ground potential has been described. However, the present invention is not limited to this, and there may be a case where a leak path exists with respect to the power supply potential or any intermediate potential. Furthermore, although the semiconductor memory device has been described in the embodiment, the present invention is not limited to this, and it is applied to a potential fixing method for a wiring and has an operation period and a standby period. It is also possible to provide a potential fixing means connected to this wiring in response to a signal from the outside, and fix the potential of this wiring based on the potential held by the potential fixing means. . In this case, the potential fixing means may be connected to the wiring at the start of the standby period or at a time close thereto. Further, the potential held by the potential fixing means can be a power source potential or a potential close thereto, or a ground potential or a potential close thereto. In addition, a DRAM having only one bit line in one memory cell column
, ROM, EEPROM, or microcomputer or logic I
The present invention can be applied to a semiconductor device such as C. Further, the potential of the wiring may be constantly fixed to the potential generated by the leak failure, that is, the potential of the leak path destination, without switching the operation of the potential fixing unit between the operation period and the standby period.

[0065]

As described above, according to the semiconductor memory device of the present invention, the presence of the bit line having the leak path does not increase the standby current and also increases the operating current in the short cycle. In addition, there is no risk of malfunction or destruction of the memory cell due to fluctuations in the power supply potential, etc. Furthermore, in order to avoid such problems, increase in chip size and difficulty in layout can be avoided. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a semiconductor memory device to which the present invention is applied.

FIG. 2 is a diagram showing a configuration of a cell array in the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration example of a memory cell in the first embodiment.

FIG. 4 is a diagram showing a configuration example of a Y switch in the first embodiment.

FIG. 5 is a diagram showing a configuration example of a one-shot pulse generation circuit in the first embodiment.

FIG. 6 is a diagram showing a configuration example of a word line activation signal generation circuit in the first embodiment.

FIG. 7 is a diagram showing a configuration example of a dummy word generation circuit in the first embodiment.

FIG. 8 is a diagram showing a configuration example of a word line selection circuit in the first embodiment.

FIG. 9 is a waveform diagram showing an operation of the semiconductor memory device in the first example.

FIG. 10 is a diagram showing a configuration of a cell array in a semiconductor memory device according to a second embodiment of the present invention.

FIG. 11 is a diagram showing a configuration example of a dummy memory cell in the second embodiment.

FIG. 12 is a diagram showing a structure of a cell array in a semiconductor memory device according to a third embodiment of the present invention.

FIG. 13 is a diagram showing a configuration example of a section decoder circuit in the third embodiment.

FIG. 14 is a diagram showing a configuration example of a word line activation signal generation circuit in the third embodiment.

FIG. 15 is a diagram showing a configuration example of a dummy word generation circuit in the third embodiment.

FIG. 16 is a diagram showing a configuration of a cell array in a semiconductor memory device which is a reference example.

FIG. 17 is a diagram showing a timing chart (A) for explaining the difference in operation between the third embodiment and the reference example.

FIG. 18 is a diagram showing a timing chart (B) for explaining the difference in operation between the third embodiment and the reference example.

FIG. 19 is a diagram for explaining changes in bit line potential between a bit line pair having a leak path and a bit line pair having no leak path in the case of the reference example.

FIG. 20 is a diagram for explaining changes in bit line potential between a bit line pair having a leak path and a bit line pair not having a leak path in the case of the third embodiment.

FIG. 21 is a diagram showing a timing chart (C) for explaining the difference in operation between the third embodiment and the reference example.

FIG. 22 is a diagram showing a timing chart (D) for explaining the difference in operation between the third embodiment and the reference example.

23 is a diagram showing a configuration of a cell array in the semiconductor memory device of Conventional Example 1. FIG.

FIG. 24 is a diagram showing the configuration of a word line activation signal and bit line precharge signal generation circuit of Conventional Example 1.

FIG. 25 is a diagram showing operation waveforms in the semiconductor memory device of Conventional Example 1.

FIG. 26 is a diagram showing a configuration of a cell array in a semiconductor memory device of Conventional Example 2.

FIG. 27 is a diagram showing operation waveforms in the semiconductor memory device of Conventional Example 2.

FIG. 28 is a diagram showing a configuration of a bit line precharge signal generation circuit in a semiconductor memory device of Conventional Example 3.

29 is a diagram showing operation waveforms in the semiconductor memory device of Conventional Example 3. FIG.

FIG. 30 is a diagram showing a configuration of a cell array in a semiconductor memory device of Conventional Example 4.

[Explanation of symbols]

1a, 1b Bit lines 2 ₀ , 2 ₁ , 2 ₂ , ... _, 2 _i Memory cells 3a, 3b Precharge transistor 3c Equalizing transistors 4 ₀ , 4 ₁ , 4 ₂ , ... _, 4 _i Word lines 5 ₀ , 5 ₁ , _, 5 _j Dummy memory cell 6 Dummy word line 7 ₀ , 7 ₁ , ... _, 7 _j Y switch 8 Write amplifier 9 Sense amplifier 15 ₁ , ..., 15 ₄ Dummy word generation circuit 16 ₁ , ..., 16 ₄ Bit line pre Charge signal generation circuit QA, QB Precharge transistor QC Equalize transistor MC0, MC1, ..., MCi Memory cell DMC Dummy memory cell BL, / BL Bit line F Fuse

Claims (5)

(57) [Claims] 1. A plurality of data holding memory cells, a plurality of bit lines in which a plurality of the memory cells are arranged on a bit line, and a memory cell of each bit line is selected in a row direction during operation to bit In a semiconductor memory device including a plurality of word lines for controlling connection to lines, and a precharge unit that precharges each of the bit lines to a predetermined potential before reading data from the memory cell, for each bit line, A semiconductor memory device, comprising: a potential fixing means connected to a bit line in accordance with a potential fixing signal only during a standby period to fix the potential of the bit line to a ground potential or a power supply potential . 2. A plurality of data holding memory cells, a plurality of bit lines in which the plurality of memory cells are arranged on a bit line, and memory cells of each bit line are selected in the row direction during operation to set bits. A cell array having a plurality of word lines for connecting and controlling the lines is divided into a plurality of sub-arrays,
For each sub-array, it is connected to each bit line according to the potential fixing signal and the potential of the bit line is set to the ground potential or the power supply potential.
In a semiconductor memory device comprising potential fixing means for fixing to each of the memory cells and precharge means for precharging each bit line to a predetermined potential before reading data from the memory cell, in all normal sub-arrays, While all the bit lines are precharged by the precharge means in the standby period and the potential fixing means is made inoperative, in the sub-array including the bit lines having the leakage path, the precharge means precharges during the standby period. A semiconductor memory device, characterized in that the potential fixing means is operated only in a standby period without charging. 3. The potential fixing means comprises a dummy memory cell provided for each bit line, and each dummy memory
The cell is configured to be connected to the corresponding bit line by a dummy word line during a standby period, and the potential of the bit line is held and fixed by the dummy memory cell. 3. The semiconductor memory device according to 1 or 2. 4. The potential fixing means comprises a plurality of bit line pairs.
From provided was their respective two dummy memory cell in every
And the two dummy memory cells are
Connect the corresponding bit line pair with a dummy word line.
Each one of the two bit lines
The potential of each bit line pair is set to the two dummy memories.
3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured to be held and fixed by cells . 5. The potential fixing means comprises a full CMOS flip-flop.
2. The semiconductor memory device according to any one of 1.