JP3425933B2 - Asynchronous inter-system information transfer method, device therefor, and recording medium recording control program therefor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous inter-system information transfer method and apparatus, and more specifically, to a second processing system that periodically operates asynchronously from the first processing system to the processing system. The present invention relates to an asynchronous inter-system information transfer method for preventing leakage of information when transferring information, a device therefor, and a recording medium recording a control program therefor.

[0002]

2. Description of the Related Art Conventional SDH (Synchronous Digital Hierarchy)
y)) In a transmission quality monitoring apparatus provided on the receiving side of a transmission line that constitutes a communication system or a communication network using the technology (hereinafter, abbreviated as SDH technology), the operation speed is set to a single operation speed. Can be configured. Also, a first processing system that takes in the transmission quality monitoring device, at a first operating speed, alarm information transmitted through a transmission path of a communication system or a communication network, or alarm information detected by the transmission quality monitoring device itself. And a second processing system that receives the alarm information taken in by the first processing system at an operation speed different from the operation speed of the first processing system, that is, a second processing system that receives the alarm information cyclically asynchronously, It is also possible to use the alarm information taken into the second processing system for monitoring the transmission quality of the transmission line.

A transmission quality monitoring device having such a configuration will be specifically described with reference to FIG. The transmission quality monitoring apparatus 100 includes a first processing system 102, a memory 106,
It is composed of a second processing system 108 and an access arbitration circuit 110. The first processing system 102 is connected to a transmission line 104 that constitutes a communication system or a communication network. First
The processing system 102 of the memory 1106 connects the output of the alarm information captured therein to the write input of the memory 106,
The read output of is connected to the capture input of the second processing system 108. The alarm information output of the second processing system 108 is connected to a display device (not shown). An access arbitration circuit 110 is connected to the first processing system 102 and the second processing system 108. The access arbitration circuit 110 includes a first processing system 102 and a second processing system 108.
It acts to arbitrate contention of access requests asynchronously issued from and to allow access to the memory 106 to either one of the two processing systems.

In the transmission quality monitoring apparatus 100, when the first processing system 102 detects the occurrence of an alarm state on the transmission path 104, the detected first alarm information (first logical value) is used as an access arbitration circuit. Write to the memory 106 while receiving access arbitration by the 110. In addition, the first processing system 1
When 02 detects the recovery of the alarm state on the transmission path 104, the detected second alarm information (second logical value) is written in the memory 106 under the access arbitration by the access arbitration circuit 110. On the other hand, the second processing system 108 reads the alarm information written in the memory 106 while being arbitrated for access competition by the access arbitration circuit 110 every unit time, for example, every second. The alarm information read from the memory 106 by the second processing system 108 is supplied to the display device and used for monitoring the transmission quality of the transmission path 104.

In this transmission quality monitoring apparatus 100,
When the occurrence or recovery of the alarm state on the transmission path 104 occurs at intervals of unit time or more, for example, as shown in FIG. 16, when the occurrence or recovery of the alarm state occurs, the alarm information Is correctly delivered from the first processing system 102 through the memory 106 to the second processing system 108.

[0006]

However, the occurrence or recovery of the alarm state on the transmission line 104 occurs within a unit time, for example, on the transmission line 104 as shown in FIG. When the occurrence of an alarm condition or its recovery occurs, the alarm information written in the memory 106 is changed to the second information.
Before it is read by the processing system 108, it is rewritten by the alarm information that occurs next. Therefore, the alarm information is not correctly delivered from the first processing system 102 to the second processing system 108. That is, the first
There is a leak in the delivery of the alarm information from the processing system 102 to the second processing system 108. Such a problem is an unavoidable problem even when the same configuration is adopted in the signal transmission system.

The present invention has been made in view of the above circumstances, and information is transferred from the first processing system to the second processing system which operates periodically asynchronously with the processing system without omission. It is an object of the present invention to provide an asynchronous inter-system information transfer method, a device therefor, and a recording medium having a control program therefor.

[0008]

In order to solve the above-mentioned problems, the invention according to claim 1 detects the occurrence or recovery of the state of the transmission line in a first processing system to which the transmission line is connected. The present invention relates to an asynchronous inter-system information transfer method for delivering the obtained information to a second processing system that operates periodically asynchronously with the first processing system. In the first processing system, occurrence or restoration of the state of the transmission path is performed. Each time the detection is performed, the information obtained at the detection timing is stored in the first storage means, and the first information within the periodic operation time of the second processing system is detected from the detection timing.
At the write timing after a predetermined time of
The information stored in the second storage means is stored in the second storage means, and the information stored in the first storage means by the previous periodic operation for each periodic operation of the second processing system. Read before storing the information, and when the second predetermined time has elapsed from the read time before the write timing, read the information stored in the second storage unit until the previous cyclic operation, Based on the two pieces of read information, the information of the occurrence or the recovery is added to the second information.
Information is read out from the second storage means, and the information read from the first storage means is overwritten on the second storage means when a third predetermined time has elapsed from the reading time of the information from the second storage means. It is characterized by that.

A second aspect of the present invention relates to the asynchronous inter-system information transfer method according to the first aspect, wherein the first predetermined time period is larger than the sum of the second predetermined time period and the third predetermined time period. By setting, it is possible to prevent the information stored in the second storage unit from being rewritten at the write timing due to the overwrite except for the conflict between the write timing and the overwrite. .

The invention according to claim 3 relates to the asynchronous inter-system information transfer method according to claim 1, wherein after the overwriting is performed, the overwriting is performed every periodic operation of the second processing system. The second information of the information obtained by re-reading from the first storage means after a lapse of a fourth predetermined time from the opened time and at the lapse of a fifth predetermined time from the re-reading time. Rewriting to the storage means is performed, and the information in the second storage means rewritten by the conflict between the write timing and the overwrite is written back by the rereading and the rewriting.

The invention according to claim 4 relates to the asynchronous inter-system information transfer method according to claim 1, 2 or 3, wherein the second processing of the information obtained by the generation or the recovery based on the two pieces of information. The delivery to the system is characterized by taking the logical sum of the above two pieces of information.

According to a fifth aspect of the invention, the information obtained by detecting the occurrence or recovery of the state of the transmission line in the first processing system to which the transmission line is connected is cycled asynchronously with the first processing system. The asynchronous inter-system information transfer device that transfers the information to the second processing system that operates normally, and each time the first processing system detects the occurrence and recovery of the state of the transmission path, the information obtained at the detection timing. A first storage means for storing information, and a first storage device within the periodic operation time of the second processing system from the detection timing.
At the write timing after a predetermined time of
Second storage means for storing the information stored in the storage means, and information stored in the first storage means for each periodic operation of the second processing system until the previous periodic operation. Read before storing the information and before the write timing, and stored in the second storage means from the read time to the previous periodic operation when a second predetermined time has elapsed. Reading information, and overwriting the second storage means with the information read from the first storage means when a third predetermined time has elapsed from the time when the information was read from the second storage means And a delivery means for delivering the generation or recovery information to the second processing system based on the two pieces of read information.

According to a sixth aspect of the present invention, in the asynchronous inter-system information transfer apparatus according to the fifth aspect, the first predetermined time period is larger than the sum of the second predetermined time period and the third predetermined time period. By setting, it is possible to prevent the information stored in the second storage unit from being rewritten at the write timing due to the overwrite except for the conflict between the write timing and the overwrite. .

According to a seventh aspect of the present invention, in the asynchronous inter-system information transfer apparatus according to the fifth aspect, the control means performs the periodic operation of the second processing system after the overwriting is performed. The re-reading from the first storage unit after a lapse of a fourth predetermined time from the time when the overwriting was performed and the re-reading after a lapse of a fifth predetermined time from the re-reading time. Rewriting information to the second storage means, and rewriting the information of the second storage means rewritten by the conflict between the write timing and the overwrite by the rereading and the rewriting. It is characterized by doing.

The invention according to claim 8 relates to the asynchronous inter-system information transfer apparatus according to claim 5, 6 or 7, wherein the delivery means takes the logical sum of the two pieces of information to deliver. I am trying.

The invention according to claim 9 relates to a recording medium having a control program recorded thereon, wherein
It is characterized in that a control program for implementing the asynchronous inter-system information transfer method described in 3 or 4 is recorded.

The invention according to claim 10 is characterized in that a control program for realizing the function of the asynchronous inter-system information transfer device according to claim 5, 6, 7 or 8 is recorded in a computer.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The description will be made in detail using examples. First Embodiment FIG. 1 is a diagram showing an electrical configuration of an asynchronous inter-system information transfer apparatus according to the first embodiment of the present invention, and FIG. 2 shows a memory provided in the asynchronous inter-system information transfer apparatus. A time sequence of generation or recovery of alarm information written in the first and second memory areas in a state where access to the first memory area is irregular and access time intervals to the second memory area are constant, 3 is a time sequence of reading the alarm information from the first and second memory areas and writing the alarm information to the second memory area in (1) of FIG. 2, and FIG. A time sequence of writing alarm information to the first and second memory areas and reading alarm information from the first and second memory areas in (2), and FIG. 5 is a time sequence of (3) in FIG. Alarm to 1st and 2nd memory area 2 is a time sequence for writing the alarm information and reading the alarm information from the first and second memory areas, and FIG. 6 is a timing sequence for writing the alarm information to the first and second memory areas in (4) in FIG. The time sequence for reading the alarm information from the first and second memory areas, and FIG. 7 shows the first and second time periods in (5) in FIG.
2 is a time sequence of reading alarm information from the memory area of 1 and writing alarm information to the second memory area.

Information transfer device 10 between asynchronous processing systems of this example
Is provided in the transmission quality monitoring device, and from the first processing system 12 that takes in the alarm information that occurs on the transmission path that constitutes the communication system or communication network using the SDH technology, asynchronously with the first processing system 12. The present invention relates to an apparatus capable of eliminating alarm information transfer failure when transferring alarm information to the second processing 18 that operates periodically, as shown in FIG.
The memory 16 includes a second processing system 18, and an access arbitration circuit 20.

The first processing system 12 is connected to a transmission line 14 which constitutes a communication system using the SDH technology.
The first processing system 12 connects the output of the alarm information fetched therein to the write input of the memory 16. The first processing system 12 also outputs its access request output 12A to the first and second memory areas 16A and 16A when an alarm condition occurs.
A write access request to B is output, and at the time of recovery, a write access request to the second memory area 16A is output.

The memory 16 has a first memory area 16A and a second memory area 16B. First memory area 1
6A is alarm information when an alarm condition occurs (logical value "1")
And the alarm information at the time of recovery (logical value "0") is written, and the second memory area 16B writes the alarm information at the time of occurrence of the alarm state to the memory 16 from the second processing system 18. This is for writing the alarm information read from the first memory area 16A by the periodical access (per unit time) to the memory when a predetermined time elapses as follows. The above predetermined time is
When the alarm condition occurs, the alarm information is sent to the first memory area 16A.
The time and its alarm information written in the second memory area 1
It is a value smaller than the time T between the time of writing in 6B.

The capture input of the second processing system 18 is connected to the read output of the memory 16. The second processing system 18 outputs a read access request to the memory 16 to the first memory area 16A and the second memory area 16B, and also outputs a write access request to the second memory area 16B. To do. The second processing system 18 has means for temporarily holding the alarm information read from the first memory area 16A, for example, a register, and the number of occurrences (the number of alarm information when an alarm condition occurs). ) Is included.

The alarm information output of the second processing system 18 is connected to a monitoring display device (not shown), and an error state is generated when the count value is larger than the threshold value, and the number of occurrences (when the count value is smaller than the threshold value). (Count value) is supplied. The monitor display device is used by a monitor for monitoring the transmission quality of the transmission line 14. When the monitored transmission quality is greatly deteriorated, for example, when the count value becomes larger than the threshold value and the transmission line is in an error state, the duplicated transmission line 14 is switched. .

Further, the first processing system 12 and the second processing system 1
An access arbitration circuit 20 is connected to 8 and. The access arbitration circuit 20 includes an access request output from the access request output 12A of the first processing system 12 and the second processing system 1.
8 from the access request output 18A of 8 to arbitrate the competition between the access request issued asynchronously with the first processing system 12 and permit access to the memory 16 to either one of the two processing systems. To do.

These access conflicts are caused by the first processing system 1.
2 between the writing to the first memory area 16A and the writing to the second memory area 16B (T in FIGS. 4 and 6) is the first time per unit time by the second processing system 18. Between the read time from the memory area 16A and the read time from the second memory area 16B (T / 2 in FIGS. 3 to 7), the read time from the second memory area 16B, and the second time. Second memory area 16B of information read from the first memory area 16A by the processing system 18 of
Time between the write time and the write time (T / T in FIGS. 3 to 7).
2) Writing to the first memory area 16A and the second memory area 16B by the first processing system 12 under the condition that the sum is larger than the sum of (A in FIGS. 4, 5, and 6).
1, A2), reading from the first memory area 16A and the second memory area 16B by the second processing system 18 (B1, B2 in FIGS. 4 to 7), and the second processing system 18 2 to the memory area 16B (B3 in FIGS. 4 to 7), and the access arbitration circuit 20
Arbitrates their access contention.

Next, the operation of this example will be described with reference to FIGS. For convenience of explaining the operation of the asynchronous inter-system information transfer device 10, the transmission line 14 is in a normal transmission state in which an alarm state is not generated, that is, initially,
In the normal transmission state, or in the normal transmission state in which the alarm state is once generated but the alarm state is recovered thereafter (referred to as the first transmission state), the first processing system 1
A case where alarm information is passed from 2 to the second processing system 18 will be described. This first transmission state is shown in (1) of FIG. 2, and its detailed time sequence is shown in FIG.
In addition to the above-mentioned first transmission state, FIG. 2 shows second to fifth transmission states which will be described later. In any of these cases, (a) is stored in the first memory area 16A. The displayed or stored alarm information is shown, and (b) shows the stored or stored alarm information in the second memory area 16B.

In the first transmission state, neither the alarm state is generated nor the recovery thereof is detected, so that the write access request from the first processing system 12 is not generated. Therefore, writing from the first processing system 12 to the first memory area 16A and the second memory area 16B of the memory 16 is not performed.

However, the first memory area 1 of the memory 16
The reading from the unit 6A per unit time (B1 in FIG. 3) and the half of the above-mentioned time T from the reading (hereinafter also referred to as the reading time T / 2 of the second processing system 18). Reading from the second memory area 16B at the elapsed time (B2 in FIG. 3) and the first at the time when the reading time of the second processing system 18 has elapsed from the time at which the reading from the second memory area 16B was performed The second processing system 18 writes the alarm information read from the memory area 16A in the second memory area 16B into the second memory area 16B (B3 in FIG. 3).

A time sequence of reading and writing by the second processing system 18 is shown in FIG. The operation will be described with reference to FIG. In Figure 3, (a)
Indicates that the alarm information "0" is continuously stored in the first memory area 16A. Since the access request output 12A of the first processing system 12 does not issue an access request to the access arbitration circuit 20, the first memory area 16A
As shown in (a) of FIG. 3, the alarm information of is a logical value "0", and the logical value is not changed as long as the above-mentioned first transmission state continues.

Further, FIG. 3B shows the second memory area 16
B indicates that the alarm information 0 ″ is continuously stored. As described above, since the transmission state of the transmission path 14 is the above-mentioned first transmission state, the access request of the second processing system 18 is made. When an access request is issued from the output 18A to the access arbitration circuit 20, the second processing system 18 is allowed to access the memory 16. The second processing system 18 allows the first memory area 16A of the memory 16 to access the memory 16. Readout B1 is performed every unit time, and the alarm information is the second processing system 1
8 registers. At the time when the reading time of the second processing system 18 has elapsed from this reading, the same reading B2 from the second memory area 16B is performed. Then, at the time when the reading time of the second processing system 18 has elapsed from the time when the reading was performed from the second memory area 16B, the alarm information read from the first memory area 16A and held in the register is displayed. Writing B3 to the second memory area 16B is performed.

The alarm information "0" read by the above-mentioned reading B2 is logically ORed with the alarm information supplied to the second processing system 18 and held in the register. This logical sum is "0", but this logical sum "0"
Passed from the first processing system 12 to the second processing system 18 that the alarm state on the transmission path 14 had not occurred during the time from the previous writing B3 to the current reading B2. That is, it means the delivery of an unoccurred state.

If the alarm state is not generated, the second processing system 1
It is not counted by the counting means of 8A. Then, the count value is compared with the threshold value every periodic unit time. When the count value is larger than the threshold value, it is displayed on the monitor display device that the transmission line 14 is in an error state. When the count value is less than or equal to the threshold value, the number of times the alarm state has occurred is displayed on the monitor display device.

Further, the alarm information read in the above-mentioned reading B1, that is, the second memory area 16B of "0".
Write B3 to the second processing unit 12 from the first processing system 12 indicates that the alarm state on the transmission line 14 continues in a state where no alarm has occurred.
To the processing system 18 (i.e., handing over the continuity of the alarm state). Therefore, in the transfer of the alarm information from the first processing system 12 to the second processing system 18, there is no omission in the delivery thereof.

Next, an alarm condition occurs on the transmission line 14 in which the above-mentioned first transmission condition continues, and the first processing system 1
2, the alarm status is detected and alarm information "1"
In the second transmission state in which the first processing system 1 is generated.
A case where alarm information is passed from 2 to the second processing system 18 will be described. This transmission state is shown in (2) of FIG. 2, and its detailed time sequence is shown in FIG.
In FIG. 4, (a) indicates that when the alarm information “0” is stored in the first memory area 16A and continues, and then the alarm state is generated in the transmission line 14, the first information is displayed. The alarm information stored in the memory area 16A is shown in FIG.
The alarm information “0” is stored in the second memory area 16B and continues, and when the alarm state is generated in the transmission line 14 after that, the alarm information stored in the first memory area 16B is displayed. Show.

In this transmission state, the first processing system 1
Writing alarm information generated from No. 2 to the first memory area 16A and the second memory area 16B (A1 and A2 in FIG. 4) and an alarm from the first memory area 16A and the second memory area 16B Reading of information (B1 and B2 in FIG. 4) and writing of alarm information read from the first memory area 16A to the second memory area 16B (B3 in FIG. 4) are performed.

FIG. 4 shows a case where write A1 and read B1 compete with each other and write A2 and write B3 compete with each other. When the write A1 and the read B1 compete with each other, the read B1 by the second processing system 18 is preferentially performed by the arbitration of the access arbitration circuit 20 as described above, and the alarm information thereof is the second process. It is held in the register of the system 18. After the reading B1 is completed, the first
Writing A1 is performed by the processing system 12 of FIG.

Then, the read B2 similar to that described in the first transfer state is performed. Also in the second transfer state, similarly to the first transfer state, the logical sum of the alarm information read in the read B1 and held in the register and the alarm information read in the read B2, that is, the logic The logical sum of the values “0” is taken by the second processing system 18. Since the logical sum is "0", the non-occurrence of the alarm state is delivered to the second processing system 18.

If the alarm state is not generated, the second processing system 1
It is not counted by the counting means of 8A. Then, the count value is compared with the threshold value every periodic unit time. When the count value is larger than the threshold value, it is displayed on the monitor display device that the transmission line 14 is in an error state. When the count value is less than or equal to the threshold value, the number of times the alarm state has occurred is displayed on the monitor display device.

Then, as described in the first transfer state, the write B3 is performed after the read B2. Write B3 at that time is set to the write timing as described above, that is, write A1.
And time A between writing A2 and reading B1 and reading B
2 and the time of read B2 and write B3 are selected to be larger than the sum of the values, and access conflict is arbitrated by the access arbitration circuit 20. Therefore, after read B3 is performed, write A2 is Done.

In this way, if the first memory area 16A, the second memory area 16B and the access arbitration circuit 20 of this example were not present, the conflict between the write A2 and the write B3 that would have occurred. Therefore, the alarm information written in the second memory area 16B, for example, the logical value "1" is rewritten with the alarm information read in the read B1, for example, the logical value "0". Things will disappear. Then, the second memory area 16 of the alarm information read in the read B1 and held in the register
Since the writing B3 to B is performed, the fact that the alarm has not been generated is continued (the continuity of the alarm state) to the second processing system 18. Therefore, even if an access conflict occurs, there is no omission in delivering the alarm information.

Next, in the case where the alarm state is generated and then the alarm state is handed over from the first processing system 12 to the second processing system 18 in the third transmission state which occurs near the time when the alarm state is recovered. explain. This transmission state is shown in FIG.
It is shown in (3) and its detailed time sequence is shown in FIG. FIG. 5A shows that the alarm information “1” is stored in the first memory area 16A and continues to be stored, the alarm state is recovered after that, and the alarm information “0” is stored. Show. Further, FIG. 5B shows the second memory area 16B.
The alarm information "0" is stored in the table and indicates that it is continuing. In this third transmission state, the first processing system 1
Writing the alarm information generated from No. 2 to the first memory area 16A (A1 in FIG. 5) and the first memory area 16A
And reading the alarm information from the second memory area 16B (B1 and B2 in FIG. 5) and writing the alarm information read from the first memory area 16A to the second memory area 16B (B3 in FIG. 5). And are done.

FIG. 5 shows a case where the write A1 and the read B1 compete with each other. When the write A1 and the read B1 compete with each other, the read B1 by the second processing system 18 is preferentially performed by the arbitration of the access arbitration circuit 20 as described above, and the alarm information thereof is processed by the second process. System 1
8 registers. After the read B1 is completed, the write A1 by the first processing system 12 is performed.

Then, the read B2 similar to that described in the first transfer state is performed. Also in the third transfer state, similarly to the first transfer state, the logical sum of the alarm information read in the read B1 and held in the register and the alarm information read in the read B2, that is, the logic The logical sum of the values “1” is taken by the second processing system 18. Since the logical sum is "1", the occurrence of the alarm condition
It is delivered to the second processing system 18.

This alarm state is generated by the second processing system 18
It is counted by the counting means A. Then, the count value is compared with the threshold value every periodic unit time. When the count value is larger than the threshold value, it is displayed on the monitor display device that the transmission line 14 is in an error state. When the count value is less than or equal to the threshold value, the number of times the alarm state has occurred is displayed on the monitor display device.

Then, as described in the first transfer state, the write B3 is performed after the read B2. In this way, since the alarm information read in the read B1 is written B3 in the second memory area 16B, the occurrence of the alarm state is continued (alarm state continuity). It is delivered to the second processing system 18. Therefore, in this transmission state, no leak occurs in the delivery of the alarm information.

Next, in the fourth transmission state in which the alarm state that has occurred is recovered and then the alarm state has occurred,
A case where the generation of the alarm state from the first processing system 12 to the second processing system 18 is handed over will be described. This transmission state is shown in (4) of FIG. 2, and its detailed time sequence is shown in FIG. FIG. 6A shows the first memory area 1
Alarm information "0" is stored in 6A and continues,
The alarm information stored in the first memory area 16A when an alarm state occurs in the transmission line 14 thereafter is shown.
In (b), the alarm information "1" is stored in the second memory area 16B and continues, and then stored in the first memory area 16B when an alarm condition occurs in the transmission path 14. Indicates the alarm information to be displayed.

In the fourth transmission state, the first memory area 1 for the alarm information generated from the first processing system 12 is used.
6A and the second memory area 16B are written (A1 and A2 shown in FIG. 6), and the alarm information is read from the first memory area 16A and the second memory area 16B (see FIG. 6).
B1 and B2) and the alarm information read from the first memory area 16A to the second memory area 16B (B3 in FIG. 6).

FIG. 6 shows a case where write A1 and read B1 compete with each other and write A2 and read B3 compete with each other. When the write A1 and the read B1 compete with each other, the read B1 by the second processing system 18 is preferentially performed by the arbitration of the access arbitration circuit 20 as described above, and the alarm information thereof is the second process. It is held in the register of the system 18. After the reading B1 is completed, the first
Writing A1 is performed by the processing system 12 of FIG.

Then, the read B2 similar to that described in the first transfer state is performed. Also in the fourth transfer state, similarly to the first transfer state, the logical sum of the alarm information read in the read B1 and held in the register and the alarm information read in the read B2, that is, read B1. The second processing system 18 obtains the logical sum of the alarm information "0" read in step B2 and the alarm information "1" read in step B2. Since the logical sum is "1", the occurrence of the alarm state is delivered to the second processing system 18.

This alarm state is generated by the second processing system 18
It is counted by the counting means A. Second processing system 18A
The count value is compared with the threshold value every periodic unit time according to. When the count value is larger than the threshold value, it is displayed on the monitor display device that the transmission line 14 is in an error state. When the count value is less than or equal to the threshold value, the number of times the alarm state has occurred is displayed on the monitor display device.

Then, as described in the first transfer state, the write B3 is performed after the read B2. Write B3 at that time is set to the write timing as described above, that is, write A1.
And time A between writing A2 and reading B1 and reading B
2 and the time of read B2 and write B3 are selected to be larger than the sum of the values, and access conflict is arbitrated by the access arbitration circuit 20, so that write A2 is performed after write B3 is performed. Done.

Therefore, the first memory area 1 of this example is
6A, second memory area 16B and access arbitration circuit 2
If 0 does not exist, the conflict between the write A2 and the write B3, which may have occurred, is avoided, so that the alarm information written in the second memory area 16B, for example, the generated logical value “1” is The alarm information read in the reading B1, for example, the recovery logical value “0” will not be rewritten. In this way, since the alarm information read out by the read B1 and held in the register is written B3 in the second memory area 16B, the occurrence of the alarm state is handed over to the second processing system 18. . That is, the continuity of the alarm state is handed over to the second processing system 18. Therefore, even if an access conflict occurs, there is no omission in delivering the alarm information.

Next, a case will be described in which the occurrence of the alarm state is handed over from the first processing system 12 to the second processing system 18 in the fifth transmission state in which the alarm state is continuously generated. This transmission state is shown in (5) of FIG. 2, and its detailed time sequence is shown in FIG. Figure 7 (a)
Shows the case where the alarm information "1" is stored in the first memory area 16A and the state continues, as shown in FIG.
Indicates that the alarm information "1" is stored in the second memory area 16B and that state continues.

In the fifth transmission state, since neither a new occurrence of the alarm state nor its recovery is detected, the write access request from the first processing system 12 is not issued. Therefore, from the first processing system 12 to the first memory 16
Is not written to the memory area 16A and the second memory area 16B.

However, the first memory area 1 of the memory 16
At the time of reading from the unit 6A for every unit time (B1 in FIG. 7) and the time when the half of the time T described above (also referred to as the reading time of the second processing system 18) has elapsed from the reading time. The read from the second memory area 16B (B2 in FIG. 7) and the first memory area 16A at the time when the read time of the second processing system 18 has elapsed from the time of reading from the second memory area 16B The second processing system 18 writes the alarm information read out from the second memory area 16B into the second memory area 16B (B3 in FIG. 7).

The time sequence of reading and writing by the second processing system 18 is shown in FIG. Figure 7
The operation will be described with reference to FIG. In FIG. 7, since the transmission state of the transmission line 14 is the above-mentioned fifth transmission state, the first processing system 12 does not detect the alarm information of the transmission line 14. Therefore, the alarm information stored in the memory area 16A by the first processing system 12 has the logical value "1" as shown in FIG. 7A, and the above-mentioned fifth transmission state continues. As long as there is no change in its logical value.

Further, as described above, since the access request output 12A of the first processing system 12 does not output the access request to the access arbitration circuit 20, the access arbitration circuit 20 causes the memory 16 in the second processing system 18. Access request is permitted, the second processing system 18 performs reading B1 from the first memory area 16A of the memory 16 for each unit time, and the alarm information is held in the register of the second processing system 18. To be done. At the time when the read time of the second processing system 18 has elapsed from this read time, the read B2 from the second memory area 16B is performed.

Also in the fifth transfer state, as in the first transfer state, the alarm information read in the readings B1 and B2, that is, the logical sum of the logical values "1" is the second processing system 18. Taken in. Since the logical sum is "1", the occurrence of the alarm state is delivered to the second processing system 18.

This alarm state is generated by the second processing system 18
It is counted by the counting means A. Then, the count value is compared with the threshold value every periodic unit time by the second processing system 18A. When the count value is larger than the threshold value, it is displayed on the monitor display device that the transmission line 14 is in an error state. When the count value is less than or equal to the threshold value, the number of times the alarm state has occurred is displayed on the monitor display device.

Then, at the time when the reading time of the second processing system 18 has elapsed from the time of reading from the first memory area 16A, the alarm read from the first memory area 16A and held in the register. Writing B3 of the information to the second memory area 16B is performed. The write B3 at that time is performed at the write timing as described above, that is, the time between the write A1 and the write A2 is between the read B1 and the read B2, and the read B2 and the write B3. The timing is selected to be larger than the sum of the time and the time. Further, since the alarm state continues to be generated, the writing A2 is not performed. Therefore, in this transmission state, contention between the write A2 and the read B3 does not occur, and the write B3 is performed without access arbitration by the access arbitration circuit 20, so that the alarm information read in the read B1, for example, the logical value "1" is written in the second memory area 16B. As a result, the fact that the occurrence state is continuing (the continuity of the alarm state) can be handed over to the second processing system 18A. Therefore, in the transfer of the alarm information from the first processing system 12 to the second processing system 18, there is no omission in the delivery thereof.

Second Embodiment FIG. 8 is a diagram showing the electrical configuration of an asynchronous inter-system information transfer apparatus according to the second embodiment of the present invention, and FIG. 9 is provided in the same asynchronous inter-system information transfer apparatus. Or recovery of alarm information written in the first and second memory areas in a state in which the access to the first memory area of the memory is irregular and the access time interval to the second memory area is constant. 10 is a time sequence for reading the alarm information from the first and second memory areas and writing the alarm information to the second memory area in (1) of FIG. 9, and FIG. Writing alarm information to the first and second memory areas in (2) in FIG. 9 and the first and second
12 is a time sequence for reading the alarm information from the memory area of FIG. 12, FIG. 12 is a diagram illustrating the writing of the alarm information to the first and second memory areas in (3) of FIG.
13 is a time sequence for reading the alarm information from the memory area of FIG. 13, FIG. 13 is a timing sequence of writing the alarm information to the first and second memory areas in (4) of FIG.
14 is a time sequence for reading the alarm information from the memory area of FIG. 14, and FIG. 14 is a timing sequence for reading the alarm information from the first and second memory areas in (5) in FIG.
And a time sequence for writing alarm information to the second memory area.

The configuration of this example is greatly different from that of the first embodiment described above, in that the first processing system and the second processing system are not provided with a time relationship. Is. That is, the asynchronous processing system information transfer apparatus 10A is
Similar to the first embodiment, the first processing system 12 and the memory 1
6, the second processing system 18A, and the access arbitration circuit 20A
It is composed of and.

The second processing system 18A makes a read access request to the memory 16 for the first memory area 16A and the second memory area 16B, and the second memory area 16B, as in the first embodiment. And write access request to. As the read access request to the first memory area 16A, in addition to the read access request of the read B1 of the first embodiment, the read access request of the read B4 after the write B3 is added, and the second memory area 16B. Read B as a write access request to
The difference is that a write access request of writing B5 to the second memory area 16B of the alarm information when the alarm information read in 4 is "1" is added.

The access arbitration circuit 20A outputs 2 from the access request output 12A of the first processing system 12.
Arbitration of contention between one write access request and three read access requests and two write access requests that are periodically issued asynchronously from the access request output 18A1 of the second processing system 18 to the first processing system 12 is performed. There is a difference in that either one of the two processing systems is allowed to access the memory 16.

These access conflicts are due to the time relationship as in the first embodiment, that is, the writing to the first memory area 16A and the writing to the second memory area 16B by the first processing system 12. The time T between the second processing system 1
8A, the time between the read time from the first memory area 16A and the read time from the second memory area 16B per unit time, the read time from the second memory area 16B, and the second processing system. Second memory area 1 of alarm information read from the first memory area 16A by 18A
Writing to the first memory area 16A and the second memory area 16B by the first processing system 12 in a state in which there is no relation of being larger than the sum of the time of writing to 6B and the time of writing (FIG. 11, FIG. 12 and A1 and A2 in FIG. 13),
Reading from the second memory area 16B and the first memory area 16A by the second processing system 18A (B1, B2, B4 in FIGS. 10 to 14) and the second memory area by the second processing system 18A. Writing to 16B (FIGS. 11 and 1)
3, B5) in FIG. 14, and the access arbitration circuit 20A arbitrates the competition between access requests that occur when performing each of these operations.

Next, the operation of this example will be described with reference to FIGS. Asynchronous information transfer device 10
For the convenience of explaining the operation of A, the transmission line 14 is in a normal transmission state in which an alarm state is not generated, that is, initially in the normal transmission state, or an alarm state is generated once. However, the case where the alarm information is handed over from the first processing system 12 to the second processing system 18A in the normal transmission state in which the alarm state is recovered (hereinafter referred to as the first transmission state) will be described. This first transmission state is (1) in FIG.
, And its detailed time sequence is shown in FIG. In addition to the above-mentioned first transmission state, FIG. 9 shows second to fifth transmission states which will be described later. In any of these cases, (a) shows the first memory area 16A.
Shows alarm information stored in or stored in
(b) shows alarm information stored in or stored in the second memory area 16B.

In the first transmission state, neither the alarm state is generated nor the recovery thereof is detected, so that the write access request from the first processing system 12 is not generated. Therefore, writing from the first processing system 12 to the first memory area 16A and the second memory area 16B of the memory 16 is not performed.

However, the first memory area 1 of the memory 16
6A for periodical reading per unit time (B in FIG. 10)
1), the read time from the second memory area 16B (B2 in FIG. 10) and the read time B2 from the second memory area 16B at the time when a predetermined first time has elapsed from the read Writing the alarm information read from the first memory area 16A and held in the register to the second memory area 16B at the time when the second time that has been determined in advance has passed (B3 in FIG. 10), No. 2
Read from the first memory area 16A (B4 in FIG. 10) at the time when a predetermined third time has elapsed from the time when the write B3 was performed to the memory area 16B of The second memory area 16 of the alarm information read out by the reading B4 and held in the register at the time when the determined fourth time has elapsed
Writing B5 to B is performed by the second processing system 18A. The first to fifth times may be the same time or different times. The total time of the first to fifth times is smaller than the above-described periodic unit time.

The time sequence of reading and writing by the second processing system 18A is shown in FIG.
The operation will be described with reference to FIG. In FIG. 10, (a) shows that the alarm information “0” is continuously stored in the first memory area 16A, and FIG.
3 (b) indicates that the alarm information "0" is continuously stored in the second memory area 16B.

As described above, the transmission state of the transmission line 14 is the above-mentioned first transmission state, and the write access request is not issued from the access request output 12A of the first processing system 12 to the access arbitration circuit 20A. Therefore, as shown in (a) of FIG. 10, the alarm information of the first memory area 16A has a logical value “0”, and the logical value cannot be changed as long as the above-mentioned first transmission state continues. Absent. When an access request is issued from the access request output 18A1 of the second processing system 18A to the access arbitration circuit 20, the second processing system 18A is allowed to access the memory 16. The second processing system 18A performs a periodic read B1 from the first memory area 16A of the memory 16 for each unit time. The alarm information is held in the register of the second processing system 18A. At the time when the first time has elapsed from this reading, the same reading B2 from the second memory area 16B is performed.
Is done.

The alarm information read in the readings B1 and B2, that is, the logical sum of the logical values "0" is taken by the second processing system 18A. Since the logical sum is "0", the occurrence of the alarm state is delivered to the second processing system 18A.
That is, the continuity of the alarm state is handed over to the second processing system 18A. If the alarm state has not occurred, the second processing system 18
It is not counted by the counting means A. Then, the count value is compared with the threshold value at every periodic unit time. When the count value is larger than the threshold value, it is displayed on the monitor display device that the transmission line 14 is in an error state.
When the count value is less than or equal to the threshold value, the number of times the alarm state has occurred is displayed on the monitor display device.

In this first transmission state, the first processing system 12
Therefore, write B3 is performed without performing write A2. In addition to this, since the alarm information read by the read B4 is "0", the write B5 is not performed. By avoiding such access conflict, there is no omission in passing the alarm information from the first processing system 12 to the second processing system 18A.

Next, an alarm condition occurs on the transmission line 14 in which the above-mentioned first transmission condition continues, and the first processing system 1
2, the alarm status is detected and alarm information "1"
In the second transmission state in which the first processing system 1 is generated.
A case where alarm information is passed from 2 to the second processing system 18A will be described. This transmission state is shown in (2) of FIG.
, And its detailed time sequence is shown in FIG. In FIG. 11, (a) shows that the alarm information “0” is stored in the first memory area 16A and the alarm information is stored in the first memory area 16A when an alarm state occurs in the transmission line 14 thereafter. The stored alarm information is shown, and (b) shows the second
The alarm information "0" is stored in the memory area 16B of the first memory area 16B, and the alarm information stored in the first memory area 16B when the alarm state occurs in the transmission path 14 thereafter is shown. In this transmission state, the alarm information generated from the first processing system 12 is written in the first memory area 16A and the second memory area 16B (A1 and A in FIG. 11).
2) and reading of alarm information from the first memory area 16A and the second memory area 16B (B1 and B in FIG. 11).
2) and writing the alarm information read from the first memory area 16A to the second memory area 16B (B in FIG. 11).
3), reading the alarm information from the first memory area 16A (B4 in FIG. 11), and to the second memory area 16B of the alarm information read from the first memory area 16A and held in the register. Is written (B5 in FIG. 11).

In FIG. 11, write A1 and read B1
And write A2 and write B2 compete with each other. These conflicts are caused by the access arbitration circuit 20A.
Is arbitrated by. The read B1 is prioritized over the write A1, and the write A1 by the first processing system 12 is performed after the read B1 by the second processing system 18A is completed. The alarm information read in the read B1 is the second
It is held in the register of the processing system 18A. Also, the read B2 is prioritized over the write A2, and the second processing system 1
After the read B2 by 8A is completed, the write A2 by the first processing system 12 is performed.

The logical sum of the alarm information read in the read B1 and held in the register and the alarm information read in the read B2, that is, the logical sum of the logical values "0" is the second processing. Taken with system 18A. The logical sum is
Since it is "0", the occurrence of the alarm state is passed to the second processing system 18A. That is, the continuity of the alarm state is handed over to the second processing system 18A. The non-occurrence of this alarm state is not counted by the counting means of the second processing system 18A. Then, the count value is compared with the threshold value at every periodic unit time. If the count value is greater than the threshold value,
It is displayed on the monitor display device that the transmission line 14 is in an error state. When the count value is less than or equal to the threshold value, the number of times the alarm state has occurred is displayed on the monitor display device.

In the second transmission state, after the writing A2 is performed from the first processing system 12, the alarm information held in the register is written B3 in the second memory area 16B. In addition to this, read B4
Since the alarm information read by and held in the register is "1", writing B5 is performed. Then, the write B3 similar to that described in the first transfer state is performed, but the read B4 and the write B5 are performed by the second processing system 18A,
Even if the alarm information in the second memory area 16B is rewritten to "0" by the write B3, the alarm information "1" read by the read B4 is written back to the second memory area 16B by the write B5. . Therefore, the alarm information written in the second memory area 16B,
For example, the logical value “1” will not be rewritten with the alarm information read in the read B1, for example, the logical value “0”. Therefore, since such access conflict is avoided, there is no omission in the delivery of the alarm information from the first processing system 12 to the second processing system 18A.

Next, in the case where the alarm state is generated and then the alarm state is handed over from the first processing system 12 to the second processing system 18A in the third transmission state occurring near the time when the alarm state is recovered explain. This transmission state is shown in FIG.
(3), and the detailed time sequence thereof is shown in FIG. In FIG. 12, (a) shows that the alarm information “1” is stored in the first memory area 16A, and when the alarm state is recovered in the transmission line 14 thereafter, the alarm information “1” is stored in the first memory area 16A. Indicates the stored alarm information, (b)
Indicates that the alarm information “1” is continuously stored in the second memory area 16B, and when the alarm state is recovered in the transmission line 14 thereafter, the alarm information stored in the first memory area 16B. Indicates. In this third transmission state, the first
Writing the alarm information generated from the processing system 12 of the above into the first memory area 16A (A1 of FIG. 12) and reading the alarm information from the first memory area 16A and the second memory area 16B (see FIG. 12). B1 and B2), and the alarm information read from the first memory area 16A to the second memory area 16B (B3 in FIG. 12) and the alarm information read from the first memory area 16A (see FIG. 12 B
4) and are performed.

In FIG. 12, write A1 and read B1
Shows the case where and conflict. Write A1 and read B1
, The read B1 by the second processing system 18A is preferentially performed by the arbitration of the access arbitration circuit 20A, and the alarm information is stored in the register of the second processing system 18A as described above. Retained. The reading B1
After the completion of the writing, the writing A1 by the first processing system 12
Is done.

Then, read B2, write B3, and read B4 similar to those described in the first transfer state.
Is done. The alarm information read by the reading B4 is held in the register of the second processing system 18A. In the third transfer state, unlike the first and second transfer states, the logical sum of the alarm information read in the read B1 and held in the register and the alarm information read in the read B2, That is, the logical sum of the logical values "1" is obtained by the second processing system 18A. The logical sum is "1"
Therefore, the occurrence of the alarm state is handed over to the second processing system 18A. That is, the continuity of the alarm state is handed over to the second processing system 18A. The occurrence of this alarm condition is the second
In the counting means of the processing system 18A, the count value is compared with the threshold value. When the count value is larger than the threshold value, it is displayed on the monitor display device that the transmission line 14 is in an error state. When the count value is less than or equal to the threshold value, the number of times the alarm state has occurred is displayed on the monitor display device.

In this third transmission state, since the writing A2 is not performed from the first processing system 12, the writing B3 performed after the above-mentioned reading B2 is the access request as described in the second transmission state. It is done without the issue of contention. In addition to this, read B4
Since the alarm information read by is "0", writing B5 is not performed. By avoiding such access conflict, there is no omission in passing the alarm information from the first processing system 12 to the second processing system 18A.

Next, in the fourth transmission state in which the alarm state that has occurred is recovered and then the alarm state has occurred,
A case where the occurrence of the alarm state from the first processing system 12 to the second processing system 18A is handed over will be described. This transmission state is shown in (4) of FIG. 9, and its detailed time sequence is shown in FIG. In (a) of FIG. 13, the alarm information “0” is continuously stored in the first memory area 16A,
The alarm information stored in the first memory area 16A when an alarm state occurs in the transmission line 14 thereafter is shown.
In (b), the alarm information "1" is continuously stored in the second memory area 16B, and is stored in the first memory area 16B when an alarm condition occurs in the transmission line 14 thereafter. It shows the alarm information.

In the fourth transmission state, the first memory area 1 for the alarm information generated from the first processing system 12 is used.
Writing to 6A and the second memory area 16B (see FIG. 13).
A1 and A2) of the first memory area 16A and the second memory area 16A
Of alarm information from the memory area 16B of the
B1 and B2), and writing of the alarm information read from the first memory area 16A and held in the register to the second memory area 16B (B3 in FIG. 13), and from the first memory area 16A. Of the alarm information (B4 in FIG. 13) and the second memory area 16 of the alarm information read from the first memory area 16A and held in the register.
Writing to B (B5 in FIG. 13) is performed.

In FIG. 13, write A1 and read B1
And the read A2 conflict with the write A2. The conflict between write A1 and read B1 is
As described above, the access arbitration circuit 20A arbitrates, the read B1 by the second processing system 18A is preferentially performed, and the alarm information is held in the register of the second processing system 18A. After the read B1 is completed, the write A1 by the first processing system 12 is performed. Similarly, the competition between the write A2 and the read B2 is arbitrated by the access arbitration circuit 20, the read B2 by the second processing system 18A is preferentially performed, and after the read B2 is completed, the first processing system is completed. Writing A2 by 12 is performed.

The logical value of the alarm information read in the above-mentioned readings B1 and B2, that is, the logical sum of the logical value "0" in the reading B1 and the logical value "1" in the reading B2 is the second processing. Taken with system 18A. Since the logical sum is "1", the occurrence of the alarm state is handed over to the second processing system 18A. That is, the continuity of the alarm state is handed over to the second processing system 18A.

This alarm condition is generated by the second processing system 18
It is counted in the counting means of A, and the counted value is compared with a threshold value. If the count value is greater than the threshold value,
It is displayed on the monitor display device that the transmission line 14 is in an error state. When the count value is less than or equal to the threshold value, the number of times the alarm state has occurred is displayed on the monitor display device.

Then, the write B3 similar to that described in the first transfer state is performed, but the second processing system 18 is used.
Read B4 is performed by A, and write B5
Therefore, even if the alarm information in the second memory area 16B is rewritten to "0" by the write B3,
Since the alarm information "1" read by the read B4 is written in the second memory area 16B by the write B5, the alarm information of the second memory area 16B is written back to "1". Therefore, the alarm information written in the second memory area 16B by the writing A2,
For example, the logical value "1" will not be rewritten with the alarm information read in the read B1, that is, the logical value "0". That is, the continuity of the alarm state is handed over to the second processing system 18A. Therefore, by avoiding such access conflict, the first processing system 12 to the second processing system 12
There is no omission in delivering the alarm information to the processing system 18A.

Next, a case will be described in which the occurrence of the alarm state is handed over from the first processing system 12 to the second processing system 18A in the fifth transmission state in which the alarm state is continuously generated. This transmission state is shown in (5) of FIG. 9, and its detailed time sequence is shown in FIG. Of FIG.
(a) shows a case where the alarm information “1” is stored in the first memory area 16A and the state continues, and FIG.
(b) shows the case where the alarm information "1" is stored in the second memory area 16B and the state is continued.

In this fifth transmission state, neither a new generation of the alarm state nor its recovery is detected, so that the write access request from the first processing system 12 is not generated. Therefore, from the first processing system 12 to the first memory 16
Is not written to the memory area 16A and the second memory area 16B.

However, the first memory area 1 of the memory 16
6A for periodical reading per unit time (B in FIG. 14)
1), reading from the second memory area 16B (B2 in FIG. 14) at the time when the first time described above has elapsed from the reading time, and the time from the time when reading from the first memory area 16A The second memory area 1 of the alarm information read from the first memory area 16A and held in the register at the time when the second time has elapsed
6B (B3 in FIG. 14) and reading from the first memory area 16A at the time when the above-described third time has elapsed from the time when writing to the second memory area 16B (see FIG. 14). B4) and the writing of the alarm information read out in B4 and held in the register to the second memory area 16B (B5 in FIG. 14) is the second.
Processing system 18A.

FIG. 14 shows a time sequence of reading and writing by the second processing system 18A.
The operation will be described with reference to FIG. In FIG. 14, since the transmission state of the transmission line 14 is the above-mentioned fifth transmission state, the first processing system 12 does not detect the alarm state of the transmission line 14. Therefore, the alarm information stored in the memory area 16A by the first processing system 12 is as shown in FIG.
(A), the logical value is “1”, and as long as the fifth transmission state described above continues, there is no change in the logical value.

Further, as described above, since the access request output 12A of the first processing system 12 does not output the access request to the access arbitration circuit 20A, the access arbitration circuit 20A causes the memory 16 in the second processing system 18A. Access request to the second processing system 18A is permitted, the second processing system 18A performs reading B1 from the first memory area 16A of the memory 16 for each unit time, and the alarm information is stored in the register of the second processing system 18A. Retained. The same reading B2 is performed from the second memory area 16B at the time when the first time has elapsed from the reading time of the reading B1.

The alarm information "1" read by the read B2 is logically ORed with the alarm information supplied to the second processing system 18 and held in the register. This logical sum is "1", and this logical sum "1" is during the time from the previous write B3 to the current read B2.
It means that the alarm state on the transmission line 14 was passed to the second processing system 18A from the first processing system 12, that is, the passing of the generated state. The occurrence of this alarm state is counted in the counting means of the second processing system 18A, and the counted value is compared with the threshold value. When the count value is larger than the threshold value, it is displayed on the monitor display device that the transmission line 14 is in an error state. When the count value is less than or equal to the threshold value, the number of times the alarm state has occurred is displayed on the monitor display device.

Then, at the time when the second time has passed from the time when the data was read from the first memory area 16A,
Writing B3 of the alarm information read from the first memory area 16A and held in the register to the second memory area 16B is performed. Furthermore, at the time when the third time has elapsed from the time when the writing B3 was performed to the second memory area 16B, the reading B4 is performed from the first memory area 16A and the alarm information read at the reading B4 is Since the alarm information is "1", the alarm information is stored in the second memory area 16 at the time when the fourth time has elapsed from the time when the reading B4 was performed.
It is written in B (B5 in FIG. 14). Therefore, since the alarm information "1" is written in the second memory area 16B by the write B3 and the alarm information read by the read B4 is "1", the alarm information is read in the second memory area 16B by the write B5. The alarm information read by B4 is written. As a result, the continuity of the alarm information from the first processing system 12 to the second processing system 18A is taken over. Therefore, in this transmission state, access conflict does not occur and the first processing system 12
There is no omission in passing the alarm information from the second processing system 18A to the second processing system 18A.

Although the embodiments of the present invention have been described in detail above with reference to the drawings, the specific configuration of the present invention is not limited to these embodiments, and does not depart from the scope of the present invention. Even if there are changes in the design, etc., they are included in this invention. For example, the present invention can be equally applied to the case of transferring information other than the alarm information from the first processing system to the second processing system. Further, as a substitute for the memory, an accessible register may be used. Further, the function of the asynchronous information transfer device may be realized by a program.

[0095]

As described above, according to the configuration of the present invention, the information received by the first processing system is temporally transferred from the first processing system to the first storage means and the second storage means. The two storage means are sequentially stored with a shift, and the two storage means are sequentially read by the second processing system that operates cyclically asynchronously with the first processing system, and information is stored based on the two read information. Since the information is read out from the first storage means and stored in the second storage means so that the continuity of the information is transferred to the second processing system, the second processing system transfers the second processing system to the second processing system.
It is possible to prevent the leakage of information from being transferred to the processing system. If a time constraint is given during writing and reading by the first processing system and the second processing system to eliminate leakage of information transfer, the speed of the transfer process becomes faster. Further, when eliminating leakage of information transfer, there is an advantage that the above-mentioned time constraint is eliminated by sacrificing the speedup of the transfer process.

[Brief description of drawings]

FIG. 1 is a diagram showing an electrical configuration of an asynchronous inter-system information transfer device according to a first embodiment of the present invention.

FIG. 2 is a time sequence of generation or recovery of alarm information written in a memory provided in the asynchronous inter-system information transfer device.

FIG. 3 is a time sequence of reading alarm information from the first and second memory areas and writing alarm information to the second memory area in (1) of FIG.

4 is a time sequence of writing alarm information to and reading alarm information from the first and second memory areas in (2) of FIG.

FIG. 5 is a time sequence of writing alarm information to and reading alarm information from the first and second memory areas in (3) of FIG.

FIG. 6 is a time sequence of writing alarm information to and reading alarm information from the first and second memory areas in (4) of FIG.

FIG. 7 is a time sequence of (5) in FIG. 2 for reading the alarm information from the first and second memory areas and writing the alarm information to the second memory area.

FIG. 8 is a diagram showing an electrical configuration of an asynchronous inter-system information transfer device which is a second embodiment of the present invention.

FIG. 9 is a time sequence of generation or recovery of alarm information written in a memory provided in the asynchronous inter-system information transfer device.

FIG. 10 is a time sequence of (1) in FIG. 9 for reading alarm information from the first and second memory areas and writing alarm information to the second memory area.

FIG. 11 is a time sequence of writing alarm information to and reading alarm information from the first and second memory areas in (2) of FIG. 9.

FIG. 12 is a time sequence of writing alarm information to and reading alarm information from the first and second memory areas in (3) of FIG. 9.

13 is a time sequence of writing alarm information to and reading alarm information from the first and second memory areas in (4) of FIG.

FIG. 14 is a time sequence of (5) in FIG. 9 for reading the alarm information from the first and second memory areas and writing the alarm information into them.

FIG. 15 is a diagram showing an electrical configuration of an asynchronous inter-system alarm information transfer device.

FIG. 16 is a time sequence when alarm information can be normally transferred from the first processing system to the second processing system in the same asynchronous inter-system alarm information transfer device.

FIG. 17 is a time sequence when the alarm information transfer device between asynchronous systems cannot normally transfer alarm information from the first processing system to the second processing system.

[Explanation of symbols]

12 First processing system 14 Transmission line 16 memory 16A First memory area (first storage means) 16B Second memory area (second storage means) 18, 18A Second processing system (delivery means) 20 Access arbitration circuit (control means)

─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-4-276933 (JP, A) JP-A-7-288509 (JP, A) JP-A-7-254889 (JP, A) JP-A-6- 291742 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 13/08 G06F 13/38 340 H04J 3/14

Claims (10)

(57) [Claims] 1. A second processing system that periodically operates asynchronously with the first processing system based on information obtained by detecting the occurrence or recovery of the state of the transmission path in a first processing system to which the transmission path is connected. A method for transferring information between asynchronous systems, wherein the first processing system detects the occurrence or recovery of the state of the transmission path every time the first processing system detects the information obtained at the detection timing. The information stored in the storage means and stored in the first storage means at a write timing after a lapse of a first predetermined time within the periodic operation time of the second processing system from the detection timing is stored in the second storage means. Of the second processing system for each cyclic operation, the information stored in the first storage means up to the previous cyclic operation is read before being stored, and the write timing is set. Before and from the read time 2 when a predetermined time elapses, the information stored in the second storage unit is read by the previous cyclic operation, and the occurrence or recovery information is read based on the read two pieces of information. The data is delivered to the second processing system, and every time the second processing system cyclically operates, a third time is read from the time when the information is read from the second storage means.
The method for transferring information between asynchronous systems, characterized in that the information read from the first storage means is overwritten in the second storage means when a predetermined time has passed. 2. By setting the first predetermined time period to be larger than the sum of the second predetermined time period and the third predetermined time period, the overwriting is performed by excluding the conflict between the write timing and the overwriting. 2. The asynchronous inter-system information transfer method according to claim 1, wherein the information stored in the second storage means is prevented from being rewritten at the write timing. 3. After the overwriting is performed, a periodical operation of the second processing system is performed from the first storage unit when a fourth predetermined time has elapsed from the time when the overwriting was performed. Re-reading and re-overwriting of the information obtained by the re-reading into the second storage means after a lapse of a fifth predetermined time from the re-reading time are performed, and the conflict between the write timing and the overwrite 2. The asynchronous inter-system information transfer method according to claim 1, wherein the information in the second storage means rewritten by the above is rewritten by the rereading and the rewriting. 4. The delivery of information obtained by the generation or the recovery based on the two pieces of information to the second processing system is performed by taking a logical sum of the two pieces of information. Item 1. The asynchronous inter-system information transfer method according to Item 1, 2 or 3. 5. A second processing system that periodically operates asynchronously with the first processing system based on information obtained by detecting the occurrence or recovery of the state of the transmission path in the first processing system to which the transmission path is connected. A non-synchronous inter-system information transfer device for delivering to the processing system, the information processing apparatus stores the information obtained at the detection timing each time the first processing system detects occurrence or recovery of the state of the transmission path. A first storage means, and a first storage means for storing the information stored in the first storage means at a write timing after a lapse of a first predetermined time within the periodic operation time of the second processing system from the detection timing. 2 storage means, and for each cyclic operation of the second processing system, reading of the information stored in the first storage means up to the previous cyclic operation before storing the information, The write timing comes before the read time. From the time when the second predetermined time elapses to the previous periodic operation, the reading of the information stored in the second storage means and the time when the information is read from the second storage means reaches the third predetermined time. Based on the control means for controlling access conflict with the overwriting of the information read from the first storage means to the second storage means at the passage of time, and the two read information. A non-synchronous inter-system information transfer device, comprising: delivery means for delivering the information on the occurrence or the recovery to the second processing system. 6. The control means sets a sum of the second predetermined time and the third predetermined time smaller than the first predetermined time, thereby eliminating the conflict between the write timing and the overwrite. 6. The inter-asynchronous information transfer apparatus according to claim 5, wherein the information stored in the second storage unit is prevented from being rewritten at the write timing due to the overwrite. 7. The control means, after the overwriting is performed, the first predetermined time after a lapse of a fourth predetermined time from the time when the overwriting is performed for each periodic operation of the second processing system.
Re-reading from the storage means and re-overwriting the second storage means with the information obtained by the re-reading after a lapse of a fifth predetermined time from the re-reading time. 6. The asynchronous inter-system information transfer device according to claim 5, wherein the information in the second storage unit rewritten by the conflict with the overwrite is rewritten by the rereading and the rewriting. 8. The asynchronous inter-system information transfer device according to claim 5, 6 or 7, wherein said delivery means performs a delivery by taking a logical sum of the two pieces of information. 9. A recording medium characterized in that a control program for realizing the asynchronous inter-system information transfer method according to claim 1, 2, 3 or 4 is recorded in a computer. 10. A recording medium characterized in that a control program for realizing the function of the asynchronous inter-system information transfer device according to claim 5, 6, 7 or 8 is recorded in a computer.