JP3428447B2 - Frame multiplex protocol processing method and frame multiplex protocol processing method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame multiplex protocol processing method and a frame multiplex protocol processing method for executing frame multiplex protocol processing by applying frame relay technology.

[0002]

2. Description of the Related Art In recent years, LAPD (Link Access Procedure)
e on the D-channel) recommendation, LAPB (Link Access Pr)
ocedure balanced mode) In the protocol such as recommendation, the frame relay technology is applied to perform the frame multiplex processing, and several hundred to several thousand links are terminated by one LSI as compared with the conventional one LSI by one LSI. The high frame multiplex protocol processing method has been widely used.

In the case of LAPD multiplexing, the SABME is set in the control field when the partner operation mode setting waiting state is not set.
When a frame in which the (Set Asynchronous Balanced Mode Extended) command is set is received from the partner terminal, the frame in which the DM (Disconnected Mode) command is set in the control field is returned to the partner terminal to reject the link setting request. If the operation according to such a recommendation is performed, a malicious call (subscriber terminal by an easy terminal program) causes DM
Upon receiving the frame, the SABME frame is immediately retransmitted without limitation.

[0004]

As described above, in the conventional frame multiplex protocol processing method, the processing capability of the means for executing the frame multiplex protocol processing by the short frame transmission / reception of SABME, DM accompanying the link setting request rejection is used. As a result, the whole frame multiplex protocol processing system becomes unstable, and in the worst case, there is a problem that a failure state occurs. The present invention has been made in order to solve the above problems, and avoids the problem of system down that occurs due to the operation according to the conventional recommendation, and there is a request for waiting for the partner operation mode setting from the host software of the line interface. An object of the present invention is to provide a frame multiplex protocol processing method and a frame multiplex protocol processing method capable of efficiently allocating processing capability to DLCI.

[0005]

A frame multiplex protocol processing method according to the present invention comprises a plurality of frame multiplexing protocol processing methods .
A line provided in a frame relay exchange that accommodates terminals
In the frame reception interface section in each line interface
In addition, the received frame corresponding to the DLCI for which the partner software operation mode setting waiting request from the upper software has not been generated is discarded at the hardware level. As a result, the load of layer 2 protocol processing can be eliminated. Further, according to the frame multiplex protocol processing method of the present invention, as described in claim 2, the means for discarding the received frame corresponding to the DLCI for which the partner software operation mode setting wait request from the higher-level software has not been issued at the hardware level. Is to have. Further, claim 3
As described in, the DLCI register for storing the DLCI for which the partner operation mode setting wait request is issued by the host software of the line corresponding unit, and whether or not the partner operation mode setting wait, which is set at the same time as this DLCI, is set. A state value register for storing the indicated state value, a DLCI conversion circuit for extracting the DLCI from the received frame, and a DLCI
A memory that stores the state value from the state value register in the address corresponding to the DLCI output from the register and reads the state value from the address corresponding to the DLCI output from the DLCI conversion circuit, and the state value output from the memory are When it is not waiting for the partner operation mode setting,
A line discarding unit is provided with a frame discarding circuit that discards the received frame corresponding to this state value.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a frame reception interface unit of a line interface unit according to an embodiment of the present invention. The frame reception interface unit of the present embodiment is provided in each line corresponding unit provided for each line in a frame relay exchange that accommodates a plurality of terminals.

The operation of the frame multiplex protocol processing method according to this embodiment will be described below with reference to the frame multiplex protocol processing sequence of FIG. When the line interface starts up and becomes ready to receive the received frame from the partner terminal, the partner terminal sets SABME (Set Alignment) in the control field for data link setting, as shown in FIG.
chronous Balanced Mode Extended) command set frame (hereinafter referred to as SABME frame) is transmitted.

The transmission of this SABME frame is performed by the LAP.
D (Link Access Procedure on the D-channel) or LAPB (Link Access Procedure Balanced mode)
According to the recommendation, after the response monitoring timer (T203 timer) times out, the maximum number of retransmissions is retransmitted. The line interface at the time of activation is in a state of discarding all SABME frames from the partner terminal.

The upper software of the line interface is the Data Link Connection Identifier.
, And hereinafter, will be referred to as DLCI), when the processing of the data link whose value is “y” can be accepted, as shown in FIG. 2, the partner operation mode setting waiting request of DLCI = y is issued to the layer 2 upper firmware. To publish.

In accordance with the above recommendation, the layer 2 upper firmware of the line interface issues a partner operation mode setting wait request of DLCI = y to a layer 2 data link controller (not shown) (hereinafter referred to as DLC).

When the DLC receives a request for waiting for setting of the partner operation mode of DLCI = y from the layer 2 upper firmware, it sets the reception enable information of DLCI = y in the reception interface section of FIG. A transition to the setting waiting state is made, and a normal response notifying that the transition to the partner operation mode setting waiting state has been completed is transmitted to the layer 2 upper layer firmware. And layer 2
When the upper firmware receives the response from the DLC, it sends a similar response to the software.

Now, the setting of the receivable information of DLCI = y for the reception interface section of FIG. 1 will be described. DLC is from layer 2 upper firmware to DLC
When a partner operation mode setting wait request with I = y is received, “y” is set in the DLCI register 1 as the value of DLCI to be set, and the partner is set as a 1-bit state value indicating whether or not the partner operation mode is set. The state value register 2 is set with "1" indicating that it is waiting for the operation mode setting.

The memory (register depending on the configuration) 4 is
The memory 4 is a memory for holding a 1-bit state value, and each address of the memory 4 corresponds to a specific DLCI. The selector 3 adds DL to the DLCI register 1.
When the CI is set and the state value is set in the state value register 2, the output of the DLCI register 1 is selected.
In this way, the DLCI set as the write address in the DLCI register 1 is input to the memory 4.

At this time, since the state value output from the state value register 2 is data-input to the memory 4, DL
The state value “1” from the state value register 2 is written to the address of the memory 4 corresponding to the DLCI from the CI register 1.

On the other hand, when the received frame data from the partner terminal is input, the data receiving circuit 5 outputs the data of the address field (hereinafter referred to as A field) of this frame to the A field DLCI conversion circuit 6, FIFO (first-in first-out memory) 7 for receiving frame data D
Output to. The A field DLCI conversion circuit 6 extracts the DLCI from the data of the A field.

The selector 3, when the DLCI is obtained by the A-field DLCI conversion circuit 6, receives the A-field DL.
The output of the CI conversion circuit 6 is selected. In this way, the DLCI as the read address output from the A field DLCI conversion circuit 6 is input to the memory 4. Memory 4
Outputs the state value stored in the address corresponding to the DLCI from the A field DLCI conversion circuit 6 to the frame discard circuit 8.

When the 1-bit status value read from the memory 4 is "0", that is, when the frame discard circuit 8 indicates that it is not waiting for the partner operation mode setting, the frame discard circuit 8 judges that the reception is discarded and the status value " DLCI corresponding to "0" (DL that became the read address when the status value "0" was read
Frame data D on the FIFO 7 specified by CI)
From the beginning to the end of the frame (that is, from the start flag to the end flag), and discard.

When the 1-bit state value read from the memory 4 is "1", that is, the frame discarding circuit 8 indicates that it is waiting for the partner operation mode setting, the frame discarding circuit 8 judges that reception is possible, No action is taken on the FIFO7. Therefore, the DLCI corresponding to the state value "1"
The frame data D on the FIFO 7 specified by (DLCI which became the read address when the state value “1” is read) is input to the DLC as it is.

In the example of FIG. 2, the receivable information (state value "1") is set only for the data link of DLCI = y, and the DLC
Since the receivable information is not set for the link of I = x, z (state value “0”), the SABME retransmitted from the partner terminal after the T203 timer timeout shown in FIG.
Among the frames, the SABME frame of DLCI = x, z is discarded by the reception interface unit of FIG.
Only the SABME frame with DLCI = y is passed to the DLC without being discarded by the reception interface unit.

DLC receives SAB of DLCI = y
Based on the data of the ME frame, the link setting process according to the above recommendation is performed, and a frame in which a UA (Unnumbered Acknowledge) response indicating that the link setting has been accepted is set in the control field is transmitted to the partner terminal, and the layer 2 The link setting notification of DLCI = y is passed to the upper firmware.

The layer 2 upper firmware is
Notify the link setting of DLCI = y to the upper software. After that, the link communication of DLCI = y is executed according to the protocol recommendation, and the received frame is subjected to the frame multiplex protocol processing by the upper software or the layer 2 upper firmware.

The FIFO 7 stores the frame data D in units of, for example, 1-bit serial or 8-bit parallel, but extracts the DLCI from the A field,
It suffices to have a capacity for a short processing time until the frame discarding circuit 8 can read out the state value corresponding to the extracted DLCI from the memory 4 and judge whether the frame discarding circuit 8 should discard the reception or can receive it based on this state value. As a result, the frame data can be delayed by the processing time, and the frame data can be prevented from being output to the DLC before the frame discard circuit 8 determines whether the reception is discarded or can be received.

Further, in the frame receiving interface section at the time of activation, all the state values of the memory 4 need to be "0" indicating reception discard. Therefore, DLC
As the initial settings at the time of start-up, by repeating the DLCI setting in the DLCI register 1 and the state value “0” setting in the state value register 2 for a predetermined DLCI, these D
All the state values of each address of the memory 4 corresponding to the LCI are reset.

As described above, according to the present invention, the line interface (depending on the scale, LSI / package / module) is added to the frame receiving interface unit of the line interface that executes the frame multiplex protocol processing by applying the frame relay technique.
It is characterized in that hardware means for discarding all received frames for each DLCI at the hardware level is provided without a request for waiting for setting of a partner operation mode from the upper software.

In order to avoid the problem caused by the operation according to the conventional recommendation, the SABME retransmission is expected in accordance with the maximum number of retransmissions after the response monitoring timer times out on the partner terminal side, and the waiting for the partner operation mode setting described above is waited for. Performs an operation at the hardware level to discard all unsolicited received frames for an individual DLCI.

Therefore, since the system itself multi-processes the protocol processing only for the links to be processed, there is no problem of system down due to malicious calls, and only the recommendation processing (DM frame transmission) for the unterminated links is not performed. In addition, since the layer 2 process for discarding the received frame is not necessary, it is possible to efficiently allocate the processing capacity to the terminating link.

[0027]

According to the present invention, the DLC in which the request for waiting for the partner operation mode setting from the upper software has not been issued.
Since the received frame corresponding to I is discarded at the hardware level, the protocol processing of only the link that the system itself should process (the link in which the request to wait for setting the other operation mode has occurred) is multi-processed. There is no problem of system down due to. Further, not only does the recommendation process for the link that does not terminate (the link for which the partner operation mode setting wait request has not occurred) not be performed, but the layer 2 process that discards the received frame is also unnecessary, so that it is efficient for the terminated link. It becomes possible to allocate processing capacity well.

[Brief description of drawings]

FIG. 1 is a block diagram of a frame reception interface unit of a line interface unit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a frame multiplex protocol processing sequence.

[Explanation of symbols]

1 ... DLCI register, 2 ... state value register, 3 ... selector, 4 ... memory, 5 ... data receiving circuit, 6 ... A field DLCI conversion circuit, 7 ... FIFO, 8 ... frame discarding circuit.

Claims (3)

(57) [Claims] 1. A frame relay exchange accommodating a plurality of terminals.
Frame reception in the line-corresponding part for each line provided in the exchange
Hard in the interface section, a frame multiplexing protocol processing method for performing a frame multiplexing protocol processing by applying the frame relay technique, the received frame corresponding to the DLCI opponent operation mode setting wait request from the host software has not occurred A frame multiplex protocol processing method characterized by discarding at a wear level. 2. A frame relay exchange accommodating a plurality of terminals.
Frame reception in the line-corresponding part for each line provided in the exchange
Hard in the interface section, a frame multiplexing protocol processing method for executing a frame multiplexing protocol processing by applying the frame relay technique, the received frame corresponding to the DLCI opponent operation mode setting wait request from the host software has not occurred A frame multiplex protocol processing method having means for discarding at the wear level. 3. A DL for storing a DLCI for which a partner operation mode setting wait request has been issued by higher-order software of a line interface in a frame multiplex protocol processing method that executes frame multiplex protocol processing by applying frame relay technology.
CI register, status value register set at the same time as this DLCI for storing the status value indicating whether or not the partner operation mode is set, DLCI conversion circuit for extracting DLCI from the received frame, and output from DLCI register The state value from the state value register is stored in the address corresponding to the selected DLCI,
A memory that reads the status value from the address corresponding to the DLCI output from the I conversion circuit, and when the status value output from the memory indicates that it is not waiting for the partner operation mode setting, the received frame corresponding to this status value A frame multiplex protocol processing method, characterized in that a line discarding circuit is provided in a line interface.