JP3429070B2 - Switching device and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (asynchronous transfer mode) communication system in which ATM networks having different lengths, particularly, a 53 × 8 bit general ATM network and an ATM network having a unique cell structure are connected. Regarding Further, the present invention is
The present invention relates to a connection switching device and method using 53 × 8 bit general ATM network equipment in an ATM network having a unique cell structure.

[0002]

2. Description of the Related Art FIG. 1 shows a connection between a conventional ATM communication system and another network. In FIG. 1, 110 and 111 are non-ATM networks, and 106 is an ATM network. Reference numeral 101 denotes a cell assembling apparatus, which is used for the ATM network 106 and the non-ATM network 11
It is installed between 0 and 111 and mutually converts an information string in the non-ATM network and a cell which is a unit of information in the ATM network. The cell assembling apparatus 101 has a cell assembling circuit 102, a cell releasing circuit 103, and a header information circuit 104. The cell conversion circuit 102 converts information on the non-ATM line into cells. The cell release circuit 103 converts an ATM cell into a non-ATM line information string. The header information control circuit 104 is A
When a call is connected to the TM network 106, the cell header value is determined according to the call setting protocol, and the cell assembling circuit 102 and the cell releasing circuit 103 are notified of the cell header value.

FIG. 2 shows an AT using a 53-octet cell.
The data structure of an ATM cell used in the M network is shown. Consider a connection between a conventional non-ATM network and an ATM network. Non-ATM network 1
When it is determined that a call connection is made between the ATM network 111 and the ATM network 106, the ATM network consults the header information control circuit 104 with the control line to determine the header information.
The header information includes a call identification number and switching information for the connected call. Header information control circuit 1
04 sends the header information to the cell assembling circuit 102. The cellizing circuit 102 receives the cell header information and fills the cell header portion with this information as shown in FIG.

User information sent from the line of the non-ATM network 110 or 111 is filled in the information section of the ATM cell, and 5
In the case of a 3 × 8 bit cell, it is transmitted to the ATM network when the information part of 48 octets is filled. Conversely, ATM
When an ATM cell is sent from the network to the cell assembling device 101,
The cell release circuit 103 sends the information in the information section to the non-ATM line of the call corresponding to the cell header determined by the header information control circuit 104.

Thus, the non-ATM networks 110 and 111 are
The TM network 106 can be used as a relay network. By the way, there is a delay in converting a non-ATM information string into ATM cells. For example, 4 non-ATM lines of 64 kbps
When it is placed in the information part of an 8 × 8 bit cell, 6 ms is required for cell formation. If an information string obtained from a lower speed line is converted into an ATM cell, the cell formation delay will be further increased. Therefore, low speed (less than 64 kbps)
When converting the non-ATM network into the ATM network, it is desirable to use a cell having a smaller bit length without using the existing 53 × 8 bit cell in order to suppress the cell formation delay. So non-A
When the TM networks 110 and 111 are replaced by the ATM networks 1 and 2, 105 does not always use the same size cell as the 106 ATM network.

[0006]

However, conventionally, it has not been possible to transfer ATM cells between ATM networks having different cell lengths. An object of the present invention is to connect ATM networks having different cell lengths and use lines and equipment of other networks. In particular, the present invention enables connection between a 53 × 8 bit general ATM network and a local ATM network having a unique cell, and a 53 × 8 bit in an ATM network having a unique cell having a cell length of 53 × 8 bit or less. General AT
It is intended to enable the use of routing and equipment using a part of the M-network.

[0007]

In order to achieve such an object, the invention described in claim 1 is an ATM network using nbit (n is an integer) fixed length cells and an mbit (m is n).
(A larger integer) a switching device connected to an ATM network using fixed-length cells, and storing mapping information for storing mapping information for associating each bit of the nbit cell with each bit of the mbit cell And a means for transmitting a cell received from an ATM network using the nbit cell to an ATM network using the mbit cell, the header part of the nbit cell is
Map to the header part of the mbit cell, or
Is the header information determined in advance to the mbit cell.
And a part of or all of the information part of the information part of the nbit cell is mapped to a predetermined b of the information part of the mbit cell based on the mapping information.
When the cell received from the ATM network using the m-bit cell and the n-m mapping means for mapping to the it position is transmitted to the ATM network using the n- bit cell, the header part of the m-bit cell is set to the nbi
map to the header part of the cell of t, or
The determined header information is used as the header part of the n-bit cell.
And mn mapping means for mapping a part or all of the information part of the information part of the cell of the mbit to a predetermined bit position of the information part of the nbit cell based on the mapping information. It is characterized by having.

According to a second aspect of the present invention, in the switching device according to the first aspect, the mapping information storage means includes a plurality of types of mapping patterns and an identification code for identifying each of the plurality of types of mapping patterns.
And the nm mapping means comprises:
An identification code corresponding to the mapping pattern selected from among Tsu ping pattern transmitted according to the information part <br/> of the mbit cells, said m-n mapping means, the information part or al of the mbit cells corresponding to the identification information began to read
And performing mapping using the mapping pattern to be.

According to a third aspect of the present invention, switching is connected to an ATM network using nbit (n is an integer) fixed length cells and an ATM network using mbit (m is an integer larger than n) fixed length cells. A switching method applied to a device, wherein the switching device comprises the nbit
Mapping information for associating each bit of each cell of the cell with each bit of the cell of the mbit is stored in advance.
When the cell received from the ATM network using the bit cell is transmitted to the ATM network using the mbit cell,
The header part of the n-bit cell is replaced with the m-bit cell header.
Map to the header part of the
The header information that is stored in the header part of the mbit cell.
And , based on the mapping information, the nb
The information of part or all of the information part of the cell of it
an n-m mapping step of mapping to a predetermined bit position of the information part of the bit cell, and the mbi
The cell received from the ATM network using the cell of t is
When transmitting to the ATM network using the cell of bit, the
The header part of the mbit cell is
Map to header part or predetermined
Map the header information to the header part of the n-bit cell.
And the mbit based on the mapping information.
Information of part or all of the information part of the cell
and an mn mapping step for mapping to a predetermined bit position of the information portion of the t cell.

According to a fourth aspect of the present invention, in the switching method according to the third aspect, the mapping information includes a plurality of types of mapping patterns and an identification code for identifying each of the plurality of types of mapping patterns. ,
The n-m mapping step includes:
Pair mapping pattern selected from among Gupatan
Send describes an identification code to respond to the information part of the mbit cells, said m-n mapping step, the m
to respond to the information part or Ra読 identification information out only bit cell
And performing mapping using the mapping patterns that.

[0011]

According to the present invention, mb is transmitted from the n-bit cell AT network.
it cell n When sending an n-bit cell to the ATM network,
Information of a part or all of the bit cell is mapped to a predetermined bit position of the mbit cell and is routed as an mbit cell in the mbit cell ATM network. On the other hand, when transmitting from the mbit cell ATM network to the nbit cell ATM network, in reverse to the mapping pattern when it is sent to the mbit cell ATM network, a part or all of the necessary part of the mbit cell is mapped to the nbit cell. , N
It enables the use of bit cells in ATM networks.

Further, according to the present invention, b at the time of sending and receiving
A mapping pattern for identifying a plurality of mapping patterns and each mapping pattern is prepared in advance without predetermining the mapping pattern of the it position.
bit cell When sending an nbit cell to the ATM network,
Map a part or all of the information of the nbit cell to a predetermined bit position of the mbit cell, and describe the code that identifies the mapping pattern using the bit position that is not subject to the mapping of the mbit cell, mb
Routing in the it-cell ATM network.

A cell is transferred from an mbit cell ATM network to an nbit cell.
When transmitting to the cell ATM network, the identification code of the mapping pattern described above is read, the mapping pattern is discriminated, and conversely to the mapping pattern when it is transmitted to the mbit cell ATM network. Map all required parts to nbit cells. Therefore, ATM networks having different cell lengths can be connected.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings.

[Embodiment 1] FIG. 3 shows an ATM network (referred to as an mbit ATM network) in which an mbit cell is used and an nbit.
It is explanatory drawing which showed the connection with the ATM network (it calls a nbit ATM network) in which the cell of a cell is used. In FIG.
301 is a switching device of the present invention. A solid line extending from the switching device 301 to the outside represents a data communication line, and a broken line represents a control line. ATMs 310 and 311 are continuous or discontinuous n-bit fixed length cells (n is an integer)
A network, 303 is an ATM network of mbit fixed length cells (m is an integer larger than n).

FIG. 4 is a diagram for explaining a data flow when the switching device 301 of the present invention transmits a cell received from the n-bit cell ATM network to the m-bit cell ATM network. In FIG. 4, reference numeral 401 is a buffer for storing cells transmitted from the n-bit cell ATM network to the m-bit cell ATM network, 402 is a mapping circuit with a control function for performing mapping in bit units, and 403 is mbit after mapping. Cell A buffer for storing cells before being sent to the ATM network. A cell header information control circuit 404 communicates with the mbit cell ATM network and determines cell header information. A control circuit 405 controls each function. 401 to 405 are included in the switching device 301 of the present invention.

The processing of the switching device 301 of the present invention for the cells transmitted from the mbit cell ATM network to the nbit cell ATM network will be described with reference to FIG. In FIG. 5, 5
A buffer 01 stores a cell transmitted from the mbit cell ATM network to the nbit cell ATM network. Reference numeral 502 is a mapping circuit with a control function for performing mapping in units of bit, and 503 is a buffer for storing cells after being mapped and before being sent to the n-bit cell ATM network.
Reference numeral 504 is a cell header information receiving circuit for receiving and storing cell header information from the n-bit cell ATM network, and 505 is a control circuit for controlling each function. 501 to 505
Are included in the switching device 301 of the present invention.

The control method of this system will be described with reference to FIGS. As shown in FIG. 3, an n-bit cell ATM network 31
0 and 311 set up a call indicated by a solid line using the mbit cell ATM network 303 through the switching device 301 of the present invention. The header control circuit 404 is an nbitATM
The required header information is determined according to the call setup protocol with the network and the mbit cell ATM network. Depending on the network configuration, the cell header used in the other party's network may be used as it is or simply by bit mapping. In this case, it is not necessary to determine the header information. Whether or not it is necessary to determine the header information is notified from each network to the switching device via a control line.

The processing at the time of sending a cell from the n-bit cell ATM network to the m-bit cell ATM network will be described with reference to FIG. The n-bit cell is temporarily stored in the buffer 401.
The control circuit 405 uses the mapping circuit 402 to
Bit mapping to t cells is performed. Whether or not the header information prepared by the header information control circuit 404 is required is notified from the network, and if necessary, the header information control circuit 404 is applied to the header portion of the sending buffer 403 of the mbit cell at the time of mapping. Map header information of. If not necessary, the header information of the nbit cell is mapped to the header information part of the mbit cell.

The data of the information part is mapped from the buffer of the buffer 401 to the buffer 403 according to a predetermined pattern for each bit. On the mbit cell side, there is a bit that is excluded from the mapping target. Thus, some or all of the bits in the n-bit cell
After mapping, the buffer 403 sends the mbit cell to the mbit cell ATM network.

A process for transmitting an mbit cell to an nbit cell ATM network will be described with reference to FIG. The mbit cell received by the switching device 301 is the buffer 5
It is stored in 01. After this, the control circuit 505 sets mbit
Cell buffer 501 to nbit cell buffer 50
The mapping circuit 502 performs the reverse mapping of the mapping pattern which is predetermined when the data is sent to the mbit cell 3 to the ATM network.

When it is determined that the header information of the mbit cell can be used for the mapping as it is according to the notification from the network, the header information of the mbit cell is used as it is, as in the procedure described in FIG. When the cell header information cannot be realized by mapping, the cell header information previously determined between the n-bit cell ATM network and the header information control circuit 504 is taken out from the header information control circuit 504. This information is mapped as nbit cell header information instead of mbit cell header information. The cells of the buffer 503 thus formed are sent to the mbit cell ATM network.

[Second Embodiment] FIG. 6 is a functional explanatory diagram of a switching device used in the second embodiment. 6 is a diagram for explaining the function of the switching device 301 of FIG. 3 instead of FIG. 4 of the first embodiment, and is the same as FIG. 4 except that a circuit 601 is connected. A code generation circuit 601 generates a code corresponding to the mapping method notified from the control circuit 405.

FIG. 7 is a diagram for explaining the data flow in the switching device 301 of FIG. 3, and corresponds to FIG. 5 of the first embodiment. The configuration of FIG. 7 is the same as that of FIG. 5 except that the circuit 701 is connected. Reference numeral 701 is a judgment circuit for judging the mapping method from the code. The processes other than the processes performed by the code generation circuit 601 and the determination circuit 701 are all the same as in the first embodiment. Only the processing performed by the code generation circuit 601 and the determination circuit 701 will be described below.

In the first embodiment, a single mapping pattern is predetermined. In this method, multiple mapping patterns are prepared. The code generation circuit 601 prepares a plurality of mapping patterns and codes corresponding to them.
However, in the case of an nbit cell and an mbit cell, from the number of unused bits (m-nbit) at the time of cell replacement,
The maximum number of mapping patterns is 2 to the m-th power. The control circuit 405 determines which mapping pattern to use. Further, the mapping circuit 402 is controlled according to the determined pattern to perform mapping.

The control circuit 405 notifies the code generation circuit 601 of the mapping pattern. Code generation circuit 601
Generates a predetermined identification code corresponding to the notified mapping pattern. In an m-bit cell, transfer data is not mapped (m-n) bit
The position is determined in advance on the transmitting side and the receiving side. The control circuit 405 uses the mapping circuit 402 to map the identification code generated by the code generation circuit 601 to this position.

In FIG. 6, a shaded portion shows a bit position determined in advance for storing the identification code. The mbit cell created by mapping the transfer data and the identification code is sent to the mbit cell ATM network.

The processing of the switching device 301 which receives the mbit cell will be described with reference to FIG. The control circuit 505 on the receiving side reads the identification code from the bit position where the predetermined (mn) bit identification code is stored. The read identification code is stored in the determination circuit 701 using the mapping circuit 502. The determination circuit 701 is
The mapping pattern is determined based on the received identification code and the control circuit 505 is notified. The control circuit 505 is
Mapping is performed using the mapping circuit 502 based on the notified mapping pattern, and the original n-bit cell is restored.

[0029]

As described above, according to the present invention, the switching device of the present invention can be installed in an interface between ATM networks using cells having different bit lengths, and bit mapping can be performed according to a predetermined mapping method. . Further, according to the present invention, the method of the mapping method is changed to a predetermined code, and a free space b at the time of mapping is obtained.
This puts it on it, so the ATM using the shorter cell
It is possible to use the communication path and equipment of the ATM network using the longer cell in the network.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a connection configuration between an ATM network and a non-ATM network.

FIG. 2 is a configuration diagram of a 53-byte cell used in a general ATM network.

FIG. 3 is a connection diagram between different length cell ATM networks of the present invention.

FIG. 4 is an n-bit cell ATM of the switching device of the present invention.
It is a functional explanatory view in the direction transmitted from the network to the mbit cell ATM network.

FIG. 5: mbit cell ATM of the switching device of the present invention
It is a functional explanatory view in the direction transmitted from the network to the n-bit cell ATM network.

FIG. 6 is an n-bit cell ATM of the switching device of the present invention.
It is a functional explanatory view in the direction transmitted from the network to the mbit cell ATM network.

FIG. 7 is an mbit cell ATM of the switching device of the present invention.
It is a functional explanatory view in the direction transmitted from the network to the n-bit cell ATM network.

[Explanation of symbols]

101 Cellizing device 102 cell circuit 103 Cell release circuit 104 header information circuit 106 ATM network 110,111 Non-ATM network 301 switching device 303 mbit cell ATM network 310, 311 nbit fixed length cell ATM network 401 buffer 402 mapping circuit 403 buffer 404 Cell header information control circuit 405 control circuit 501 buffer 502 mapping circuit 503 buffer 504 Cell header information receiving circuit 505 Control circuit 601 code generation circuit 701 Judgment circuit

Claims (4)

(57) [Claims] 1. A switching device connected to an ATM network using nbit (n is an integer) fixed length cells and an ATM network using mbit (m is an integer larger than n) fixed length cells. A mapping information storage unit that stores mapping information that associates each bit of an n-bit cell with each bit of the m-bit cell, and a cell received from an ATM network that uses the n-bit cell is an ATM that uses the m-bit cell. When transmitting to the network, the header part of the nbit cell is set to the mbi
map to the header part of the cell of t, or
The determined header information is used as the header of the mbit cell
Min mapped, based on the mapping information, a n-m mapping means for mapping the predetermined bit position of the parts of the information or portions of all the information the mbit cell information portion of the cell of the nbit, When the cell received from the ATM network using the mbit cell is transmitted to the ATM network using the nbit cell, the header part of the mbit cell is changed to the nbi
map to the header part of the cell of t, or
The determined header information is used as the header part of the n-bit cell.
And mn mapping means for mapping a part or all of the information part of the information part of the cell of the mbit to a predetermined bit position of the information part of the nbit cell based on the mapping information. A switching device characterized by being provided. 2. The switching device according to claim 1, wherein the mapping information storage unit has a plurality of types of mapping patterns and an identification code for identifying each of the plurality of types of mapping patterns, and the n− m mapping means is provided for the plurality of mapping patterns.
Describes <br/> Ru identification code to correspond to the mapping pattern selected from among the turn information portion of the mbit cells
And the mn mapping means sends information on the mbit cell .
Switching apparatus characterized by the mapping using the mapping pattern <br/> over emissions corresponding to the partial or Ra読 identification information headings. 3. A switching method applied to a switching device connected to an ATM network using nbit (n is an integer) fixed length cells and an ATM network using mbit (m is an integer larger than n) fixed length cells. The switching device stores in advance mapping information that associates each bit of the n-bit cell with each bit of the m-bit cell, and stores a cell received from an ATM network using the n-bit cell. , When transmitting to the ATM network using the mbit cell, the header part of the nbit cell is changed to the mbi
map to the header part of the cell of t, or
The determined header information is used as the header of the mbit cell
Min mapped, based on the mapping information, a n-m mapping step of mapping a predetermined bit position of the parts of the information or portions of all the information the mbit cell information portion of the cell of the nbit, When the cell received from the ATM network using the mbit cell is transmitted to the ATM network using the nbit cell, the header part of the mbit cell is changed to the nbi
map to the header part of the cell of t, or
The determined header information is used as the header part of the n-bit cell.
Mapping step, and based on the mapping information, an mn mapping step of mapping part or all of the information part of the information part of the mbit cell to a predetermined bit position of the information part of the nbit cell. A switching method characterized by being provided. 4. A switching method of claim 3, wherein the mapping information includes an identification code for identifying each of a plurality of types of mapping pattern and the plural kinds of mapping patterns, wherein n-m mapping step , The plurality of mappins
Pair mapping pattern selected from among Gupatan
Send describes an identification code to respond to the information part of the mbit cells, said m-n mapping step, the mbit cells
Switching method characterized in that the mapping using the mapping <br/> pattern corresponding to the information part or Ra読 identification information headings.