JP3429296B2 - How to control the printer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention
Has a processor that performs processing to synchronize data
Device and control method. [0002] 2. Prior Art and Problems to be Solved by the Invention
The application was filed on July 8, 1991 and is pending US
Patent Application No. 07 / 726,929, entitled "Thing
Chip page printer controller ”(Si
naggle Chip Page Printer Co
related to the United States of America.
The U.S. patent application by reference to the license application number
The description in the description of the above constitutes a part of this specification
And The present invention has a novel processor and
Computer system to minimize the processing load.
Provided is an apparatus having a controllable processor and a control method.
What you want to do. [0004] According to the present invention, there is provided a processor according to the present invention.
The at least first processor issuing the instruction.
And a second processor in communication with the memory.
For data and fetch, serialization and control
An apparatus having a function of performing synchronization of
Write-only for receiving commands from one processor
Command register, command register contents
Control and monitoring of the second processor.
Read / write status that holds the information to be read
・ Mode register for setting register and operation mode
Command / status / mode register consisting of a register
Data, frame buffer address and formater
Register file means for storing bit constants;
To generate memory address and control signals,
Frame buffer address and format
Means for performing arithmetic operations on numbers, and
Temporarily store the memory address before accessing
And address latch means for parallelizing from the memory.
Receives scan data and scans the scan data.
Serialization means for realizing and sending to the control object,
Control of the command / status / mode register means
Access the register file means
Means for performing arithmetic operations and said serializing means.
And control means for controlling.
You. According to the control method of the present invention, at least the
One processor and a second processor in communication with the memory
Scan data fetch, serialization and
Control method for performing synchronization with the control target in the
Receives a command from the first processor, and receives a command from the second processor.
Holds information about the control and monitoring of the
Setting the operation mode of the linter;
Space for storing buffer addresses and format constants
Step and generate memory address and control signals.
The frame buffer address and the format
Performing arithmetic operations on mat constants;
Before accessing the memory, the memory address
Temporarily latching; and
Receiving scan data; and
Serializing the data to the controlled object and sending the data.
It is characterized by having. Further, the control method of the present invention includes:
At least a first processor for issuing instructions, and a memory
Having a second processor in communication with the scan data
・ Fetch, serialize and synchronize with printer
A method of controlling a printer to execute
File address and format constant
And the printer processes the data.
That the second processor is ready to
Notifying steps and whether data should be printed
By the control software of the first processor.
And the control software.
A print command is transmitted to the second processor by air.
Loading the associated command register; and
To the second processor via the printer.
Asserting the frame synchronization signal, and
Taking the time for the margin of the
Waiting for the line synchronization signal to be sent from the
And the step to take the time of the left margin of the page
And the image frame to be sent to the printer
Fetching by the second processor;
The image frame is scanned in synchronization with the clock of the
Step to serialize to the printer line and send to the printer
At the end of each scan line
Until the next line synchronization signal
Waiting for the left margin timer to start.
It is characterized by having. [0005] BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described.
Will be explained. Preferred embodiments according to the present invention are described in detail below.
However, those skilled in the art will appreciate that the present invention teaches newly
And many modifications without substantial deviation from the benefits.
You will easily recognize that changes can be made
U. Therefore, all such amendments and modifications are also claimed.
As described in the claims.
Things. As shown in FIG.
The stem is typically a microprocessor for instructions (i
nstruction micropresso
r) 102, a printer video processor (PVP)
104, page memory 106 ("frame buffer"
Serial communication interface)
108 and a printer engine 110
You. In general, the instruction microprocessor 102
Run a command set and thereby print on a paper page
Generate the data to be done. The generated data is ぺ
Memory 106 where the printer video
-Retrieved by processor 104. Two-way arrow 1
As indicated by 16, the instruction microprocessor 102
Also, printer video processor 104 and status
They also exchange signals. [0006] The printer video processor 104 and the
The linter engine 110 is a printer video processor.
Switch 104 sent to the printer engine 110 from the
Control the frequency and timing of the can data
Communication via a handshake control signal and a clock.
I believe. Serial such as Universal Asynchronous Transceiver (UART)
The communication interface 108 is a microprocessor for instructions.
Status information directly from the printer engine
110 to communicate with. [0007] US patent application Ser.
No. 726,929, entitled "Single Chip Pen"
Printer Controller "(Single Ch
ipPage Printer Control
r), a very large scale integrated circuit (VLSIC) semiconductor
A page-printer controller in the form of a chip
It is proposed for controlling the linter engine 110. FIG. 2 shows a specific example of the page printer system.
Is a diagram showing a typical realization method, in which a page
Printer controller from computer system
Remote, but very close to the printer engine
It has been placed. Also, page printer controller
Minimizes the processing load on the computer system
Peripheral components for performing image operations so that
Built-in. As shown in FIG. 2, the page printer
Controller 202 is a host computer system 2
To the printer engine 110 at a location far from
It is located very close. Typically,
The page printer controller 202 has a system
Access scan data stored in memory 204
The data for actual printing.
It is designed to be sent to the engine 110. VLSIC Page Printer Control
The controller 202 includes an instruction microprocessor 102 and a preprocessor.
Video processor 104, serial communication interface
Interface 108, input / output interface 206, and
A moly system 208 is provided. Instruction Microphone
The processor 102 not only performs diagnostics, but also
Data transformation, clipping, scaling,
Rasterization can be realized. I / O interface
206 is indicated by various arrows from 210 to 216
As such, essentially the page printer controller 20
Interface for all of the internal components
Connected to the I / O bus network 217
Interfaces to all connected external peripherals
Also has a role. Further, the memory system 208
Is the page memory 106 in the system memory 204
Includes fast cache loaded with data from
I have. In operation, printer video
The processor 104 supports the input / output interface 206.
Requesting the external page memory 106
Access data in Each time a request is made,
The video processor 104 includes an external page memory 106
Address position and data size in the
To the source 206. When requested, printer video
The processor 104 addresses and data for the next request
Update data size. On the other hand, I / O interface
Resources 206 for use by the memory system 208
Address and data size until ready
Is stored. The memory system 208 provides this information
From the external page memory 106 to
Access to printer data
The data is returned to the server 104. Printer video processing
The processor 104 then stores the data and
Data to the data engine 110 in series. So
Serial communication is clock of printer engine 110
Synchronize with Flow without interruption of scan data
(Uninterrupted stream)
Printer engine for sending to printer engine 110
The processor 104 controls the page memory 106
Sufficient scan time to handle the latency associated with processing
I have to put my data in a queue
No. The page printer controller 202
The use has many important advantages. Page printer
Controller 202 scans from page memory 106.
Direct memory access to direct data (direct
  memory access (DMA)
Can be. Since the data has been accessed,
If it is desired, a command located outside the system memory 204
Manipulated by the command microprocessor 102
it can. By doing so, the computer system
The processing load on the system 203 is reduced. In addition, for instructions
The microprocessor 102 is a computer system
As with the processor related to 203, the simplified instruction set
Computer (reduced instruction)
  setcomputer (RISC) type architecture
It may indicate that it is one of the chas. R
The number of instructions is limited in the ISC type architecture. That's it
Such a configuration further improves performance. The present invention has a novel video processor
Device, especially a processor for controlling the printer.
It is sa. The video processor is locally associated with the printer
And communicate with the instruction processor and the memory. Bidet
Processor generates the timing signals and scans
Data fetch, serialization, and printer synchronization
Perform the conversion. The video processor has a register file.
, Adder / subtractor (adder / subtracto)
r), having each means of serialization and control
I have. Register file means frame buffer
Stores address and format constants. The adder means includes a memory address and
Frame buffer to generate printer control signals
Arithmetic operation (ari
execute the same operation. The serializing means converts parallel data from the memory.
Receives, serializes the data and sends it to the printer
You. Finally, the control means is controlled by the instruction processor.
Control signal. The control means is a register file
Access the column. In addition, adder means and serialization means
It is this control means that controls the steps. In particular, the video processor provides
Proposed as a printer controller to be located locally
Has been provided. The microprocessor in the printer controller
The processor executes instructions and performs image processing, while video and
The processor provides scan status and interrupt signals
Fetch and serialize scan data in addition to generating
Required to achieve printer engine synchronization
The mechanism is provided. Video processor
By issuing a request to the interface.
Data in external page memory, also known as
Each request to be accessed has an equivalent data size.
It consists of a dress. Scan data request issued
The video processor will address it for the next request.
Address and data size. Receive request data
The video processor scans the data directly.
Send to printer engine in column. scan data
To the printer engine without interruption
The printer video processor has a page memo
Waiting time required to process data request
Queue enough scan data to
Must. I. architecture The printer video processor 300 according to the present invention
The architecture is described by way of example in FIG. Pre
Video processor 300 scans from memory.
Fetch scan data, scan data to printer
Data serialization, printer synchronization, scan status signal
Required to generate a signal and generate an interrupt
It has a structure. Generally, a printer video processor
300 can be divided into two subsystems. No.
One subsystem is an I / O interface 206 and a
A second subsystem communicating with the linter engine 110;
Is the memory system 208 and the printer engine 1
Communicate with 10. In FIG. 3, the first subsystem is a PV
P-IOU interface 302, pixel counter
304, register file 306, read-only memo
(ROM) 308, adder 310, address latch
312, instruction / status / mode register 314
And a controller 316. PVP-
The IOU interface 302 has an I / O address and an I / O
Tries for controlling the data bus flow
It has a tate buffer. Pixel counter 3
04 is the left margin and pin
To count the dot clock for xell scan
Used for Register file 306 writes 1
Is the port register file for read only / 2
But there is a frame buffer address and format
Information about the timing, notes and notes
Used to generate a re-address. register·
The registers contained in the file 306 are shown in Table A below.
Shown in <Table A>register Purpose Base frame buffer start address (byte address) Pbase old base register (band buffer mode) X max Width of frame buffer scan                     (Rounded up to the nearest multiple of 8 in bytes) Y step memory address increment (number of bytes) Y max number of scans in frame T margin Number of scans at the top of the frame Bsize Band buffer size (number of rows) V mit vertical interrupt scan number Base current Current base register (internal use) Current Current scan memory address (internal use) X current X address in current scan (internal use) Y current Current scan number (internal use) Data size memory access size (internal use) Bcnt Current position in current band buffer (internal use) Tmp 0 Temporary register (internal use) Tmp l Temporary register (internal use) Tmp 2 Temporary register (internal use) In addition, two separate registers are used for timing calculations
To save space in the register file.
Therefore, they are not included in the register file 306. So
The two registers are shown in Table B below, but in the preferred embodiment.
Are stored in the pixel counter 304. <Table B>register Purpose L margin The number of video clocks to the left of the first dot                     Minus (-) 2 X maxl Number of bytes in scan line minus (-) 1 Read-only, closely related to register file 306
Memory (ROM) 308 from the format constant set
Become. In the preferred embodiment, ROM 308 contains 0, 1,
It consists of 4, 8, and 16 constants. The adder 310 stores the register file data
Perform arithmetic operations on data and / or ROM constants. That
Write the calculation result back to the register file 306
Address, control and status signals
Used by controller 316 to generate
You. Specifically, the adder 310 performs the “carry out”
Creates a flag and a "zero" flag, the two flags
Used by controller 316 to compare sizes.
Will be The "carry out" flag is the first opera
Size of the command is greater than or less than the second operand
Indicates whether it is either. On the other hand,
The lag is the size of the first operand, the second operand
Indicates whether it is the same as For example, zero
The flag indicates if the current address matches the old address
It is sent to the controller 316 by the adder 310. Address latch 312 stores the current address.
To pay. The current address in address latch 312 is
When a memory read / write request is made, the PVP-IOU
Interface 302. Address latch 31
2 indicates that the controller 316 controls the I / O address bus.
It is necessary to reduce the number of control cycles.
For memory read / write requests for performance reasons
In addition, the controller 316 may use the register file 306
Instead of reading the current address from the
Switch 312 on the I / O address bus
Enable tri-state buffer for sending
To Command / Status / Mode Register
Are collectively denoted by reference numeral 314, but the soft
Scan conversion control by software, software
Scan conversion monitoring and software PVP
Instruction microcontroller to allow interrupt control
Can be read or written by the processor 102
In some cases. The instruction microprocessor 102 is
In addition to performing cutting, coordinate transformation, clipping, scaling
Rasterization of ring and scan data can be realized. In operation, the controller 316
Printer printer under the control of command register 314
The sequence of the video processor 300 is advanced. life
The command microprocessor 102 has a command register
314 by setting the start frame bit
Load the scan command and receive the information
The controller 316 starts scanning. control
316 initializes the scan and follows the sequence
Scan the pages. The controller 316
Performs a series of calculations until the serialization is completed, and the serializer
Address and printer engine to load
The timing for the gin 110 is generated. Page complete
Sometimes, the scan pending bit in command register 314
If reset, scan from new address
Is resumed. The mode register 314 is
Page register as described for
Readings that are programmed prior to operation
Read / write register. Mode register 3
14 is not a double buffer system. In addition, PVP
While mode 300 is running, mode register 314 is
Dynamic programming is a preferred embodiment
Not allowed. Contents of mode register 314
Is as described in Table C below. <Table C>Mode bits Reset level function <0> TMDE 0 timing mode <1> JBMS 0 JBMS mode <2> BBE 0 band buffer enable <3> CINT 0 print completion interrupt enable <4> VINT 0 vertical interrupt enable <5> PRDY 0 PRDY interrupt enable <6> VSREQ 0 VSREQ interrupt enable <7> BBI band buffer interrupt                                       Enable <8> DIV 0 Video clock division selection <9> BLV 0 black level <31:10> Reserved 0 Program to "0" The "timing mode" bit and the "JBMS" bit
Together, the PVP 300 is in mode I, II, or I
Select which of II to operate. These three
The mode is different for different conventional printers with different interactive characteristics.
I correspond to each other. In other words, the printer according to the invention
The video processor 300 is the first software
With one of the three conventional printers
This is a changeable system that enables speech processing. More specifically, it is described in this specification.
Conventional pudding operating in Mode I
Vertical synchronization of status register 314
(VSync) bit is set by software
This initiates a page operation.
In addition, the printer clock is free running at high speed.
Is. The VSync signal is sent to the printer engine 1
10 in response to the FSYNC signal from
Please note that it is generated. In this specification
A conventional platform that operates in the described mode II
In the linter, the printer's FSYNC signal is
Trigger video processor 300 to operate page
Is started. In addition, the printer clock is
Lee running. Finally, as described herein
Conventional printer operating in mode III
Then, the printer's FSYNC signal is
Trigger processor 300 to perform page operations
Begins, but in this case the printer clock is free
It's not a sleeping. In a preferred embodiment, JBMS and TM
The decoding scheme for the DE bit is
It is shown in Table D. Many other decodes besides those listed here
Tables can be considered, and the printer mode is set to other than three types.
It should be understood that
You. <Table D>IBM bit TMDE bit mode     0 1 I     0 0 II     1 1 or 0 III As defined by the JBMS and TMDE bits
The printer video processor 300 is in mode I
D if programmed to operate
If the IV bit is "0", divide the video input clock by 8
Then, if it is “1”, the PVP clock will
Through generators (408, 410 in FIG. 4)
Report. The printer video processor 300 is
To operate in mode II or mode III
If programmed, the PVP clock generator
Does not divide the video input clock. Further, in a preferred embodiment, the "van"
Buffered mode ''.
To change the memory management. The BBE bit
If logic high ("1"), the band buffer
・ Mode is selected, but all other pages are normal
Mode is selected. In this specification, the band
The fa mode is one mode of operation.
In that mode, the printer video processor 300
Is the page memory for printing text pages
Alternately use different frame buffers. Van
Buffer is the size of each B-size scan line.
Mori Block. Belongs to the first band buffer
The first address refers to the "base" address
You. First address belonging to other band buffers
Is hereinafter referred to as the "P base" address. Further, in the mode register 314,
Of CINT, VINT, PRDY and VSREQ
Can be interrupted by each interrupt source
It represents that. Any of these bits are logic high
If set, then the associated interrupt
The source enables the generation of a particular PVP interrupt.
In the preferred embodiment, more than one interrupt is active at a time.
May be active. PRDY bit of mode register 314
Is set to a logic high,
Ready for blink from printer engine 110 (P
RDY) signal is inactive
If the state transitions to active, an interrupt
Is notified. In addition, the video of mode register 314 is
The scan request (VSREQ) bit is
Is set to the printer
VSREQ signal from gin 110 is inactive
If it changes to active, an interrupt is notified. The BLV bit is a logic high or low
Depending on the glitch, "white level" or "black
Level). The above level is a book
Allowed by printer video processor 300 of the invention
The scan data inversion caused by another feature.
Connect. Usually, the log sent to the printer engine 110 is
Gic low ("0") corresponds to the white of the page
And a logic high ("1") turns the page black
Equivalent to. In the preferred embodiment, the black level
Is the default level. If inversion is selected
For example, a logic low is equivalent to black and a high is
Equivalent to The exception is the margin, which is always white
It does not change. As described in detail below with respect to FIG.
In the meantime, the scan data has a margin “blanking (b
(Sending to logic 347)
Black level signal 634 and blank signal
636). The spare bits shown in Table C are
Program to zero to prevent effects from being triggered
It needs to be rammed. Spare bits are production test organization
Or for future performance enhancements. The command register 314 stores an instruction
From the control software in the microprocessor 102
This is a write-only register that receives commands. That
The contents can be read through status register 314.
Can be. The contents of the command register 314 are
It is shown in Table E. <Table E>Command bits Reset level function     <0> STF 0 frame start <1> RSET 0 reset PVP (for diagnosis) <2> BKRL 0 Back side printing, right to left <3> ERASE 0 Erase after printing <31: 4> Reserved 0 Program to "0" Command register 314 stores the PVP operation.
Used to start and support some test functions
Is done. Except by command register 314
No operation is started. Command register 3
14 for performance reasons and changeable specifications.
It is a bull buffer system. Command register
314 first loading to PVP 300
Frame generation is permitted. Command register 3
14 is loaded a second time, the second frame is reloaded.
Unless it is a set (RSET) or test function,
Started after completion of the first frame. Next, the first frame
If the command register 314
When loaded for the third time, the results may be unpredictable.
There is a case. However, the RSET bit is set
Exception in which case all operations are aborted
Can be The STF bit in Table E is
Command operation and normal system operation
The PVP 300 executes at the time of
Start the operation. Printer controller
When the set signal is requested, the command register 314
Is cleared and all operations are aborted. Ko
Sets the RSET bit of command register 314
Also interrupting all operations
Can be. Basically, the RSET bit is the command register
It has priority over other bits in the star 314. For the BKRL bit, “back side printing” is performed.
Whether it is going to do so. Back side printing is set
If so, the pages are scanned in reverse order. That is,
From bottom to top, right to left. The ERASE bit indicates that the frame buffer
Indicates whether it will be erased after printing. More specifically,
Mori Ward needs printer video processing for printing
Memory 300 after being read by the
The code is erased. This feature further enhances performance
Can be made. The spare bits shown in Table E are
Program to zero to prevent effects from being triggered
I have to ram it. This spare bit is produced
Used to implement test mechanisms or future performance enhancements
Sometimes. The status register 314 stores PVP3
The information on the control and monitoring of 00 is stored. Stay
The status register 314 is a read / write register.
The contents are as shown in Table F below. <Table F>Status bits Read / write function                     <0> FIP readout frame in progress <1> FPD readout frame pending <2> CINTA read page completed <3> VINTA read / clear Vertical direction time complete <4> BBIA read / clear (band) buffer complete <5> PRDYAP read / clear PRDY positive edge transition received <6> PRDYAN read / clear PRDY negative edge transition received <7> VSREQA read / clear VSREQ transition received <8> LSYNC read LSYNC pin level <9> FSYNC read FSYNC pin level <10> PRDY read PRDY pin level <11> PPRDY read PPRDY pin level <12> Prnt read / write Print pin level <13> CPrdy read / write CPrdy pin level <14> MREQ read Memory request pending <15> BLANK readout Horizontal blanking status                 (Horizontal banking ststus) <16> FIFOE read FIFO empty <17> FIFOEB read FIFO block empty <18> FIFOF read FIFO full <19> FIFOR read / clear FIFO refill                                               (Refill) error <20> ERASE read-out frame after print permission                                               Clear buffer <21> BKRL read Back side printing, right to left <22> VSync read / write VSync pin level The FIP bit indicates that the frame has already started,
Indicates that it has not been completed. FPD bit is second
Frame is already loaded, but reset
That it has not been started, except for a command
Is shown. The reset command applies to all operations
Interrupt and clear these bits. [0039] state transition
on) bit (CINTA, VINTA, BBIA, P
RDYA, VSREQA> are related events
Occurs and indicates that it has not been cleared. So
The corresponding interrupt enable is set.
Causes an interrupt when active. Stay
Set the status bit in the status register to logic high
Setting clears these bits
Then, the interrupt is cleared. Log in state bit
Write the lock row in the preferred embodiment.
These bits do not change anything. Set once with hardware
When activated, the associated state bit is
RSET bit of 0 becomes active or PVP
When the reset command is executed,
Not reset. The pin level bit indicates the level of the input / output pin.
Hold. LSYNC, FSYNC, PRDY and
Each bit of PPRDY is an input (hence the read
VSYNC, PRNT and CPR
The DY bit is the output. VSYNC, PRNT and
The CPRDY bit is reset by a reset operation.
Is cleared to a logic low and the processor
Which level by writing to status register 314
Can also be dynamically programmed. TMDE, BBE and interrupt enable
Bit is finally stored in the mode register 314.
Holds the programmed value. Some of the bits are dedicated to testing.
You. For example, consider the following bits: M
The REQ state bit indicates that the PVP 300
Indicates that one or more memory requests remain. BLANK
The bit is horizontal blanking (horizontal b)
ranking is currently taking place. FI
The FO state bit is the scan data shown in FIG.
Holds various FIFO control states of queue 344
You. Reset the interrupt in the PVP 300
For this reason, the reset instruction is executed by the PVP command register 31.
4 or a separate interrupt bit is
Whether the status register 314 is reset. V When the int register is loaded,
Decremented each time the line is reset
(X current is X When loaded from max
H). V When int becomes zero (0) or less, VINT
The A status bit is set. VINT interrupt enable
Interrupt is for instructions if the bull bit is set
It is sent to the microprocessor 102. V int is
The data in the pointed scan line is
Generated after being sent to the print engine 110. The C1NT (print completion interrupt) bit is
The last scan of the data is sent to the printer engine 110.
Set after being set. Status bits and interrupt enable
If the printer is set with both
Be informed. If the PRDY interrupt is enabled
If the PRDY bit is active from inactive
(PRDYAP transition bit is status
Is set in the register 314) and the PRDY interrupt
Is set. PRDY interrupt enabled
The PRDY bit from active to inactive
(PRDYAN transition bit is status
• also set in register 314)
The RDY interrupt is set. PVP 300 in band buffer mode
The BBI interrupt is enabled and the current
File has been printed (BBI status bit is set)
And the base register has already been replaced (swa
If p), the BBI interrupt is set. Ba
If no buffer mode is selected, the BBI
The state bit is always cleared. FIG. 4 shows a preferred embodiment of the controller 316.
This is a simple example. The controller 316 controls the decoder 40
2. State machine 404, logic / buffer 40
6, clock divider 408, clock buffer
410, interrupt logic 412, and decoder / ma
It consists of a multiplexer 414. Features described in this specification
Many other circuit configurations can be implemented by those skilled in the art to achieve
It must be emphasized that the outcomes can be considered. The decoder 402 has a printer video program.
Reading for latches and / or registers in the processor 300
I / O to generate read / write enable
Address, read / write signal, chip select
Decode the address strobe. Decoder 4
02 is also sent to the PVP-IOU interface 302.
Generate a shake control signal. In the preferred embodiment
The handshake control signals are “Ready” and “Read”.
Out / write "signals. The logic / buffer 406 stores the current address.
Is input / output address buffer by the address latch 312.
To the PVP4-IOU interface
Read / write of memory transferred to interface 302
Create the size of the request. In addition, logic / buffer
406 is controlled by the state machine 404.
The adder output to calculate the end of the scan line.
Mask the last 4 bits. And logic / buffer
406 indicates that two scan lines overlap
If so, the menu is controlled by the state machine 404.
At the time of a memory write request, two bits of the current address are
Clock generator is the printer clock
Generates a dot clock. The operation
Is necessary to clarify this function provided by the present invention.
is there. The clock buffer 410 is connected to a printer
In synchronization with the printer clock from the engine 110,
Video clock to printer video processor 300
Supply Clock divider 408 is a clock divider.
Printer clock from the buffer 414
And divide the frequency into either 8 or 16
Split or split completely according to the features of the present invention
Do either or not. The split option is
Select register 314. The interrupt logic 412 is a printer
A function used to monitor the status of the video processor 300
To generate the interrupt signal, the status register
Event bits and mode register interrupt enable
Perform combinational logic with bits. The preferred embodiment includes:
There are five interrupts: (1) Drop when a certain scan line is reached
Direct interrupt. (2) Band buffer indicating end of band buffer
interrupt. (3) Interrupt to indicate completion of page. (4) A new page is assigned to the printer video processor 300.
Printer engine 110 to start
Frame synchronization interrupt. (5) Ready signal from printer engine 110
Interrupt to signal the receipt of The decoder / multiplexer 414 receives input / output
From the PVP-IOU interface 206
Decode to register file write address and
Navel. The decoder / multiplexer 414
I / O address or printer video processor address
Address and write to register file
Enable the signal. The state machine 404 has a register
Of calculation of constants in file 306 and ROM 308
Control the order. The order of calculation is determined by the printer engine 11
0 and the timing signal from register 314
Sequencing and events
Commands for triggering
/ Status / mode register bits.
A sequence of events that occur within the printer video processor
And executed by the state machine 404
The algorithm will be described later with reference to FIGS.
explain. Referring back to FIG. 3, the printer
The second subsystem of the video processor includes a memory system.
System 208 and the printer engine 110.
As shown in FIG. 3, the second subsystem is a PVP-MC
U interface 342, scan data queue
(FIFO) 344, parallel-serial shift register
Realizer) 345 and controller 346
You. The PVP-MCU interface 342 has
Includes latch for storing data from MCU bus
Have been. The scan data queue 344 is essentially
It is a FIFO buffer, PVP as long as there is space.
-Data from the MCU interface 342 is loaded
It is. Along with the PVP-MCU interface 342,
Storing scan data in the scan data queue
, Page in progress, to printer engine 110
Interrupt-free flow of video bits.
Specifically, scan. Data queue 344 is full
(Full) signal and empty signal
It is sent to the roller 314. In response, the controller 3
46 prevents data loss or before scanning
In order to prevent the queue 344 from being emptied,
Control the flow. The depth of the queue 344 is
And depends on the
Expected worst case latency and target maximum bidet
Set by the clock rate, but
In the embodiment, the number is at least 8 words. The serializer 345 has scan data
Scan data bytes from the data queue 344 are
Has been loaded. The scan data byte is
Logic 347 before being sent to the
It can be operated by the controller 346 via. Lodge
Step 347 will be described later in this specification. Good
In a preferred embodiment, the serializer 345 has 8 bits.
One bit per dot clock (DCLK)
Output in series at the rate of PVP300 to Printer
Printer video data output to the engine 110
Data 370 is referred to herein as WDATA. FIG. 5 shows the control shown in FIG.
FIG. 146 is a low-level block diagram of block 346. In FIG.
The controller 346 has the bus data of the MCU.
To assert the appropriate latch enable when valid
The counter 502, the latch / logic 504, and the
It has a trick 502. According to another feature of the invention,
The hardware is provided with a license from the memory system 208.
With front-end mode and random data return
The mechanism required to achieve compatibility with both backside modes
Have. As described above, the scan in progress of the page
By storing the data in the scan data queue,
Video bit interrupt to printer engine 110
A perfect flow is possible. As shown in FIG.
Logic 508 in roller 346 writes the video queue.
Generate a write signal. Further, logic 508 includes
PV to be written to can data queue 344
Select P-MCU interface data. The low of the parallel-serial shift register 346
In reading, the counter 514 and the decoder 51
6 bytes to scan data queue 344
Generate a select. The counter 514 has a front mode and
Mechanisms required to achieve compatibility with both backside modes
Up / down counter to provide
You. In front mode, byte select is byte add
Must occur during the increase in
Byte select during byte address decrement
Must occur. Latch / logic 520, counter 522
And the decoder 524 provides a switch to the printer engine 110.
Generate a bit select for the can data.
Like the counter 514, the counter 512 has both front and rear sides.
Up / Down card compatibility for compatibility with
Unta. In front mode, the least significant bit
(LSB) is serialized first. Conversely,
In serialization, the most significant bit (MSB) is serialized first.
It is. All bytes in one word in scan data queue
When the data is loaded into serializer 345, a new word
Scan data wait to enable serialization of
That word must be removed from the matrix 344.
No. The controller 346 further includes a synchronizing
The logic 526 is provided. Operate in front mode
Synchronizer / logic 526 when running
Will load the most significant byte into serializer 345
Detected in the scan data queue 344.
Generate a protruding signal. Synchronizer in reverse mode /
Logic 526 determines that the least significant byte is the serializer 34
5 and wait for scan data
A read signal is generated in the matrix 344. Another important feature of the present invention is that the printer
The data sent to the engine 110 is a word address
Rather than being serialized starting from a byte
is there. Current address is first at scan line start address
Each time the address is set, the least significant three bits of the current address are
Is pre-loaded into the counter 514 of FIG. Therefore, FIG.
Of the scan data queue 344
Any scan data byte of each scan line
Can be selected as the start byte of the input. FIG. 6 shows the FIFO shown by the broken line in FIG.
FIG. 6 is a low-level block diagram of block 380. FIF
The O block 380 is a PVP-MCU interface 3
42, video data queue 344, serializer 3
45 and logic 347. As shown in FIG. 6, the PVP-MCU interface
The preferred embodiment of the face 342 is for waiting for video data.
64 * 4 bits FIFO stored in matrix 344
(FIFO) to direct data into buffer 610
Four 32-bit registers (602-608)
Contains. The interface 342 also determines which set of
Register (a pair of 602 and 604 or a pair of 606 and 608
Tuple) should be loaded into FIFO buffer 610
64-bit multiplexer (MUX) to select
Is provided. 2-bit up counter 614
Together with the decode logic (DEC) 616
An enable signal is output to the nodes 602 to 608. further,
The decode logic (DEC) 620 is a flip-flop.
Combined with rops 622-626,
Last register was preloaded first
Then, a FIFO push signal is generated. 8 at the output of FIFO buffer 610
The input multiplexer 628 is connected to the FlFO buffer 61.
Which of the 8 bytes from 0 is the shift register (serializer
Isa) Select to be loaded into 345. 3 bit
The up / down counter 630 provides a decode (D
EC) 632 and select to multiplexer 628
Generate a reset signal. In addition, bidirectional 8-bit shift
• Register 345 serializes printer video data
To The dot clock (DCLK) 656 is
Used as the clock for the printer engine 110
Is the PVP system clock (SCLK)
Note that it may be asynchronous
You. However, as shown in FIG.
The pop instruction to 0 is synchronous with DCLK656,
PVP system via logic 640 and decode 642
Resynchronized with the system clock (SCLK). The FIFO buffer 610 has a width of 64 bits.
G, 4 bits deep. However, the FIFO according to the present invention
The buffer 610 is compatible with both front and back modes.
In addition to the 32-bit and 64-bit MCU switch mode,
Must also be compatible. The system is 32
When operating in cut mode, the FIFO
The data provided externally as input to the file 610 is
While sent in 32-bit blocks, 64 bits
In the case of operation in a unit, the data is 64 bits.
Come in blocks. In addition, the FIFO data is loaded
The order is different between the front mode and the back mode. The reason
, Front mode requires left-to-right page scan
In this case, the address increases. Reverse
In reverse mode, page scanning is performed from right to left.
Address, in which case the address decreases. Follow
To support front mode and back mode.
Supports both bit mode and 64-bit mode
So that when a memory request is performed
The circuit shown in FIG. 6 always has a series of FIFO
Have to go through a licensing procedure. In the 32-bit mode, as shown in Table G below
As shown, the 2-bit up counter 614 goes low first.
Is executed. <Table G>Counter state Memory request   00 For 4-word (short) request   10 In case of 2 word request   11 When requesting one word In 64-bit mode, as shown in Table H below,
The load up counter 614 is loaded first. <Table H>Counter state Memory request   00 In case of 4-word request   01 1 or 2 word request Four possible operation scenarios individually
By analyzing the data in the FIFO block 380.
The loading procedure is described below. Specifically,
There are four cases: (1) 32-bit mode / front mode (run from left to right
Investigation) (2) 32-bit mode / back side mode (run from right to left
Investigation) (3) 64-bit mode / front mode (running from left to right
Investigation) (4) 64-bit mode / back side mode (run from right to left
Investigation) In the discussion below, DO, D1, D2, and D3 are F
The data word returned to IFO block 380,
Is the lowest order address, and D3 is the highest priority address.
Assume dress. Operation scenario (1), that is,
32-bit mode and front mode (scan from left to right)
In the case of, registers 602 to 608 store a specific start buffer.
Unit STB [1: 0] and the state of the counter 614.
And loaded as shown in Tables I through K below. <Table I> Case 1: 4-word requestSTB [1: 0] CTR = 00 CTR = 01 CTR = 10 CTR = 11   00 R2 = D1 R3 = D1 R0 = D2 R1 = D3   01 R3 = D1 R0 = D2 R1 = D3 R2 = D0   10 R0 = D2 R1 = D3 R2 = D0 R3 = D1   11 R1 = D3 R2 = D0 R3 = D1 R0 = D2 Two FIFO push signals are generated: PUSH1: {R3, R2} PUSH2: {R1, R0} <Table J> Case 2: Two-word requestSTB [1: 0] CTR = 10 CTR = 11 00 R0 = D2 R1 = D3 01 R1 = D3 R0 = D2 One F1FO push signal is generated PUSH1: {R1, R0} <Table K> Case 3: One word requestSTB [1: 0] CTR = 11 xx R1 = D3 One FIFO push signal is generated: PUSH1: {R1, xx} Operation scenario (2), ie, 32 bits
Mode and back mode (scanning from right to left)
Data 602 to 608 have a certain start byte STB.
[1: 0] and the state of the counter 614, the following table
Loaded as shown from L to N. <Table L> Case 3: 4-word requestSTB [1: 0 ]CTR = 00 CTR = 01 CTR = 10 CTR = 11   00 R0 = D0 R1 = D1 R2 = D2 R3 = D3   01 R1 = D1 R2 = D2 R3 = D3 R0 = D0   10 R2 = D2 R3 = D3 R0 = D0 R1 = D1   11 R3 = D3 R0 = D0 R1 = D1 R2 = D2 Two FIFO push signals are generated: PUSH1: {R3, R2} PUSH2: {R1, R0} <Table M> Case 2: Two-word requestSTB [1: 0] CTR = 10 CTR = 11 00 R2 = D2 R3 = D3 01 R3 = D3 R2 = D2 One FIFO push signal is generated PUSH1: {R3, R2} <Table N> Case 3: One word requestSTB [1: 0] CTR = 11 00 R3 = D3 One FIFO push signal is generated PUSH1: {R3, xx} Operation scenario (3), ie, 64 bits
Mode and front mode (scanning from left to right)
Stars 602 to 608 have a certain start byte STB.
[1: 0] and the state of the counter 614, the following table
Loaded as shown from O to Q. <Table O> Case 1: 4-word (short) requestSTB [1: 0] CTR = 10 CTR = 11   00 ｛R3=R2｝ = ｛D1, D0｝ ｛R1 = R0｝ = ｛D3, D2｝   01 {R1 = R0} = {D3, D2} R2 = R0} = {D1, D0} Two FIFO push signals are generated PUSH1: {R3, R2} PUSH2: {R1, R0} <Table P> Case 2: Two-word requestSTB [1: 0] CTR = 01 xx {R3, R0} = {D1, D0} One FIFO push signal is generated PUSH1: {R1, R0} <Table Q> Case 3: One word requestSTB [1: 0] CTR = 01 xx {R1, R0} = {D1, xx} One FIFO push signal is generated PUSH1: {R3, R2} Operation scenario (4), ie, 64-bit
Mode and back mode (scan from right to left)
The stars 602 to 608 are as shown in Tables R to T below.
, A particular start byte STB [1: 0] and the counter
The state of the data 614 is loaded. <Table R> Case 1: 4-word requestSTB [1: 0] CTR = 10 CTR = 11   00 {R1 = R0} = {D1, D0} R3 = R2} = {D3, D2}   01 {R3 = R2} = {D3, D2} R1 = R0} = {D1, D0} Two FIFO push signals are generated PUSH1: {R3, R2} PUSH2: {R1, R0} <Table S> Case 2: Two-word requestSTB [1: 0] CTR = 10 xx {R3 = R2} = {D3, D2} Two FIFO push signals are generated PUSH1: {R3, R2} PUSH2: {R1, R0} <Table T> Case 3: One word requestSTB [1: 0] CTR = 10 xx {R3, R2} = {D3, xx} One FIFO push signal is generated PUSH1: {R3, R2} As described above <, shift / restore from FIFO buffer 610
Select one of the 8 bytes to be read into the register 345
The logic to do is a 3-bit up / down counter
630. Up / Down counter 630
Is the number of each scan with bits CURRENT [2: 0].
Only loaded at the beginning of the line. Bit CUR
RENT [2: 0] is the start byte STB of the scan
[1: 0] is determined. Load shift register 345
Each time the up / down counter 630
Select is output to the multiplexer 628, and the clock is output.
Is taken. In the preferred embodiment, the counter 630
The byte sequence corresponding to the state is shown in Table U below.
You. <Table U>CTR             BYTE 0000 001 1 010 2 011 3 100 4 101 5 110 6 111 7 In front mode (scanning from left to right), the counter 630
Is an up counter and shift register 345 is on the right
Shift (LSB first). CTR = 111, FI
Any time a FO pop or trigger is generated,
Is done. Shift register 345 stores the last byte of data.
Must be in this state before shifting all
I don't want to. In the back mode (scanning from right to left), the cow
The counter 630 is a down counter, and the shift register 3
45 shifts left (MSB first). CTR = 00
Whenever it reaches 0, a FIFO pop signal is generated
You. Further, the block sent to the logic 347
The rack level (BLV) signal 634 is
Black and white video data (WDATA) 370
Decide which of the two corresponds. The mode in Fig. 3
If BLV = 0 in the register 314, WDAT
A = 1 corresponds to black, and if BLV = 1, WD
ATA = 0 corresponds to white. In addition, the BLANK signal 636 is
If asserted for 347, then the printer
・ Video data (WDATA) is white (BLV
= 0, 0, BLV = 1, 1), page
Gin is available. As described above, various purines can be prepared according to the present invention.
Data will be available. Mode register 314
The bits in are between the printer video processor 300 and
Three types of printer engines 11 to interface
Initialized to select one of zeros. In this book
In a conventional printer operating in mode I,
Frame synchronization of status register (VSync)
By setting bits by software,
Operation is triggered. In addition,
Clock is very fast and free running
is there. A slave operating in mode II herein
In conventional printers, the printer's FSYNC signal is
Triggers the video processor 300 to
Operation starts. In addition, printer
The hook is free running. Finally, in this specification
Conventional printer operating in mode III
Then, the printer's FSYNC signal is
Trigger processor 300 to page operation
Is started. In this case, the printer clock is free
・ Not running. Operation in the above three modes is possible
To implement clock divider 408 of FIG.
The preferred embodiment that has emerged is shown in FIG. 7 below. FIG. 7 shows the low level of the divider 408 of FIG.
FIG. In FIG. 7, the divider 40
The output of 8 is called "dot clock"
Clock data to the printer engine 110
Go out. The line synchronization (LSYNC) signal is
Regardless of the type of data
Is sent. When the LSYNC signal is received, the edge
Detector 702 is the leading edge of “LSYNC”
Is detected, and the flag 704 is set to logic high. Logi
High, flag 704 indicates divider 408
Generate a dot clock. Synchrona
Iser 706 receives the output dot clock and
Operate in sync with the printer clock
To do. The logic 708 includes a multiplexer (MU)
X) To send an input signal 710 to the
Between the output of the printer 706 and the input printer clock.
An AND function is formed between them. The signal is signal 714
And 716, so that Modes II and III
Is to propagate through multiplexer 712
Has become. The mode I program is controlled by the divider 718.
Appropriate operation with the linter becomes possible. Diva
Ida 718 divides the printer clock by 8 or 16
Divide the signal into any one of them and send the divided signal to logic 708.
Send in. Logic 708 connects to multiplexer 712
To generate an input signal 720 to the printer
An AND function is performed on the signal and the divided signal. De
If the divider 408 is operating in mode I,
Multiplexer 712 controls signal 720 according to control 722.
Output the dot clock. If the printer engine 110 scans
When it reaches the end of IN, a blank signal is output to the latch 724.
Is entered. The blank signal has a logic
Low so that divider 408
Stop the output of the dot clock. II.operation A sequence of events that occur in the printer video processor 300
The sequence is described below. 1. The parameters of the video register file 306 of FIG.
Data is preloaded, in which the base register is
included. The operations are page size, file
The frame buffer address or margin is
Usually, unless dynamically changed during the
This is done during initialization of the printer and related peripherals. 2. The printer engine 110 is for the PVP 300
Asserts that data preparation is complete
ert). 3. The print signal is sent to the instruction microprocessor (instr
action microprocessor) 102
Printer engine 1 by the control software inside
Asserted for 10. 4. The print command is in the instruction microprocessor 102
Command of PVP300 by the control software of
• Loaded into register. 5. FSYNC signal from printer to PVP300
Asserted. As shown in FIG. 4, the FSYNC signal
Is asserted to the state machine 404. 6. State machine 404 is the top margin timing
Start to take Operation in front mode of PVP300
State machine 404 during the
The "top margin" used to time the gin
8 and 9 for the “counting algorithm”.
It is detailed. On the other hand, the PVP 300 operates in the back side mode.
When rating, the state machine 404
Top used to time the top margin
9 and 1 for the margin counting algorithm.
3 will be described in detail. 7. Upper margin timer (register T margin
Complete the count)
And the pixel counter 304 is the printer engine 1
Wait for the LSYNC signal from 10. 8. Input of LSYNC signal received by PVP300
The pixel counter 304 has left margin
Ima (register L programmed by margin
Is started), and the serializer 345
The first frame buffer to be sent to the
Fetch data. 9. Left margin timer L margin completes
Scan data is synchronized with the printer clock
Therefore, the flow starts from the controller 346 of the PVP 300.
I will. When operating in front mode of PVP300
State to serialize scan data to
"Serialization algorithm used by machine 404
FIG. On the other hand, PVP
When the 300 is operating in reverse mode,
State machine to serialize scan data
"Serialization algorithm" used by 404
This is described in detail in FIG. End of scan is L
X determined by the margin counter m
ax register data is used. 10. At the end of each scan line, a pixel
The counter 304 indicates that the last scan of the image frame
Until completion, LSYNC and L margin timer
I'm forced to wait. PVP300 is in front mode.
At the end of each scan line when
That is, at the right margin of the page, the state machine 404
Used by the "post scan line algorithm"
This is described in detail in FIGS. 11 and 12. one
On the other hand, if the PVP 300 is operating in backside mode
Each scan line by the state machine 404.
Post-scan line alignment used at the
The algorithm is described in detail in FIGS.
You. 11. When the last scan of the image frame is completed, P
The VP 300 reads the next print command from the command register 314.
Wait for the command to be sent. Pending print command
If exists, a new frame is started immediately.
You. III.Features and benefits In sum, the present invention has numerous features and advantages.
By way of example, some functional features will be discussed next. The printer video processor 300
Enables efficient and fast direct memory access (DMA)
It has the necessary mechanisms to manifest. The printer video processor 300
Bytes of data at the beginning and end of each scan line
・ Equipped with the necessary mechanisms to achieve alignment
You. In other words, rather than from a word address,
Serialization of data starting from write address
That is. According to the present invention, for printing a page
Printer video processor in page memory
Band that uses different frame buffers
The buffer mode can be realized. More specifically
Is the base and P base in band buffer mode
・ Data corresponding to address is blank operation
Top page (top-of-page)
Also exchanged during operation. Printer video
The processor 300 determines whether the base and P base addresses
B-size scan line band buffer starting with
Use alternately. Two bands for scanning pages
If only the buffer address is needed,
And P base registers prior to page scan
Is initialized only once. However, 2
If you need more than one band buffer address
Printer video processor 300
Signal and state bit to complete band buffer
And thereby the base and P base addresses
Can be changed dynamically
is there. With the printer video processor,
Operate in either front or back mode
And become possible. Another feature of the present invention is that the printer
The video processor 300 outputs to the printer engine.
Scan data can be inverted.
Image to be physically printed on paper is reversed
That is. Frame buffer during page scan
The function of partially clearing the
Another feature of the video processor 300 is that
You. More specifically, Printer Video Pro
The processor 300 typically sends a message after each memory read request.
Send a memory write request. Read request and write
Request size near or at the end of the scan line
Usually the same except for data byte requests in
You. After each memory request, the data is
And then sent to the printer engine 110
In the meantime, the state machine 404 of the PVP 300
The next byte requested via arithmetic unit 310 is also the next scan.
Check if it is on the line. If so
Printer video processor 300
Hit the backup flag and the byte is
Inn. First memory read
When a request is made for the next scan line,
The overlap flag is used to completely clear a word.
A mask for the requested address and data size.
Masking may also be performed. Finally, the printer video processor 3
00 maintains compatibility with various types of printers. Pre
Bit in the mode register of the
Defaults are set, so that operating characteristics
Can choose one of the different conventional printers
it can. Features and advantages other than those described above of the present invention
Examines the drawings and text described in this specification.
Will be apparent to those skilled in the art. here
Any additional features and advantages other than those discussed in
, But are incorporated herein. IV.An example FIGS. 17, 18, and 19 show the front mode and the back mode.
Printer / Pidget / Processor for each surface mode
Is an example of the input / output address specification generated by the above. This
These examples illustrate many of the features and advantages of the present invention.
Reveals. Example layout in these figures
Are almost the same, and are shown in FIGS. 17 and 18 here.
We will discuss only examples, but consider the following
Is equally applicable to FIG. In FIG. 17, legend block 1
Reference numeral 502 denotes various parameters in the register file 306.
Represents the initial value of the data. These parameters are
It is shown and described in Table A. In short, block 15
The parameter 02 performs the following functions. Y ma
x is the scan line on the virtual page shown in FIGS.
In number. Base is the first byte address, P
The base indicates the address of the next band buffer.
ing. B size is the band corresponding to the base address
-The size of the buffer. In this example, B size
Is set to 3, so the band buffer interrupt
Only occurs after the third scan line 1540
You. X max is when the scan line is completed
Used to confirm. Y Step is for each scan
-To indicate from which address on the line to start
Used for X max1 is 1 byte from the number of bytes
It is equivalent to the number subtracted. X When max1 is scanned
Used to check if data is serialized
You. The FSYNC signal 1504 starts the page
From the printer engine 110 to let you know when
Sent. Blank signal 1506 indicates that data is blank
Let me know when it will be done. When data is blanked,
The linter engine 110 does not print anything on the page,
The page is white. First, X current is X max and
Are equivalent. X current is the register
Current address in file 306 is the next scan line
Compared with the start address (base-current)
Used by PVP 300 to determine if
Flag. If X-current is 1 or less
PVP 300 checks for overlap
You. X max is allowed on the scan line
Indicates the maximum number of bytes. Basically, X max is a special feature
Set to a fixed value, and then a byte is
As it is sent to the gin 110, its value
It is decremented to operate. Good
In a preferred embodiment, X max is 96 bytes (60
h). But in practice, scanning
Lines can be no more than 89 bytes, but
X in the example max is cut to the nearest multiple of 8 bytes
It has been raised. The memory read request is sent to the printer engine
Mechanism during printing of the button 110 (shown herein
Does not scan the top margin,
Sent by PVP 300 to memory. Reference number 15
17 shows in FIG. 17 the register file 3
Base address, which is the current address stored in
"7ffffddh" ("h" at the end means hexadecimal
) Is an input / output address “7ffffddh”.
Is sent to the memory. fundamentally,
The last two bits of the input / output address sent to the memory are zero.
This is the current address masked by b. Therefore, PVP3
All input and output addresses sent to memory by 00
It is a word address, not a byte address. The input / output address is written to the memory
According to another feature of the present invention, the write signal
Command of the ERASE bit in the command register 314
After each read request. Reading
Data is transferred from the memory to the PVP 300 by the read request
Sent. The next write request is
Notify memory to write zero to location
To clear that location in memory
You. To the above address “7ffffdch”
As a result of the memory read request
Code (4 bytes) in the scan data queue 344
Is loaded. Data requested by PVP 300
The amount of data depends on the specific I / O address sent to memory.
Therefore, it is determined. Next, the retrieved data is stored in columns (
As shown in column 1510,
Cleared inside. One word consisting of 4 bytes
Is loaded into the PVP 300, so X ma
x is decremented from 60h to 5ch
However, 60h represents 96 bytes and 5ch is 92 bytes.
Represents The column indicated by reference numeral 1512 is a PVP.
Represents another read request sent from 300 to memory
I have. The current address in the register file 306 is “7
ffffelh ”. The last two bits are
Mask to zero to generate dress "7fffffe0h"
Has been locked. Input / output address "7ffff0h"
As a result of the addressed memory read request,
Is loaded into scan data queue 344
You. As shown in the column indicated by reference numeral 1512, the same four
The word is cleared in memory. In addition, 16 bytes
Are loaded into the PVP 300
X max decrements from 5ch to 4ch
5ch represents 92 bytes and 4ch
ch represents 76 bytes. The column indicated by reference numeral 1514 is the pixel
After serialization is started, sent from PVP300 to memory
Represents another read request to be performed. Register
The current address in the file 306 is “7ffffff1h”
And its related input / output address is "7ffffff0h".
is there. At this time, no more words are scanned
Is not loaded into the data queue 344 because it is
Scan data queue in the preferred embodiment
(FIFO) 344 stores only 32 bytes
is there. Word low in scan data queue 344
The clear function does not occur because it is not loaded. But
X current is decremented to 3ch
You. The blank signal is deasserted (deassertion).
rt) at which point the scan data queue 344
Already has data to print, so PVP3
00 immediately serializes the data and prints
Can be sent to the gin 110. First scan line
As shown at 1516, the printer engine 110
Print 3 bytes from the address sent to column 1510
Can be In addition, the printer engine 110
Is shown on the first scan line 1516
As shown in FIG.
Site can be printed. Scan data queue 344 contains data
When the volume is low, as column 1518 shows,
And read it further into memory to have the data sent.
Send out request. Further, the word in the memory is
May not be cleared at the end of the
Signal is reasserted).
Consider column 1520 in FIG. That searched
Four words are not cleared in column 1522. Why is it
Then because the next address set overlaps
is there. Specifically, “80000036h” is changed to “800
00030h ". Clearly,
The three memory read requests are sent to the printer engine 11
0 is ready to print the next scan line 1528
Before it is done. [0100] As described above, according to the present invention, a new professional
Having a processor and processing
Equipment with a processor that can minimize the burden
An arrangement and control method is provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a typical page printer system. FIG. 2 is a diagram showing a specific method of realizing a page printer system. FIG. 3 is a high-level block diagram of the printer video processor shown in FIG. 4 is a low-level block diagram of the controller 1 shown in FIG. 5 is a low-level block diagram of the controller 2 shown in FIG. FIG. 6 is a low level block diagram of the video data queue of FIG. FIG. 7 is a low-level block diagram of the clock divider shown in FIG. 8 is a diagram illustrating a methodology implemented by a state machine in the controller 1 shown in FIG. 9 is a diagram illustrating a methodology implemented by a state machine in the controller 1 illustrated in FIG. FIG. 10 shows states in the controller 1 shown in FIG.
FIG. 3 is a diagram illustrating a methodology implemented by a machine. FIG. 11 shows states in the controller 1 shown in FIG.
FIG. 3 is a diagram illustrating a methodology implemented by a machine. FIG. 12 shows states in the controller 1 shown in FIG.
FIG. 3 is a diagram illustrating a methodology implemented by a machine. FIG. 13 shows states in the controller 1 shown in FIG.
FIG. 3 is a diagram illustrating a methodology implemented by a machine. FIG. 14 shows a state in the controller 1 shown in FIG.
FIG. 3 is a diagram illustrating a methodology implemented by a machine. FIG. 15 shows states in the controller 1 shown in FIG.
FIG. 3 is a diagram illustrating a methodology implemented by a machine. FIG. 16 shows states in the controller 1 shown in FIG.
FIG. 3 is a diagram illustrating a methodology implemented by a machine. FIG. 17 illustrates an example of I / O addressing generated by the printer video processor for front mode. FIG. 18 illustrates an example of I / O addressing generated by the printer video processor for front mode. FIG. 19 illustrates an example of I / O addressing generated by the printer video processor for backside mode. [Description of References] 102: microprocessor for instructions, 104: printer video processor, 106: page memory, 108
... Serial communication interface, 110 ... Printer
Engine, 200 ... Page printer controller, 2
04: system memory, 206: I / O interface, 208: memory system.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-264368 (JP, A) JP-A-2-156325 (JP, A) JP-A-1-249352 (JP, A) JP-A-63- 155321 (JP, A) JP-A-62-74663 (JP, A) JP-A-3-285456 (JP, A) JP-A-4-140163 (JP, A) JP-A-5-278304 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) B41J 5/30 B41J 2/44 G06F 3/12 G06F 15/177

Claims (1)

(57) [Claim 1] At least a first processor that issues instructions and a second processor that communicates with a memory, scan data fetch, serialization, and synchronization with a printer Storing a frame buffer address and a format constant in a file register; and verifying that the printer is ready to process data by the second processor. Notifying the printer that the data is to be printed by the control software of the first processor to the printer; and relating the print command to the second processor by the control software. Loading a command register; and Asserting the frame synchronization signal to the processor; taking the time of the top margin of the page; waiting for the line synchronization signal to be sent from the printer; and left margin of the page. Fetching an image frame to be sent to the printer by the second processor; synchronizing with the clock of the printer, serializing the image frame to a scan line to convert the image frame into a scan line. At the end of each scan line, waiting for the next line synchronization signal and the start of the left margin timer until scanning of the image frame is completed. Control method.