JP3432043B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, the present invention relates to a method for manufacturing a semiconductor device having a depletion mode type transistor (hereinafter referred to as D-FET) and an enhancement mode type transistor (hereinafter referred to as E-FET). Furthermore, the present invention particularly relates to a method for manufacturing a semiconductor device which is formed on the main surface of a semi-insulating substrate formed of a GaAa compound semiconductor and is suitable for a Schottky junction type transistor (hereinafter referred to as MESFET).

[0002]

2. Description of the Related Art Conventionally, in the manufacturing technology of semiconductor devices,
When D-FET and E-FET are formed on the same wafer by an ion implantation method, an ion implantation step of forming a channel region (active layer) of D-FET, an ion implantation of forming a channel region of E-FET. The steps are provided separately. That is, since the D-FET and the E-FET have different ion implantation conditions, particularly acceleration energy setting and implantation dose setting, the channel region is inevitably formed in two separate steps.

4A to 4F are process cross-sectional views showing a conventional semiconductor device manufacturing method in which a two-step implantation method is adopted for each step. In the first step, FIG.
As shown in FIG. 3, the mask 2 is formed on the main surface of the substrate 1. A compound semiconductor, especially a GaAs semi-insulating substrate (wafer) is used as the substrate 1. A photoresist mask is used for the mask 2. The mask 2 is opened at least in the formation region of the channel region of the E-FET. The mask 2 is formed to have a thick film thickness so that channel forming impurity ions (hereinafter, simply referred to as ions) do not pass in the D-FET formation region.

In the second step, as shown in FIG. 4B, the mask 2 is used, and ions are implanted into the main surface portion of the substrate 1 through the opening of the mask 2. Reference numeral 3 is a region into which ions are implanted (a region that becomes a channel region when activated by annealing in a later step). Ions are implanted by the ion implantation method, and low acceleration energy is used for the implantation. Si ions are used as the ions. And
In the third step, the mask 2 is removed as shown in FIG.

In the fourth step, as shown in FIG. 4D, the mask 4 is formed again on the main surface of the substrate 1. As the mask 4, a photoresist mask is used for the mask 4. In the mask 4, at least the formation region of the channel region of the D-FET is opened.

In the fifth step, as shown in FIG. 4E, the mask 4 is used, and ions are implanted into the main surface portion of the substrate 1 through the opening of the mask 4. Reference numeral 5 is a region into which ions are implanted. Ions are implanted by an ion implantation method, and high acceleration energy is used for the implantation. Si ions are used as the ions. Then, in the sixth step, as shown in FIG. 4F, the mask 4 is removed.

After that, the respective ions implanted in the regions 3 and 5 are activated to form a channel region. The activation is performed by annealing (heat treatment). Although not shown in FIGS. 4A to 4F, a Schottky junction gate electrode is formed after the channel region is formed, and a source region and a source region are formed before or after the channel region is formed. A drain region is formed.

Upon completion of each of these steps, MESFE
T is formed, and D-FET and E-FET are formed at the same time.

Next, the electrical characteristics of the MESFET in which the channel region is formed by the ion implantation method will be described. For simplicity of explanation, it is assumed that the implanted Si ions are 100% carriers. Usually, the ions immediately after being implanted by the ion implantation method do not act as carriers, only crystal defects are generated in the substrate 1, and the activation of the channel region is not achieved. Heat treatment (drive-in diffusion treatment) is used to activate the channel region, and the implanted ions can be activated by repairing crystal defects to function as carriers. As described above, in general, 100% complete activation cannot be realized, so the amount of ion implantation is determined in consideration of the ratio of activation in the design of a semiconductor device. However, in the following description, for the purpose of facilitating the understanding of the present invention, the implanted ions are 10
0% is assumed to function as a carrier.

G. W. Taylor,
H. M. Darley, R. C. Frye and P. K. Chatterj
ee, IEEE Trans. Electron Devices. ED-2
6, 1979, pp. 72-192. ), The concentration distribution of the implanted ions can be approximated to a Gaussian distribution (the peak of the concentration distribution is represented by the implantation depth R _P and the dispersion width of the concentration distribution is represented by σ _P ). , MESFE
The threshold voltage V _{TH of} T is expressed by the following equation (1).

[0011]

[Equation 1] V _TH : threshold voltage V _φ : metal-semiconductor work function Δ: depth of Fermi level in conduction band in D-FET q: charge Q: implantation dose N _A : impurity concentration of substrate V _bi : internal potential V _BS: substrate - source voltage, where impurities in the substrate for simplicity are not doped (N _a → 0) consider the case, metal - semiconductor between work function V _phi, the Fermi level depth Δ When each is considered, the threshold voltage V _{TH of the} MESFET is calculated by the following equation (2).
It is represented by.

[0012]

[Equation 2] FIG. 5 shows the dose Q and the threshold voltage V according to the above equation (2).
It is a figure showing the relationship with TH. In FIG. 5, the results obtained by accelerating the acceleration voltage at the time of ion implantation to a plurality of levels are plotted. Actually, the implantation depth R _P of the peak of the concentration distribution corresponding to the acceleration voltage at the time of ion implantation and the dispersion width σ _{P of the} concentration distribution are calculated according to the LSS theory,
This calculated value is substituted into the formula of threshold voltage V _TH ,
The threshold voltage V _TH is required.

The work function V _φ between metal and semiconductor is usually 0.7.
Since the value is around V, the implantation dose Q is 1.0 × 10.
^{When 12} atoms / cm ² and an acceleration voltage of 45 KeV are selected, the threshold voltage V _TH can be set to 0.2V. The MESFET set to this threshold voltage V _TH is a normally-off type, and an E-FET can be formed. Further, when the implantation dose Q is the same and the acceleration voltage is selected to be 100 KeV, the threshold voltage V _TH can be set to -0.5V. The MESFET set to this threshold voltage V _TH is a normally-on type, and a D-FET can be formed.

On the other hand, the acceleration voltage is fixed at 60 KeV,
When the implantation dose Q is selected to be 7.2 × 10 ¹¹ atoms / cm ² , an E-FET can be formed, and when the implantation dose Q is selected to be 1.9 × 10 ¹² atoms / cm ^2. Is DF
ET can be formed. That is, the E-FET and the D-FET can be made separately by changing the setting value of the implantation dose Q.

[0015]

In the manufacturing technology of the semiconductor device having the above-mentioned E-FET and D-FET,
Although the E-FET and the D-FET can be formed on the same substrate 1 (wafer) by the two-step ion implantation process, the following points have not been taken into consideration. (1) Each channel region of the E-FET and D-FET is formed in a separate process, and the ion implantation process of two times in total exists as a completely separated process. That is, in the ion implantation apparatus, the first ion implantation is performed, and then the mask 2 used in the first ion implantation is removed, and the mask 4 used in the second ion implantation is formed. Exists, and a long interrupt time is required between the two ion implantation steps. Therefore, in the ion implantation apparatus, the dose capacity such as implantation dose and energy changes, and the threshold voltage V _TH of each of E-FET and D-FET varies independently in each process. That is, the variation in the relative threshold voltage V _TH difference between the E-FET and the D-FET becomes very large, and the circuit characteristics as designed cannot be obtained, so that the manufacturing yield of the semiconductor device decreases. To do. (2) As described above, as a method of forming the E-FET and the D-FET, a method of fixing the acceleration voltage and a method of fixing the implantation dose amount are known. Since the interrupt time exists between the first ion implantation step and the second ion implantation step, it is difficult to adopt the method of changing the acceleration voltage while maintaining the operating state of the ion implantation apparatus stable. . Therefore, generally, a method of changing the dose amount while fixing the acceleration voltage is adopted. However,
In this method, since the implantation dose amount is different between the first ion implantation step and the second ion implantation step, the degree of damage generated in the substrate 1 (channel region) is different. Therefore, the activation rate, the characteristics of the active layer, and the like are varied in the activation (heat treatment) after the ion implantation, and the circuit characteristics as designed cannot be obtained, so that the manufacturing yield of the semiconductor device is reduced as described above. .

The present invention has been made to solve the above problems, and an object of the present invention is to provide an E-FET and a D-FE.
It is to improve the manufacturing yield in a method of manufacturing a semiconductor device having T. In particular, the present invention is an E-FET, D
-Effective in the manufacturing method of the compound semiconductor device in which each FET is formed of MESFET.

[0017]

In order to solve the above-mentioned problems, the invention according to claim 1 is a method of manufacturing a semiconductor device, wherein a second region different from the first region with respect to the first region of the main surface of the substrate is used. A through implantation mask that can decelerate the acceleration energy of the impurity ions for channel formation that are implanted in the region
A step of forming on the main surface of the substrate by a lift-off method ,
The through implantation mask is provided in the first region of the main surface of the substrate.
A first region having a channel region set to a first threshold voltage by injecting impurity ions for channel formation indirectly through
While forming the transistor, the transistor is directly formed through the opening of the through implantation mask in the second region of the main surface of the substrate in the same step and with the same acceleration energy and the same dose amount.
And a step of forming a second transistor having a channel region set to a second threshold voltage different from the first threshold voltage by injecting the channel forming impurity ions. And

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the step of forming the first transistor and the second transistor is EF.
It is characterized in that it is a step of forming ET and D-FET.

Further, according to a third aspect of the invention, in the method of manufacturing a semiconductor device according to the second aspect, the step of forming the through implantation mask on the main surface of the substrate is a main surface of a semi-insulating substrate. Forming the through implantation mask in the first region above, the first transistor and the second transistor
The process of forming a transistor is MESFE of E-FET
It is a step of forming MESFETs of T and D-FETs.

[0020]

In the present invention, the selective through implantation method is adopted as the ion implantation method, and the ion implantation process which has been divided into two steps is integrated into one ion implantation process, and the threshold voltage (V
First and second transistors having different _TH ) can be formed in the same process. Since the channel regions of the first and second transistors are formed in a single ion implantation process performed simultaneously, the implantation dose amount is kept constant and the acceleration voltage is kept constant. Furthermore, the implantation depth (R _P ) of the peak of the concentration distribution in the channel region can be controlled by adjusting the film thickness of the through implantation mask. Therefore, the relative variation between the threshold voltage of the first transistor and the threshold voltage of the second transistor can be reduced. Further, the degree of damage caused by ion implantation can be made equal in the channel formation region (substrate main surface portion) of the first transistor and the channel formation region of the second transistor.

[0021]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 is a sectional view showing the basic structure of a MESFET mounted on a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the MESFET is formed on the main surface of the substrate 10, and the MESFET is formed on the channel region 11.
Source region 12, drain region 12 and gate electrode 13
Equipped with. As the substrate 10, a semi-insulating substrate formed of a GaAs substrate is used. The channel region 11 is an E-FET
The concentration distribution (reference numeral 11E) that can be set to the threshold voltage of 11 or the concentration distribution (reference numeral 11D) that can be set to the threshold voltage of D-FET. Normally, the MESFET is used as a high frequency device, and high-speed switching characteristics are required, so that the n-type is used. The source region 12 and the drain region 12 are formed with a higher concentration distribution than the channel region 11 in order to improve ohmic characteristics. A source electrode 14 is electrically connected to the source region 12, and a drain electrode 14 is electrically connected to the drain region 12. The source electrode 14 and the drain electrode 14 have, for example, A
An ohmic metal in which u, Ge, and Ni are sequentially stacked is used. The gate electrode 13 is in contact with the surface of the channel region 11 by a Schottky junction. For the gate electrode 13, Ti-
A Schottky junction metal formed of Pt-Au is used.

In the present invention, the selective through implantation method is adopted as the method for forming the MESFET described above, and in this selective through implantation method, the nature of the depth shift of the ion implantation layer (channel region 11) at the time of the through implantation is positive. Used. The depth shift control will be described later, and the manufacturing method that first adopts the selective through implantation method, that is, E
A method of manufacturing -FET and D-FET on the same substrate (wafer) 10 will be described. 2 (A) -FIG. 2
(F) is a sectional view showing each step for explaining the manufacturing method of the above MESFET. Note that FIG. 2A to FIG.
In (F), only the respective channel formation region portions of the E-FET and D-FET are shown, and the explanation is simplified to facilitate understanding of the present invention.

First, the lift-off method is used and the substrate 10 is used.
Through implantation mask 16 is formed on the main surface of. That is, in the first step, as shown in FIG. 2A, the mask 15 is formed in the D-FET formation region on the main surface of the substrate 10. For the mask 15, for example, a resist film formed by a photolithography technique is used. In the second step, as shown in FIG. 2B, a through implantation mask 16 is formed on the entire main surface of the substrate 10 including the mask 15. As the through implantation mask 16, for example, a Si ₃ N ₄ film suitable for depth shift control in MESFET is used,
The Si ₃ N ₄ film is formed by a deposition method such as an ECR method or a sputtering method, which has excellent deposition directionality. The present invention can be applied to a MISFET formed on a Si substrate.
In the case of T, a SiO ₂ film is preferable as a through implantation mask. In the third step, as shown in FIG. 2C, the mask 15 is selectively removed, and the mask 15 is removed and the unnecessary through implantation mask 1 on the mask 15 is removed.
6 is removed. As a result, the through implantation mask 16 having an opening in the D-FET formation region and covering the E-FET formation region is completed. In the through implantation mask 16, the presence or absence of an opening can control the depth shift of implanted ions. In the present invention, the through implantation mask 1 is previously prepared.
6 can be formed, and an opening can be formed by combining a mask formed by a photolithography technique and etching using this mask. However, in order to reduce damage to the main surface of the substrate 10 due to etching, the through implantation is used in the present invention. A lift-off method is used to form the mask 16.

In the fourth step, as shown in FIG. 2D, a mask 17 is formed on the through implantation mask 16. An opening is formed in the mask 17 at least in the channel forming region of the E-FET and the channel forming region of the D-FET. A resist film formed by, for example, a photolithography technique is used for the mask 17. The through implantation mask 16 allows implantation ions to pass, but the mask 17 does not permit implantation ions to pass.

In the fifth step, as shown in FIG. 2 (E), the mask 17 and the through implantation mask 16 are used, and the channel forming region of the E-FET is formed by ion implantation.
Channel forming impurity ions are simultaneously implanted into each of the channel forming regions of the D-FET. In the channel formation region of the E-FET, a through implantation mask 16 is added in the opening of the mask 17, and ions are indirectly implanted. On the other hand, in the channel formation region of the D-FET, ions are directly implanted in the opening of the mask 17 and the opening of the through implantation mask 16. In the ion implantation, the implantation dose amount and the acceleration voltage that can obtain the threshold voltage of the D-FET are set. In the channel forming region of the E-FET, as compared with the channel forming region of the D-FET, the acceleration energy is reduced by the through implantation mask 16 and the depth of implanted ions is shifted (becomes shallower). As a result, the threshold voltage of E-FET, D-FE
Each threshold voltage of T can be adjusted. Reference numeral 11E is E-
An ion implantation region is formed by implanting ions into the channel formation region of the FET, and a reference numeral 11D is an implantation region in which ions are implanted into the channel formation region of the D-FET. Ions are implanted by an ion implantation method, and for example, Si ions as n-type impurity ions are used as the ions. Then, in the sixth step, as shown in FIG. 2F, the mask 17 and the through implantation mask 16 are removed.

Thereafter, the respective ions implanted in the implantation regions 11E and 11D are activated, and the channel region 11 is formed.
Is formed. The activation is performed by heat treatment.
Although not shown in FIGS. 2A to 2F, after the channel region is formed as shown in FIG. 1, the Schottky junction type gate electrode 13 is formed and the channel region 11 is formed. The source region 12 and the drain region 12 are formed before or after the formation.

Upon completion of each of these steps, MESFE
T is formed, and D-FET and E-FET are formed at the same time.

Next, a method of calculating the required depth shift amount will be described. FIG. 3 is a diagram showing the relationship between the dose Q, the threshold voltage V _TH, and the peak implantation depth R _P of the concentration distribution. As shown in FIG. 3, the acceleration energy is 60 KeV.
In the case of direct injection at, the peak injection depth R _P is 510
Become Å. Threshold voltage V _TH of D-FET is -0.5V
If set to a peak implant depth threshold voltage V _TH of the E-FET with the same dose can be set to 0. 2V R _P
For example, 150Å can be selected. That is, the threshold voltage of the E-FET and the D-FET can be obtained by performing the ion implantation once.
360 peak implant depth R _P to obtain a threshold voltage of the
A depth shift of Å is required. In other words, the film thickness of the through implantation mask 16 is set to a film thickness that can obtain the depth shift.

The method of estimating the depth shift amount from the direct implantation in the through implantation method is H. Ryssel (H. Rysse
l and Hoffman: in "Process and Device Simul
ation for MOS VLSI Circuits ", P. 29
5. 1983. ) Has proposed the following method. The distribution C (X) of implanted ions is expressed by the following equation (3) as a function of the implantation direction depth X (the coordinate origin is the surface of the through implantation mask).

[0031]

[Equation 3] In the above formula (3), C (X) is the implantation distribution when the substrate 10 itself has the same composition as the through film. t is the film thickness of the through implantation mask 16, σ _P1 is the distribution width of the implantation distribution of the substrate 10, and σ _P2 is the distribution width of the implantation distribution of the through implantation mask 16. The wider the dispersion width of the implantation distribution, the lower the deceleration ability of the implanted ions, and conversely, the narrower the dispersion width, the higher the deceleration ability of the implanted ions. Therefore, σ _P1 / σ _P2 in the formula of the injection distribution C (X) means the speed reduction capability ratio. That is,
It is easy to understand if it is thought that the through implantation mask has a high deceleration ability, and deceleration proceeds quickly even at the same depth, and it seems as if the implantation depth itself becomes shallow. Here, when the dispersion width of the implantation distribution is σ _P1 = σ _P2 (for example, the substrate 10
When the and through implantation mask 16 are made of the same material), there is no depth shift. However, if the through implantation mask is removed after the ion implantation, the distribution depth from the surface of the substrate 10 becomes shallower by the film thickness t of the through implantation mask 16.

In this embodiment, the substrate 10 made of a GaAs substrate is provided with a through implantation mask 16 made of a Si ₃ N ₄ film.
The case where Si ₃ N ₄ is formed is explained.
When the composition (denseness) of the film is different, the dispersion width σ _{P2 of the} injection distribution
Varies depending on the composition of the film. For example, in this embodiment, σ _P1 / σ _P2 = 1.6 and the depth shift amount is 360.
When the film thickness t of the through implantation mask 16 is obtained as Å, t = 360Å / 1.6 = 225Å. Therefore, if the through implantation mask 16 is set to have a film thickness of 225 Å, DF can be obtained in one ion implantation process.
The threshold voltage V _{TH of} ET can be set to -0.5V, and at the same time, the threshold voltage V _TH of E-FET can be set to 0.2V.

[0033]

As described above, in the present invention, the selective through implantation method is adopted as the ion implantation method, and the ion implantation step which has been divided into two steps is integrated into one ion implantation step, and the threshold value is reduced. The first and second transistors having different value voltages can be formed in the same process. Since the channel regions of the first and second transistors are formed in a single ion implantation process performed simultaneously, the implantation dose amount is kept constant and the acceleration voltage is kept constant. Further, the implantation depth of the peak of the concentration distribution in the channel region can be controlled by adjusting the film thickness of the through implantation mask. Therefore, the relative variation between the threshold voltage of the first transistor and the threshold voltage of the second transistor can be reduced. Further, the degree of damage caused by ion implantation can be made equal in the channel formation region of the first transistor and the channel formation region of the second transistor. As a result, in the semiconductor device manufacturing method, the manufacturing yield can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a basic structure of a MESFET mounted on a semiconductor device according to an embodiment of the present invention.

2A to 2F are cross-sectional views showing each step of the method for manufacturing the MESFET described above.

FIG. 3 is a diagram showing a relationship between a dose amount, a threshold voltage, and a peak implantation depth of a concentration distribution.

4A to 4F are process cross-sectional views showing a conventional method of manufacturing a semiconductor device in which a two-step implantation method is adopted for each process.

FIG. 5 is a diagram showing a relationship between a dose amount and a threshold voltage.

[Explanation of symbols]

10 substrate, 11, 11E, 11D channel region, 1
2 source regions or drain regions, 13 gate electrodes,
14 source or drain electrode, 15 and 17 mask, 16 through implantation mask.

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 27/095 H01L 21/338 H01L 29/812 H01L 21/266

Claims (3)

(57) [Claims] 1. A through implantation mask capable of decelerating acceleration energy of impurity ions for channel formation which is ion-implanted into a second region different from the first region with respect to the first region of the substrate main surface by a lift-off method. And the through implantation mask in the first region of the main surface of the substrate.
A first region having a channel region set to a first threshold voltage by injecting impurity ions for channel formation indirectly through
While forming the transistor, the transistor is directly formed through the opening of the through implantation mask in the second region of the main surface of the substrate in the same step and with the same acceleration energy and the same dose amount.
Comprising: the step of forming a second transistor having a channel region set to indirectly the implanting impurities for forming a channel ion the first threshold voltage and different from the second threshold voltage, the And a method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the first transistor and the second transistor is a step of forming an enhancement mode type transistor and a depletion mode type transistor. A method of manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the through implantation mask on the main surface of the substrate is performed in the first region on the main surface of a semi-insulating substrate. A method of manufacturing a semiconductor device, which is a step of forming a through implantation mask, wherein the step of forming the first transistor and the second transistor is a step of forming an enhancement mode type MESFET and a depletion mode type MESFET.