JP3433466B2 - Multiplication circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier using Booth's algorithm suitable for digital signal processing.

[0002]

2. Description of the Related Art A multiplier for multiplying a coefficient K by sampling data D of a digital signal is used in a digital signal processing circuit. Conventionally, a multiplier used for such digital signal processing is as shown in FIG.
It is composed of a partial product generation unit 101 and a partial product addition unit 102. The partial product generation unit 101 obtains a partial product with the data D for each bit of the coefficient K. The partial product addition unit 102 adds these partial products. As a result, the product of the coefficient K and the data D is substituted into the multiplication value P, and P ← K × D is obtained.

In digital signal processing, it is sometimes desired to perform special arithmetic processing in addition to such multiplication of positive numbers. For example, suppose now that a multiplication of P ← −K × D is desired. The configuration shown in FIG. 6 cannot directly execute such multiplication.

Therefore, conventionally, when multiplying by such a negative coefficient, a cumulative adder used together with a multiplier is used. That is, the basic operation of digital signal processing is multiplication and addition. Therefore, as shown in FIG. 7, the cumulative adder 111 is used together with the multiplier 110. The cumulative adder 111 includes an adder 103 and a register 104.

A bit inverting unit 105 is provided at the input of the cumulative adder 111 as shown in FIG. A signal C0 is supplied to the bit inverting unit 105 from the input terminal 122. Further, this signal C0 is the maximum value of the adder 103.
Input to carry of lower bit .

The bit inverting section 105 is composed of EX-OR gates 121 _{0 to} 121 _47, as shown in FIG. Each bit of the output of the multiplier 110 is supplied to one of the input terminals 120 _{0 to} 120 ₄₇ of the EX-OR gates 121 _{0 to} 121 ₄₇ . EX-OR gate 121
₀ The to 121 ₄₇ the other input terminal of the signal C0 is supplied from the input terminal 122. EX-OR gates 121 ₀ to 1
The output of 21 ₄₇ is output from the output terminals 123 _{0 to} 123 ₄₇ .

In FIG. 8, the signal C0 from the input terminal 122 is supplied to the lowest carry of the adder 103, and as a result,

[Equation 6] Therefore, the calculation ± K × D can be equivalently performed.

[0008]

As described above, in the conventional multiplication circuit, the bit inverting section 105 is provided. If the coefficient K is 16 bits and the data D is 32 bits, 48 EX-OR gates are required as the bit inversion unit 105. Therefore, the circuit scale increases.

Further, conventionally, since the lowest carry input is provided in the adder 103, there is a problem that the time required for addition becomes long.

Furthermore, conventionally, in order to perform the special operation of P ← D, it is necessary to flow a value of -1 to the data bus, which lowers the utilization efficiency of hardware. Similarly, P ←
Even when performing the operation K, it is necessary to pass a value of -1 to the data bus.

That is, P ← D To do the multiplication, K = -1 As P ← (-1) × D And then C0 = 1 As

[Equation 7] It is said that

However, in this case, since the input of the multiplier / adder is normally connected to the data bus, it is necessary to flow the data of -1 to the data bus on the K side, and the utilization efficiency of the hardware is deteriorated. Resulting in.

Therefore, an object of the present invention is to provide P ← (−K) × D, P ← D, P without increasing the circuit scale.
It is to provide a multiplication circuit that can perform a special operation such as ← K.

[0014]

The present invention is a two's complement table.
Multiply the expressed multiplier K by the multiplicand D represented by two's complement
It uses Booth's algorithm to calculate the multiplication value P
In the multiplication circuit, the 2's complement multiplier K is
It consists of the upper sign bit and each bit of the numerical value,

[Equation 8] And the multiplicand D expressed in 2's complement is
Consisting of the sign bit of the place and each bit of the numerical value,

[Equation 9] , The sign bit of the multiplier K expressed as 2's complement
A sign bit input means bets is inputted, complement of expression 2
Numeric bit input in which each bit of the numerical value of the multiplier K is input
And a sign bit of the two's complement multiplier K and
A gate signal is provided to gate each bit of the number.
Gate signal input means, and a multiplier K expressed in two's complement
First input for setting the inversion / non-inversion of the sign bit of
Sign bit inversion / non-inversion input means to which a force signal is supplied
And the inversion of each bit of the number of the multiplier K expressed in 2's complement
/ Second input signal for setting non-inverted is provided
Numerical bit inversion / non-inversion input means and gate signal input
The first output signal based on the gate signal input from the stage.
0 as the number or 2 of the number supplied to the sign bit input means
A first gear that outputs the sign bit of the complemented multiplier K
Gate input from the gate signal input means
0 or a number as the second output signal, respectively, based on the signal
2's complement multiplier supplied to the value bit input means
Second gate means for outputting each bit of the numerical value of K, and a sign
No. 1 bit input from the bit inversion / non-inversion input means
The first gate means outputs a first signal based on the force signal.
The inverted value or non-inverted value of the output signal of 1 is used as the third output signal.
A sign bit inversion / non-inversion means for and outputting numerical bit
Second input signal input from the inverting / non-inverting input means
Based on the second output means output from the second gate means.
Outputs the inverted or non-inverted value of the force signal as the fourth output signal.
Numerical value bit inversion / non-inversion means and sign bit inversion
/ Third output signal output from the non-inverting means and a numerical value
Fourth output signal output from bit inversion / non-inversion means
For each bit of
And Booth encoder to perform over de, out of the booth encoder
A section for obtaining a partial product of the force and the multiplicand D represented by two's complement
It was expressed in 2's complement by adding the partial product and the partial product.
The multiplication value P of the multiplier K and the multiplicand D represented in two's complement is output.
And a partial product adding means for force, most of the Booth encoder
Input to the lower digit from the numerical bit inversion / non-inversion input means
And a second input signal to be supplied, which is a multiplication circuit.

In the present invention, the multiplier transforming unit represents the multiplier K by a second-order Booth algorithm.

[Equation 10] All bits inverted least significant bi Booth encoder of K
The sign inversion value of K can be obtained by setting the input of
To be

In the present invention, the multiplier transforming unit represents the multiplier K by a second-order Booth algorithm.

[Equation 11] And K _l-1 = 0 of the _{K l-2 = K l-} 3 = K l-4 ··· K 2 = K 1 = K 0 = K -1 = 1, the least significant bit of the Booth encoder input To 1
By doing so, a value of K of 1 is obtained.

According to the present invention, the multiplicand transformation unit converts the multiplicand D represented by 2's complement.

[Equation 12] 0 can be input as D _n-1 = 0, D _n-2 = D _n-3 = D _n-4 ... = D ₂ = D ₁ = D ₀ = 0 .

[0018]

In the multiplier using the Booth's algorithm for obtaining the multiplication value P by multiplying the multiplier K represented by 2's complement and the multiplicand D, the multiplier K input to the partial product generator for generating a partial product is By including a multiplier transforming unit that transforms and a multiplicand transforming unit that transforms the multiplicand D input to the partial product generating unit, it is possible to perform a special transformation such as P ← (−K) × D, P ← D, P ← K. Can perform calculations.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In Figure 1, 1 _{0-1 15} is an input terminal of the coefficient K. The input terminal 1 _{0-1 15,} signals of the respective bits of the 16 bit modulus K (k0~k15) is supplied. This coefficient K is represented by a two's complement.

Reference numerals 2 _{0 to} 2 ₃₁ are input terminals for data D.
The input terminal 2 _{0-2 31,} 32-bit data D (d0
The signal of each bit of (-d31) is supplied. Data D
Is expressed in 2's complement.

Reference numeral 3 is a K deforming portion. This K deformation part 3
AND gates 4 ₀ to 4 ₁₅ and EX-OR gates 5 _{0 to} 5
Consists of ₁₅ and.

One input terminal of each of the AND gates 4 ₀ to 4 ₁₅ is connected to each of the input terminals 1 ₀ to 1 ₁₅ . AND
Gate 4 _{0-4 15} the other input terminal of each of the control signal K
It is connected to the input terminal 6 of CL0.

[0023] One input terminal of the EX-OR gate 5 _{0-5 15} is connected to the output terminal of each of AND gates 4 _{0-4 15.} The other input terminals of the EX-OR gates 5 _{0 to} 5 ₁₄ are
Is connected to the input terminal 7 of the control signal K C L1, EX-OR
The other input end of the gate 5 ₁₅ is connected to the input terminal 8 of the control signal KCL2.

Reference numeral 9 is a booth encoder section. Busue <br/> Nko reader unit 9 is composed of a Booth encoder 10 _{0 -} 10 ₈ for secondary Booth encoding process. The Booth encoder 10 _{0 -} 10 ₈ is constructed as shown in FIG.

In FIG. 2, the input terminal 21 for the signal b _k-1
Is connected to the input end of the inverter 24. Inverter 2
The output terminal of 4 is connected to the input terminal of the inverter 27, and is also connected to the input terminals of the AND gate 31 and the AND gate 33. The output terminal of the inverter 27 is the AND gate 3
0, connected to the input end of the AND gate 32.

The input terminal 22 for the signal b _k is an inverter 25.
Connected to the input end of. The output end of the inverter 25 is connected to the input end of the inverter 28, and is also connected to the input end of the AND gate 30 and the input end of the AND gate 33. The output end of the inverter 28 is the AND gate 31, AN
It is connected to the input end of the D gate 32.

The input terminal 23 of the signal b _{k + 1} is the inverter 2
6 is connected to the input terminal. The output end of the inverter 26 is connected to the input end of the inverter 29, and is also connected to the input end of the AND gate 32 and the output terminal 38 of the signal P.

The output terminals of the AND gates 30 and 31 are ORed.
It is connected to the input terminal of the gate 34. The output terminal of the OR gate 34 is connected to the output terminal 36 of the signal S.

The output terminals of the AND gates 32 and 33 are ORed.
It is connected to the input terminal of the gate 35. The output terminal of the OR gate 35 is connected to the output terminal 37 of the signal W.

[0030] In FIG. 1, the input terminal of the signal b _k-1 of the Booth encoder 10 _0, the input terminal 7 of the control signal KCL1
Connected to. Input terminal of the signal bk Booth encoder 10 ₀ is connected to the output terminal of the EX-OR gate 5 _0.
Input terminal of the signal b _{k + 1} of the Booth encoder 10 _0, EX
-Connected to the output of OR gate 5 ₁ .

The input end of the signal b _k-1 of the Booth encoder 10 ₁ is connected to the output end of the EX-OR gate 5 ₁ .
Input of Booth encoder 10 ₁ of the signal b _k is, EX-
It is connected to the OR gate 5 _{and second} output terminals. The input end of the signal b _{k + 1} of the Booth encoder 10 ₁ is connected to the EX-OR gate 5
Connected to the output of ₃ .

Hereinafter, the input ends of the signals b _{k-1 to} b _{k + 1} of the Booth encoders 10 ₂ to 10 _{8 respectively have} three EX-Os.
Each EX-OR gate 5 in which R gates 5 _{3 to} 5 ₁₅ are continuous
It is connected to the output terminals of _{3 to} 5 ₁₅ .

The Booth encoder 10 _{0 -} 10 ₈ of each of the S, W, the output terminal of the P is connected to the input terminal of the selector 16.

Reference numeral 11 is a D deforming portion. The D deformation section 11 is
It is composed of AND gates 12 _{0 to} 12 ₃₁ and an OR gate 13. AND gate 12 _{0-12 31} one input terminal of each of is connected to the input terminal 2 _{0-2 31} of each bit (d0-d31) of the data D. AND gate 12 ₀ ~
The other input terminal of 12 ₃₁ is connected to the input terminal 14 of the control signal DCL0. One input terminal of the OR gate 13 is
The input terminal 15 of the control signal DCL1 is connected.

The outputs of the AND gates 12 _{0 to} 12 ₃₀ are connected to the input terminals of the selector section 16. AND gate 12
The output terminal of ₃₁ is connected to the other input terminal of the OR gate 13. The output of the OR gate 13 is connected to the input terminal of the selector section 16.

The selector section 16 obtains a partial product of the coefficient K and the sampling data D. Selector section 1
6 selects the encoding result of the Booth encoders 10 ₀ to 10 ₇ to obtain a partial product.

The output terminal of the selector section 16 is the partial product addition section 1
8 input terminals. The partial product addition unit 18 adds the partial products. The output of the partial product addition unit 18 is the output terminal 19
Is output from.

In one embodiment of the present invention, the K deforming section 3 is provided for the coefficient K. Further, a D transformation unit 11 is provided for the data D. Such a K deformation part 3
And by providing the D deforming portion 11, P ← (−K) ×
Special arithmetic processing such as D, P ← D, P ← K becomes possible. This will be described in detail below.

The 16-bit coefficient K is expressed in two's complement as follows:

[Equation 13] Is expressed as. Also, the 32-bit data D is
In two's complement,

[Equation 14] Is expressed as.

In general, to reduce the partial product of the multiplication,
Booth's algorithm is used. When the coefficient K is expressed by the second-order Booth algorithm,

[Equation 15] And the operation P ← K × D is

[Equation 16] Is expressed as Here, {-K _{2m + 1} + (K _2m + K _2m-1 ) ・ 2 ^-1 } ... (7) {-K _{2m + 1} + (K _2m + K _2m-1 ) ・ 2 ^-1 } ・ D ・2 ^(m-7) ... (8) Equation (7) is the result of the secondary booth encoding of the second degree, and Equation (8) is the partial product.

Here, in the equation (3), if all the values of K are bit-inverted, and the value of K ₋₁ = 1 (9) is the inversion of K ′,

[Equation 17] And a negative value of K is obtained.

Therefore, if a partial product is generated using the encoding result of the secondary Booth obtained by the equation (9),

[Equation 18] Can be executed.

Further, if K ₁₅ = 0, K ₁₄ = K ₁₃ = K ₁₂ = ... = K ₂ = K ₁ = K ₀ = K _-1 = 1 ... From the equation (3), K (1) = {-0+ (1 + 1) · 2 ⁻¹ } 2 ⁰ + {− 1+ (1 + 1) · 2 ⁻¹ } 2 ⁻² + ... + {− 1+ (1 + 1) · 2 ^-1 } 2 ^{2 (m-7)} + ... + {-1+ (1 + 1) · 2 ^-1 } 2 ^-14 = 1 (14), and P = K (1) × D = D・ ・ ・ (15) is obtained.

Further, if D ₃₁ = 1, D ₃₀ = D ₂₉ = D ₂₈ = ... = D ₂ = D ₁ = D ₀ = 0 (16), then from the equation (2), D = If −1 ≡ D (-1) ... (17),

[Formula 19] The result is obtained.

From the above, in the case of performing multiplication P ← K × D , a circuit for outputting an encoding result satisfying the expressions (3) and (5) is added, and P ← −K × D is executed. To do
A circuit that satisfies the expressions (9) and (10) is added to, and a circuit that satisfies the expressions (13) and (14) is added to execute P ← D, and P ← K is executed. In equation (9), equation (10), (16)
It can be seen that it is sufficient to add a circuit that satisfies the formula.

The equations (3) and (5) can be realized by a multiplier using an ordinary Booth algorithm. The Booth encoder unit 9 performs processing equivalent to the expressions (3) and (5). Further, the selector unit 16 performs a process equivalent to the equation (8) .

The Booth encoder 10 _{0 -} 10 ₈ 2
Inverters 24-26, 27-29 as shown in FIG.
AND gates 30 to 33 and OR gates 34 and 35
Can consist of As is clear from the equation (7), there are five types of encoding results, 0, ± 1/2, and ± 1.
Corresponding to this, the circuit of (1) satisfies the truth table as shown in FIG.

In this table, bk + 1, bk, bk-
1 corresponds to K _{2m + 1} , K _2m , and K _2m−1 in the equation (7), respectively.

If the encoding result is positive, P = 1 and
When it is negative, P = 0 , and when the encoding result is 0, W = S = 0 , when it is 1/2, W = 0, S = 1, and 1 when W.
= 1 and S = 0, it operates as a secondary Booth encoder.

In FIG. 1, in order to generate the inversion of K'which satisfies the expressions (9) and (10), the signals KCL0, KCL1 and KCL2 from the terminals 6, 7 and 8 are respectively set to KCL0 = "H". "KCL1 =" H "KCL2 =" H "(19)

In the case of K (1), the signals KCL0, KCL1 and KCL2 are respectively calculated from the equations (13) and (14): KCL0 = “L” KCL1 = “H” KCL2 = “L” ...・ ・ (20)

From the equation (16), D (-1) is the terminals 14, 1
The signals DCL0 and DCL1 from 5 may be set to DCL0 = "L" DCL1 = "H" (21).

When performing a normal operation of P ← K × D, KCL0 = “H” KCL1 = “L” KCL2 = “L” DCL0 = “H” DCL1 = “L” (22) And FIG. 4 summarizes the relationship between these control signals and the desired multiplication format.

Further, a special operation for executing the bottom stage bk-1 input of the Booth encoder with a zero value will be described.

First, when K and D (-1) are used, P = K.times.D (-1) =-K (23) from the equation (17), and the sign inversion of the K value is obtained.

Next, if K ₁₅ = 1, K ₁₄ = K ₁₃ = K ₁₂ = ... = K ₂ = K ₁ = K ₀ = K _-1 = 0 ... (24) , (3), K (−1) = {− 1+ (0 + 0) · 2 ⁻¹ } · 2 ⁰ + {− 0+ (0 + 0) · 2 ⁻¹ } · 2 ⁻² + ... + {− 0+ (0 + 0) · 2 ⁻¹ } · 22 ( ^m−7) + ... + {− 0+ (0 + 0) · 2 ⁻¹ } · 2 ⁻¹⁴ = −1 (25) When K (-1) and the D value are used, P = K (-1) * D = -D (26), and the sign of the D value can be inverted.

Here, in order to realize the equation (24), the signals KCL0, KCL1 and KCL2 from the terminals 6, 7 and 8 are used.
Are respectively set as KCL0 = “L”, KCL1 = “L”, KCL2 = “H” (27).

Further, the signals KCL0, KCL1 and KCL2
Where KCL0 = “L” KCL1 = “L” KCL2 = “L” (28), the Booth encode result becomes zero, as is apparent from the equation (3). In this state, K (0) = 0 ... (29).

On the other hand, DCL0 = "L" DCL1 = "L" (30) Then, the output of the D deforming section becomes zero as well, D (0) = 0 ... (31) Becomes If this K (0) or D (0) is used, P = K (0) × D = K × D (0) = K (0) × D (0) = 0 (32) Thus, the multiplication result can be forced to zero.

FIG. 5 is a summary of the method of realizing the special operation. In the table, * indicates that the input is arbitrary. When P = 0, K (0) or D (0) is used, so the other multiplication input is arbitrary.

[0061]

According to the present invention, in a multiplier using Booth's algorithm for obtaining a multiplication value P obtained by multiplying a multiplicand K represented by 2's complement and a multiplicand D, partial product generation for generating a partial product is performed. P ← −K × by providing a multiplier transforming unit that transforms the multiplier K input to the unit and a multiplicand transforming unit that transforms the multiplicand D input to the partial product generation unit.
Special operations such as D, P ← D, P ← K can be performed. Such a modification unit can reduce the number of EX-OR gates as compared with a system in which P ← −K × D is equivalently realized by using subtraction in the cumulative addition unit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of an example of a Booth encoder according to the embodiment of the present invention.

FIG. 3 is a schematic diagram used to describe an embodiment of the present invention.

FIG. 4 is a schematic diagram used to describe an embodiment of the present invention.

FIG. 5 is a schematic diagram used to describe an embodiment of the present invention.

FIG. 6 is a block diagram used to describe a conventional multiplication circuit.

FIG. 7 is a block diagram used to describe a conventional multiply- add circuit.

FIG. 8 is a block diagram used to describe a conventional multiply- add circuit.

FIG. 9 is a block diagram of an example of a sign inversion unit in a conventional multiplication circuit.

[Explanation of symbols]

1 ₁ to 1 ₁₅ Coefficient K input terminal 2 ₀ to 2 ₃₁ Data D input terminal 3 K deformation unit 9 Booth encoder unit 11 D deformation unit

Claims (10)

(57) [Claims] 1. A multiplier K expressed as a two's complement and a two's complement.
A boo for obtaining a multiplication value P by multiplying the represented multiplicand D
In the multiplication circuit using the S. algorithm, the above-mentioned 2's complement multiplier K is the most significant code bit.
And each bit of the numerical value. And the multiplicand D expressed as 2's complement above is the most significant sign bit.
And each bit of the numerical value. And the sign bit of the 2's complement multiplier K is input.
The sign bit input means and each bit of the numerical value of the multiplier K expressed in the two's complement described above.
Numerical value bit input means for inputting, and the sign bit and numerical value of the multiplier K represented by the above two's complement
A gate signal is supplied to gate each bit.
Signal input means and inversion / non-inversion of the sign bit of the multiplier K expressed as the two's complement.
A code provided with a first input signal for setting the inversion
Bit inversion / non-inversion input means and inversion of each bit of the numerical value of the multiplier K expressed by the above two's complement
/ Second input signal for configuring a non-inverting is supplied
Numerical value bit inversion / non-inversion input means and a gate signal input from the gate signal input means.
Then, 0 or the sign bit as the first output signal
Of the above two's complement multiplier K supplied to the input means
Based on the gate signal input from the first gate means for outputting the sign bit and the gate signal input means.
Then, as the second output signal, 0 or the numerical value
2's complement expressed multiplier supplied to the input means.
Second gate means for outputting each bit of the numerical value of K
And the sign bit inversion / non-inversion input means
Output from the first gate means based on the input signal of 1
The inverted or non-inverted value of the first output signal applied to the third
Sign bit inversion / non-inversion means for outputting as output signal
And the number input from the numerical bit inversion / non-inversion input means
Output from the second gate means based on the input signal of 2.
The inverted or non-inverted value of the second output signal applied to the fourth
Numerical value bit inversion / non-inversion means to output as output signal
And a third bit output from the sign bit inversion / non-inversion means.
Output signal and output from the numerical bit inversion / non-inversion means
For each bit of the output fourth output signal
Booth encoder for encoding with algorithms
And the output of the Booth encoder and the two's complement representation
A partial product calculating means for obtaining a partial product with the multiplicand D, and a multiplier K expressed as a two's complement by adding the partial products
Outputs the multiplication value P with the multiplicand D expressed as the two's complement
Means for adding partial products, and the least significant digit of the Booth encoder is the numerical bit
The second input signal input from the inverting / non-inverting input means is
A multiplication circuit characterized by being supplied . 2. The two's complement representation of the first output signal
The sign bit of the multiplied multiplier is output and
The output part of the above outputs the numerical part of the multiplier expressed in 2's complement.
The gate signal is supplied to the gate signal input means so that
Feeding, and the sign bit inversion / non-inversion means becomes a non-inverting output
As described above, the sign bit inversion / non-inversion input means has the first
When an input signal is supplied and the numerical bit inversion / non-inversion means produces a non-inversion output
In both cases, 0 is supplied to the least significant digit of the Booth encoder.
To the above-mentioned numerical bit inversion / non-inversion input means so that
The above two's complement table developed by Booth's algorithm by supplying an input signal
The expressed multiplier K is directly supplied to the partial product calculating means.
Multiplier circuit according to claim 1 which is to be. 3. The two's complement representation of the first output signal.
The sign bit of the multiplied multiplier is output and
The output part of the above outputs the numerical part of the multiplier expressed in 2's complement.
The gate signal is supplied to the gate signal input means so that
So that the sign bit inversion / non-inversion means has an inverted output.
To the sign bit inversion / non-inversion input means.
Signal and the above-mentioned numerical bit inversion / non-inversion means produces an inverted output.
Is supplied to the least significant digit of the Booth encoder
The second input to the numerical bit inversion / non-inversion input means
2's complement table developed by Booth's algorithm by supplying a force signal
The sign of the expressed multiplier K is inverted to the partial product calculating means.
The multiplication circuit according to claim 1 , wherein the multiplication circuit is supplied . 4. The first output signal and the second output signal
To the gate signal input means so that 0 is output to
Supply the gate signal, The sign bit inversion / non-inversion means outputs a non-inversion.
First input to the sign bit inversion / non-inversion input means
Supply the signal, When the numerical bit inversion / non-inversion means produces an inverted output,
Is supplied to the least significant digit of the Booth encoder
The second input to the numerical bit inversion / non-inversion input means
By supplying a force signal, 2's complement table developed by Booth's algorithm
The expressed multiplier K is set to (K = 1) and the partial product operator
The multiplication circuit according to claim 1, wherein the multiplication circuit is supplied to the stage. 5. The first output signal and the second output signal
To the gate signal input means so that 0 is output to
Supply the gate signal, The sign bit inversion / non-inversion means has an inverted output
To the sign bit inversion / non-inversion input means.
No. When the numerical bit inversion / non-inversion means produces a non-inversion output
Together with the above booth 0 is supplied to the least significant digit of the coder
To the above-mentioned numerical bit inversion / non-inversion input means so that
By supplying the input signal, 2's complement table developed by Booth's algorithm
The expressed multiplier K is set to (K = -1), and the partial product operation is performed.
The multiplication times according to claim 1, wherein the multiplication times are supplied to the means.
Road. 6. The first output signal and the second output signal
To the gate signal input means so that 0 is output to
Supply the gate signal, The sign bit inversion / non-inversion means outputs a non-inversion.
First input to the sign bit inversion / non-inversion input means
Supply the signal, When the numerical bit inversion / non-inversion means produces a non-inversion output
In both cases, 0 is supplied to the least significant digit of the Booth encoder.
To the above-mentioned numerical bit inversion / non-inversion input means so that
By supplying the input signal, 2's complement table developed by Booth's algorithm
The expressed multiplier K is set to (K = 0), and the partial product operator
The multiplication circuit according to claim 1, wherein the multiplication circuit is supplied to the stage. 7. The two's complement multiplicand D above
Sign bit input means for inputting the sign bit; Each bit of the above numerical value of the multiplicand D represented by the above two's complement
Numerical bit input means for inputting, Sign bit and numerical value of the multiplicand D represented by the above two's complement
A gate signal is provided to gate each bit of
Gate signal input means, Inversion of the sign bit of the multiplicand D expressed as 2's complement /
A symbol supplied with a third input signal for setting non-inversion
Bit inversion / non-inversion input means, Based on the gate signal input from the gate signal input means
Then, as the fifth output signal, 0 or the above sign bit
The two's complement multiplicand D supplied to the input means
Third gating means for outputting the sign bit of Based on the gate signal input from the gate signal input means
Then, as the sixth output signal, 0 or the numerical value
2's complement multiplicand supplied to the input means
Fourth gate means for outputting each bit of the numerical value of the number D
When, The first input from the sign bit inversion / non-inversion input means
Output from the third gate means based on the input signal of
The inverted or non-inverted value of the applied fifth output signal to the seventh
Sign bit inversion / non-inversion means for outputting as output signal
When, The multiplication circuit according to claim 1, wherein 8. The two's complement representation of the fifth output signal.
The sign bit of the multiplied multiplier is output and
Outputs the numerical value of the above 2's complement multiplier to the output signal of
As described above, the gate signal is supplied to the gate signal input means.
Salary, The sign bit inversion / non-inversion means outputs a non-inversion.
The sign bit inversion / non-inversion input means has the third
By supplying the input signal, The multiplicand D expressed in 2's complement is the partial product as it is.
The multiplication according to claim 7, wherein the multiplication is supplied to an arithmetic means.
circuit. 9. The fifth output signal and the sixth output signal
To the gate signal input means so that 0 is output to
Supply the gate signal, The sign bit inversion / non-inversion means has an inverted output
To the sign bit inversion / non-inversion input means.
By supplying a force signal, The multiplicand D represented by the above two's complement is (D = -1)
7. The partial product calculating means is supplied to the partial product calculating means.
The multiplication circuit described in 1. 10. The fifth output signal and the sixth output
The gate signal input means so that 0 is output to the signal
Supply the gate signal to The sign bit inversion / non-inversion means outputs a non-inversion.
The sign bit inversion / non-inversion input means has the third
By supplying the input signal, If the multiplicand D expressed in 2's complement is (D = 0),
8. The method according to claim 7, wherein the partial product calculation means is supplied.
The described multiplication circuit.