JP3433822B2 - Wireless device - Google Patents

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial applications Conventional technology (Fig. 7) Problems to be Solved by the Invention (FIG. 7) Means for Solving the Problems (FIGS. 1 to 6) Action (Figs. 1-6) Example (1) Overall configuration of the embodiment (FIG. 1) (2) Correction of frequency error (Figs. 1 to 3) (3) SCH detection (FIGS. 1 and 4 to 6) (4) Effects of the embodiment (5) Other embodiments The invention's effect

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wireless device, and can be applied to, for example, a digital cellular which encodes and transmits a voice signal.

[0003]

2. Description of the Related Art Conventionally, in a digital cellular phone, which is one of radio telephones, by encoding and transmitting a voice signal, a time-division multiplexing method is applied so that one channel is simultaneously used by a plurality of terminal devices. It is designed to be used.

That is, when the terminal device of this type is turned on, the preset 124 channels are sequentially scanned to detect the channel with the highest electric field strength. As a result, the terminal device is assigned a BCCH (broadcast control channel) assigned to the area to which the terminal device belongs.
Is detected and this BCCH is received.

The BCCH is adapted to form a time slot and transmit various kinds of information, whereby the digital cellular receives information of the base station which receives the BCCH at each terminal device and sends out the BCCH, which is adjacent to the information. The information of the base station, the calling information of the terminal device, and the like are transmitted. Therefore, the terminal device executes the processing procedure shown in FIG. 7 to synchronize the entire operation with the base station.

[0006] That is, when the terminal device receives the detected channel, it proceeds from step SP1 to step SP1.
2, the FCCH (frequency correction channel) inserted in the channel at a predetermined cycle is detected. Here, the FCCH is a synchronization signal to which a bit pattern is assigned so that the data of the value "0" continues for a predetermined number of bits when demodulated, and in the digital cellular, GMCH.
This data is SK-modulated and transmitted. Thus, in the terminal device, the FCCH timing is roughly detected by detecting the correlation value between the predetermined reference signal and the received signal, and the entire operation is roughly performed with respect to the base station based on the FCCH. It is designed to be synchronized with.

Then, in step SP3, the terminal device detects a frequency error with reference to the received data of this FCCH. Here, FCCH has a value of “0” when demodulated.
Since the data of is a synchronization signal to which a bit pattern is assigned so as to be continuous for a predetermined number of bits, when sampling the reception result obtained by quadrature detection in the terminal device at the correct timing, in the reception result,
Expressed on the IQ plane, the I-axis and the Q-axis are sequentially circulated in a 90-degree phase.

On the other hand, when the terminal device receives the FCCH with the timing shifted from the base station, this timing shift occurs (that is, there is a frequency error in the processing frequency with respect to the carrier frequency of the FCCH). ), The received data is slightly deviated from the I axis and the Q axis. As a result, the terminal device detects the deviation of the received data based on the reception result of the FCCH, thereby detecting the frequency error.

Further, when the terminal device detects the frequency error in this way, it corrects this frequency error in the following step SP4. This correction of the frequency error can be performed by controlling the operation of the reference signal generating circuit that generates the clock in the terminal device, and instead of this, the value of the received data can be corrected by applying the method of complex operation. Can also be implemented.

When the frequency error is corrected in this way,
Then, the terminal device moves to step SP5, where FC
The SCH (synchroniz
ation channel) is detected and a completely synchronized state with the base station is formed based on the SCH detection result.

Here, the SCH is a synchronizing signal of a predetermined bit pattern which is inserted in the channel like the FCCH, and the terminal device detects this SCH based on the FCCH timing detection result. It is done like this. As a result, when the entire operation is synchronized with the base station, the terminal device moves to the subsequent step SP6, completes the process of establishing this synchronization, and monitors the time slot of BCCH.

[0012]

By the way, an actual terminal device may be used in a state where the reception state is deteriorated. Especially, in mobile communication such as a vehicle-mounted terminal device, noise and fading may occur. Waveform distortion may occur in the received signal. Further, in this case, due to the Doppler shift, the carrier frequency itself of the received signal may change with time.

Therefore, in the conventional terminal device, there is a problem that it is difficult to accurately detect the frequency error and the FCCH timing due to this type of disturbance.

That is, in this type of terminal device, when it is difficult to accurately detect the frequency error by correcting the frequency error and transmitting and receiving various information at the timing synchronized with the base station, Since various information is transmitted / received to / from the base station in a timing shifted state, it becomes impossible to execute the required processing reliably and promptly.

On the other hand, if the FCCH timing cannot be accurately detected, it becomes difficult to detect the subsequent SCH. In this case, the terminal device repeats the S operation many times.
CH will be detected, and eventually it will take time before the call can be started. By the way, even when the clock frequency of the terminal device is largely displaced with respect to the base station,
Similarly, there is a problem in that the FCCH timing cannot be accurately detected. As described above, in this type of terminal device, by detecting the FCCH and correcting the clock frequency, this clock frequency is detected when the FCCH is detected. There are features that cannot be avoided.

The present invention has been made in consideration of the above points, and an object thereof is to propose a radio apparatus capable of accurately detecting the frequency error and the timing of the first synchronization signal.

[0017]

In order to solve such a problem, in the first invention, a synchronization signal FCCH having a predetermined pattern inserted in a transmission signal at a predetermined cycle is used as a reference,
In the wireless device 1 which receives the transmission signal, the transmission signal is received based on a predetermined internal clock, and the reception data IQ is received.
By detecting the correlation value between the received data IQ and a predetermined reference pattern, the synchronization signal FCCH is detected from the received data IQ, and the detected synchronization signal FCC is detected.
The reception data IQ of a predetermined bit including before and after H is stored in the memory circuit, and the reception data IQ stored in the memory circuit.
The first frequency error of the internal clock with respect to the synchronization signal FCCH is detected on the basis of the detection result, and the reception data I stored in the memory circuit is detected based on the detection result of the first frequency error.
By correcting the phase of Q, the frequency shift of the received data IQ stored in the memory circuit is corrected, and based on the received data IQ corrected of the frequency shift, the synchronization signal FC
The second frequency error remaining in the reception data IQ with the frequency deviation corrected for CH is detected, and the frequency of the internal clock matches the frequency of the synchronization signal FCCH based on the first and second frequency error detection results. The reception data IQ obtained at this time is obtained.

In the second aspect of the invention, the radio apparatus 1 for receiving a transmission signal is based on the first and second synchronization signals FCCH and SCH of a predetermined pattern which are inserted in the transmission signal at a predetermined cycle. , A reception signal IQ is obtained by receiving a transmission signal on the basis of a predetermined internal clock, and a correlation value between the reception data IQ and a predetermined reference pattern is detected, whereby the first reception data IQ is extracted from the reception data IQ.
Of the first synchronization signal FCCH and the reception data IQ of a predetermined bit including before and after the detected first synchronization signal FCCH.
Is stored in the memory circuit, the first frequency error of the internal clock with respect to the first synchronization signal FCCH is detected based on the received data IQ stored in the memory circuit, and the first frequency error is detected.
The frequency deviation of the received data IQ stored in the memory circuit is corrected by correcting the phase of the received data IQ stored in the memory circuit based on the detection result of the frequency error of the received data IQ. The timing of the first synchronization signal FCCH is re-detected by detecting the correlation value between the reference pattern and the reference pattern, and the second synchronization signal SCH is detected based on the re-detection result of the timing.

[0019]

Therefore, according to the first invention, the first frequency error of the internal clock with respect to the synchronization signal FCCH is detected based on the reception data IQ stored in the memory circuit, and the reception data IQ stored in the memory circuit is detected. By performing the phase correction with the first frequency error and detecting the frequency error again based on the phase-corrected reception data IQ, the frequency error can be detected without repeating the reception and detection of the synchronization signal FCCH. Can improve the detection accuracy of.

According to the second aspect of the invention, the first synchronization signal FC is generated based on the reception data IQ stored in the memory circuit.
The first frequency error of the internal clock with respect to CH is detected, the reception data IQ stored in the memory circuit is phase-corrected by the first frequency error, and the correlation value between the phase-corrected reception data IQ and the reference pattern is detected. By thus re-detecting the timing of the first synchronization signal FCCH and detecting the second synchronization signal SCH at the re-detected timing, it is possible to detect the second synchronization signal SCH without repeating reception of the synchronization signal FCCH. The first synchronization signal FCCH can be detected with high accuracy, and thus the second synchronization signal SCH can be detected based on the re-detection result of the timing of the first synchronization signal FCCH.
CH can be detected reliably.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) Overall Configuration of the Embodiment In FIG. 1, reference numeral 1 denotes a digital cellular terminal device as a whole, in which a transmission signal transmitted from a base station is received by an antenna 2 and a reception signal obtained as a result is received by the antenna. It outputs to the amplifier circuit 3 via a duplexer (not shown).

Here, the amplifier circuit 3 amplifies this received signal with a predetermined gain and then outputs it to the high frequency processing circuit (RF processing) 4, and the high frequency processing circuit 4 uses this predetermined local oscillation signal to receive this received signal. Frequency conversion. As a result, the terminal device 1 can switch the frequency of the local oscillation signal to selectively receive a desired channel.

Further, the high frequency processing circuit 4 demodulates the I signal synchronized with the reference phase of the received signal by performing quadrature detection of the frequency converted received signal, and at the same time, outputs a Q signal having a phase difference of 90 degrees with respect to the I signal. Is demodulated, and the I and Q signals are converted into digital values by a built-in analog digital conversion circuit.

The data processing circuit 5 receives the I data and the Q data.
It is formed by a digital signal processor that processes data, and the I data and Q data are waveform-equalized to correct distortion, thereby reducing the effects of fading and multipath. Further, the data processing circuit 5 detects the FCCH based on the I data and the Q data, and detects the frequency error based on the detection result, thereby correcting the frequency error of the received signal.

At this time, the data processing circuit 5 detects the SCH based on the FCCH detection result, and synchronizes the entire operation with the base station based on the detection result (that is, the process of establishing synchronization). In this state, the terminal device 1 further receives the BCCH and demodulates the data.

In addition to this series of processing, the data processing circuit 5
After performing convolutional decoding on the demodulated data, error correction processing,
The decoded data obtained as a result is selectively output to the voice processing circuit 6 or the central processing unit 8.

Here, the audio processing circuit 6 performs audio expansion processing on the decoded data to demodulate the audio data, and the built-in digital analog conversion circuit converts this audio data into an audio signal. Further, the voice processing circuit 6 drives the speaker 7 with this voice signal, so that the terminal device 1 can receive the voice signal of the call target transmitted from the base station.

On the other hand, the central processing unit 8 receives the predetermined information transmitted from the base station based on this decoded data, and switches the frequency of the local oscillation signal based on the reception result, thereby determining the predetermined information. The frequency is switched to the call channel so that the terminal device 1 can receive a predetermined reception channel and receive a voice signal.

On the other hand, the transmission system of the terminal device 1 converts the voice signal output from the microphone 9 into voice data by the voice processing circuit 6 and then performs voice compression processing. The data processing circuit 5 convolutionally codes the output data of the voice processing circuit 6 to generate transmission data, and replaces the output data of the voice processing circuit 6 with various control codes output from the central processing unit 8. Is convolutionally encoded to generate transmission data.

The RF processing circuit 4 quadrature-modulates this transmission data to generate an I signal and a Q signal, then synthesizes the I signal and the Q signal to generate a transmission signal, and sets this transmission signal to a predetermined frequency. Convert frequency. Further RF processing circuit 4
Outputs the frequency-converted transmission signal to the antenna 2 via the amplifier circuit 10, so that the terminal device 1 can transmit a voice signal of a caller, a call signal to a base station, or the like. ing.

At this time, the terminal device 1 has the data processing circuit 5
Among the transmission signals transmitted from the base station to the plurality of terminal devices by applying the time division multiplexing method by switching the transmission and reception timing based on the predetermined timing detection result detected in , The time slot assigned to its own station is selectively received, and the time slot assigned to its own station is used to transmit voice data and the like to the base station.

Therefore, the central processing unit 8 is adapted to secure a work area in the random access memory (RAM) 13 and execute the processing program stored in the read-only memory circuit (ROM) 11. In response, a control code is output to each circuit block to control the entire operation. For example, when a predetermined operator of the display key input unit 12 is pressed, a call signal is sent to the base station in response to this operation. When a call signal is input from the base station, the reception channel is switched.

(2) Correction of frequency error The terminal device 1 performs frame synchronization with FCCH as a reference,
Further, the frequency error is corrected, and then the entire operation is accurately synchronized with the base station with reference to the SCH, and then the time slot is received to receive desired information. That is, when the power of the terminal device 1 is turned on and the area to which the terminal device belongs is further switched, the terminal device 1 executes the processing procedure shown in FIG. 2 to execute the processing for establishing synchronization.

That is, the terminal device 1 uses the step SP11.
To step SP12, the operation of the RF processing circuit 4 is switched based on the control code output from the central processing unit 8, whereby the desired channel is received, and then the data processing circuit 5 detects the FCCH. This FC
The CH is detected by generating a predetermined reference signal in the data processing circuit 5 and detecting a correlation value between the reference signal and the received signal. The data processing circuit 5 detects the correlation value of the correlation value. The rising edge is detected to detect FCCH.

As a result, when the terminal device 1 detects the FCCH timing, it sets the time base counter built in the data processing circuit 5 on the basis of this timing, thereby synchronizing the entire operation with the frame. Then, the terminal device 1 moves to step SP13 and outputs a control code to the data processing circuit 5 to detect a frequency error.

Here, when the data processing circuit 5 detects the timing of the FCCH, the IQ data of the FCCH from the IQ data sequentially demodulated and the IQ data before and after the FCCH are stored in a built-in memory circuit. (In this case, since one burst of FCCH is 148 bits, IQ data of 200 bits or more is stored in the memory circuit as a whole.) Of IQ data stored in this memory circuit, this frequency is calculated from the IQ data of FCCH. Detect the error. That is, this type of reception result can be represented by a vector,
When sampling the reception result for each bit and obtaining the reception result, the deviation of the sampling timing with respect to the base station (that is, the deviation of the clock of the terminal device) is represented by θ _e [rad], and quadrature detection is performed. The obtained reception result at the predetermined timing is the vector S ₀ (α ₀ , β ₀ ).
The vector S ₄ (α ₄ ,
β ₄ ), and using the amplitude angle display,

[Equation 1]

[Equation 2] In this case, the phase error θ _e can be expressed by the following equation.

[Equation 3]

Therefore, from the equations (1) and (2), the following equation is obtained.

[Equation 4] The relational expression of can be obtained.

Where the following equation

[Equation 5] When the relational expression of

[Equation 6] By obtaining the relational expression of, the phase error θ _e can be detected by solving the imaginary part of the expression (4) in this case.

That is, from equation (4),

[Equation 7] The relational expression of can be obtained.

As a result, the terminal device 1 can detect the frequency error by executing the arithmetic processing of the equation (7) based on the reception result. It should be noted that the data processing circuit 5 further performs averaging processing to remove the influence of noise and the like, and phase error θ
It is designed to detect _e .

That is, within one slot, since the amplitude of the reception result does not change significantly, the data processing circuit 5

[Equation 8] The phase error θ _e is detected by executing the arithmetic processing of.

When the phase error θ _e is detected in this way, the terminal device 1 then proceeds to step SP14 and corrects the frequency error of the IQ data stored in the memory circuit based on the frequency error detection result. That is, the data processing circuit 5 converts the phase error θ _e obtained by executing the arithmetic processing of the equation (8) into the phase error θ 1 per bit, and then sequentially stores the IQ data I 1, I 2 stored in the memory circuit,
...... In, Q1, Q2, ... Qn (all represented by complex data)

[Equation 9] Then, the IQ data IQ is phase-rotated by the angle −θ1 to correct the frequency error, and the IQ data with the corrected frequency error is stored in the memory circuit.

Subsequently, the data processing circuit 5 proceeds to step SP.
Moving to 15, the frequency error is detected again based on the IQ data in which the frequency error is corrected. That is, in this type of terminal device, the frequency error of the clock source is ±
An error of about 3 [ppm] is unavoidable. In this case, in the digital cellular, since the BCCH is set in the frequency band of 900 [MHz], this frequency error is
It becomes ± 2700 [Hz] with respect to the frequency of CCH.

Therefore, as shown in FIG. 3, the frequency error is 0 [Hz], ± 1 [kHz], ± 2 [kHz], ± 3 [kHz].
As a result of simulating the relationship between the frequency error and the detection accuracy of this frequency error, it was found that when the frequency error increases, the detection accuracy decreases and the standard deviation of the detection result increases. In this simulation, the noise level Eb / No was set to 5 [db], the frequency error was detected 100 times under each condition, and the standard deviation of the detection result was detected.

The ra100 fading type is a fading model that occurs when driving at a speed of 100 km / h in a rural landscape, and the ht100 fading type is a hilly area at 100 km / h. It means a model of fading that occurs when driving on. As a result, it can be seen that the detection accuracy decreases as the frequency error increases regardless of the presence or absence of fading.

From this, it is understood that in the terminal device 1, the frequency error detection accuracy can be improved by reducing the frequency error based on the initially detected frequency error and then detecting the frequency error again.

As a result, the frequency error can be corrected by the frequency error detection result and various data can be received at the correct timing, so that the reliability of data processing can be improved and the data processing characteristic of the terminal device 1 as a whole. It is also possible to improve the characteristics of synchronization establishment in the terminal device as a whole, and to shorten the time required to establish synchronization.

At this time, the IQ data is phase-rotated to correct the frequency error, and the frequency error is detected again with reference to the corrected IQ data, whereby a separate FC is obtained.
Even if CH is not detected, the frequency error can be detected again, and the frequency error can be detected in a correspondingly short time, whereby a callable state can be formed in a short time.

Thus, when the data processing circuit 5 detects the frequency error θ2 again in this way,

[Equation 10] Then, the frequency error θ of the entire terminal device 1 with respect to the FCCH is detected.

When this frequency error .theta. Is detected, the data processing circuit 5 outputs this detection result to the central processing unit 8, and the central processing unit 8 makes a reference based on this frequency error detection result in the following step SP16. The control code is output to the signal generation circuit. As a result, the terminal device 1 corrects the frequency of the internal clock so that the frequency shift becomes 0, whereby the terminal device 1 corrects the frequency error with reference to FCCH, and then proceeds to step SP17. Complete the procedure.

(3) Detection of SCH On the other hand, the terminal device 1 newly detects the FCCH timing using the IQ data in which the frequency error is corrected in this way, and SCH is detected based on the timing detection result.
Detect CH. That is, as shown in FIG. 4, the frequency error is 0 [Hz], ± 1 [kHz], ± 2 [kHz], ±, as in the case where the frequency error detection accuracy is simulated.
When 3 [kHz] was selected and the relationship between the frequency error and the timing of FCCH detection was simulated, it was found that the accuracy of FCCH timing detection deteriorates as the frequency error increases.

In this simulation, 40
The FCCH was set to start from the 0th bit, and the FCCH was detected 100 times under each condition, and the maximum position, the minimum position and the average value of the detected positions and the variance of the detected positions were detected. In addition, in this simulation result,
The cases in which the frequency error becomes large and the dispersion becomes small are also tabulated, but in this simulation, if the FCCH detection timing is greatly delayed, it is set as an error, and the actual dispersion is set. Has been found to increase as the frequency error increases.

On the other hand, the probability of FCCH detection is shown in FIG.
It has been found that the detection probability decreases as the frequency error increases in this case as well. As a result, in the terminal device 1, the frequency error is reduced based on the frequency error detected first, and then the FCC is restarted.
It can be seen that if H is detected, the FCCH timing detection accuracy can be improved.

As a result of this timing detection result, SC
H can be detected and SCH can be detected reliably and with high accuracy,
Therefore, the reliability of data processing can be improved, and the data processing characteristics of the terminal device 1 as a whole can be improved. Further, the characteristics of synchronization establishment can be improved as a whole and the time required for synchronization establishment can be shortened. can do.

Further, at this time, the IQ data is phase-rotated to correct the frequency error, and the FCCH is detected again based on the corrected IQ data.
Even if H is not detected, the FCCH timing can be detected correctly, and the SCH can be detected in that short time.
As a result, a callable state can be formed in a short time.

Further, at this time, the FCCH can be detected again simply and surely by re-detecting the FCCH by using the IQ data stored in the memory circuit for re-detecting the frequency error. A state can be formed, and in the data processing circuit 5 which is a digital signal processor, the amount of calculation processing can be reduced, and the power consumption of the entire terminal device 1 can be reduced accordingly.

That is, when the terminal device 1 receives the BCCH as shown in FIG. 6 by assigning the same reference numerals to the processes common to those in FIG. 2, it moves from step SP11 to step SP12, and the data processing circuit 5 sends the FCCH Upon detection, the IQ data is stored in the memory circuit. Thus, the amount of IQ data to be stored in this memory circuit is stored in the memory circuit before and after one burst of FCCH, including the data of the margin for re-detecting FCCH. As a result, the data processing circuit 5 stores the IQ data in which the FCCH is detected and the data before and after the IQ data in the memory circuit for 200 bits or more in total.

Subsequently, the terminal device 1 moves to step SP13, detects a frequency error in the IQ data stored in the memory circuit, corrects the frequency error of this IQ data in the following step SP14, and corrects the frequency error in the following step SP20. A correlation value is detected between the corrected IQ data and the reference pattern used in step SP12, and thereby the FCCH timing is detected again.

Subsequently, the terminal device 1 proceeds to step SP16, corrects the frequency error of the clock, and then detects SCH at step SP21. Here, the data processing circuit 5 stores the IQ data decoded at the timing when the SCH is considered to arrive in the memory circuit based on the FCCH timing detection result detected in step SP20, and stores this IQ data and a predetermined reference pattern. The SCH is detected based on the comparison result of. As a result, when the data processing circuit 5 detects the SCH based on the comparison result,
The entire processing timing is corrected based on this SCH, and thereby the operation of the entire terminal device 1 is synchronized with the BCCH, and the terminal device 1 establishes synchronization with the base station in this way, and then proceeds to step SP22. Then, the processing procedure is completed.

(4) Effects of the Embodiments According to the above configuration, after correcting the frequency error of the IQ data stored in the memory circuit, the FCCH and the frequency error are detected again using the corrected IQ data. With this, the FCCH and the frequency error can be detected with high accuracy, whereby the synchronization can be established easily and quickly, and a state where a call can be made in a short time can be formed.

(5) Other Embodiments In the above-mentioned embodiments, the case where the FCCH and the frequency error are re-detected has been described, but the present invention is not limited to this, and only one of them is carried out as necessary. You may do it.

[0063]

Further, in the above-mentioned embodiment, the case where the present invention is applied to the digital cellular has been described, but the present invention is not limited to this, and the transmission signal is received on the basis of the synchronization signal inserted at a predetermined cycle. It can be widely applied to wireless devices.

[0065]

As described above, according to the present invention, the first frequency error of the internal clock with respect to the first synchronizing signal is detected based on the received data containing the first synchronizing signal stored in the memory circuit. Then, after phase-correcting the reception data stored in the memory circuit with the first frequency error, the frequency error is detected again based on the phase-corrected reception data, or a first error is detected from the phase-corrected reception data. By re-detecting the timing of the synchronization signal, the frequency error detection accuracy can be improved without repeating the reception and detection of the first synchronization signal, and the reception of the synchronization signal FCCH is not repeated. Even
It is possible to realize a wireless device that can detect the first synchronization signal with high accuracy and can reliably detect the second synchronization signal based on the detection result.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital cellular terminal device according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the correction of the frequency error.

FIG. 3 is a characteristic curve diagram for explaining the relationship between frequency error and detection accuracy.

FIG. 4 is a table for explaining frequency error and FCCH detection accuracy.

FIG. 5 is a characteristic curve diagram for explaining a frequency error and an FCCH detection probability.

FIG. 6 is a flow chart used for explaining FCCH detection.

FIG. 7 is a flowchart for explaining conventional synchronization establishment.

[Explanation of symbols]

1 ... Terminal device, 2 ... Antenna, 3,10 ... Amplification circuit, 4 ... RF processing circuit, 5 ... Data processing circuit, 6 ...
… Voice processing circuit, 8… Central processing unit.

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields investigated (Int.Cl. ⁷ , DB name) H04B ^7/ 24-7/26 H04Q ^7/ 00-7/38 H04L ^7/ 00-7/10

Claims (2)

(57) [Claims] 1. A radio apparatus for receiving the transmission signal with reference to a synchronization signal having a predetermined pattern inserted in the transmission signal at a predetermined cycle, wherein the transmission signal is received with reference to a predetermined internal clock. obtain the received data, by detecting a correlation value between the received data and a predetermined reference pattern, or the received data
Luo said detecting the synchronization signal, and stores the received data of a predetermined bit including front and rear of the detected said synchronizing signal to the memory circuit, on the basis of the received data stored in the memory circuit,
The first frequency error of the internal clock with respect to the synchronization signal is detected, and the received data stored in the memory circuit is phase-corrected on the basis of the detection result of the first frequency error. and correcting the frequency deviation of the received data stored, on the basis of the received data correcting the frequency deviation, and detecting a second frequency error remaining in the received data corrected the frequency deviation with respect to the synchronizing signal, the A radio apparatus, wherein the received data obtained when the frequency of the internal clock matches the frequency of the synchronization signal is obtained based on the first and second frequency error detection results. Wherein it being inserted into a transmission signal in a predetermined cycle
Re based on the first and second synchronizing signal having a predetermined pattern, in a wireless device for receiving the transmission signal to obtain a received data by receiving the transmission signal based on the predetermined internal clock, the received data By detecting the correlation value between the received data and the predetermined reference pattern .
Detects Luo said first synchronizing signal, the first in which the detected
The reception data of a predetermined bit including before and after the synchronization signal of is stored in the memory circuit, and based on the reception data stored in the memory circuit,
The first frequency error of the internal clock with respect to the first synchronization signal is detected, and the received data stored in the memory circuit is phase-corrected based on the detection result of the first frequency error. and correcting the frequency deviation of the received data stored in the memory circuit, by detecting the correlation values between the received data and the reference pattern obtained by correcting the frequency shift, re-detect the timing of said first synchronizing signal, A radio apparatus, wherein the second synchronization signal is detected based on a result of re- detection of the timing with respect to the first synchronization signal .