JP3434771B2 - Lower device facing test method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-order device opposed test method, and more particularly to a low-order device opposed test method for mutually controlling execution of test procedures among a plurality of low-order devices.

[0002]

2. Description of the Related Art In general, a test whether a device containing a microprocessor is normal is executed by executing a self-diagnosis program by the microprocessor.

As an example of such a test using a microprocessor, the "microprocessor diagnostic method" described in Japanese Patent Laid-Open No. 12747/1993 is known.

This publication describes a technique in which the function of the entire device as a microprocessor system is tested by a diagnostic program stored in the device.

Further, when a device incorporating a microprocessor constitutes a hierarchy system of an upper device and a lower device, it is necessary to test the lower device.

Such a low-level device opposition test method uses a dual-port memory to interface with a high-level device equipped with a processor and a plurality of low-level devices equipped with the processor while performing a face-to-face test between the low-level devices. Since the interface between the device and the lower device is one-to-one, the upper device test program issues instructions to each lower device test program via the dual port memory and controls each lower device test program during the test. It will be tested while.

[0007]

In the above-described conventional lower device counter test method, since the upper device and the lower device interface via the dual port memory, the lower devices cannot directly communicate with each other. Since the upper apparatus test program has to sequentially control a plurality of lower apparatus test programs and sequentially perform the counter test, there is a drawback that the lower apparatus counter test takes time.

An object of the present invention is to provide a lower device counter test method for simultaneously performing a plurality of lower device counter tests without the control of the upper device test program during the lower device counter test and shortening the test time. It is in.

[0009]

[0010]

[Means for Solving the Problems] Lower device counter test of the present invention
The test method consists of a plurality of lower-level devices each equipped with a processor, and one upper-level device equipped with a processor.
When the plurality of lower devices perform an interface test between the plurality of lower devices via the dual port memory in the upper device with the plurality of lower devices facing each other, the plurality of lower devices include the dual port memory. The address conversion unit in the higher-level device allows the test programs in the lower-level device to directly exchange information via the same address in the dual-port memory so that the same address can be accessed, and test while controlling the test procedure. Is characterized by.

It is composed of a host device equipped with a processor and a plurality of lower devices each equipped with a processor.
The upper device has a test program, a dual port memory used as an interface area, and an address conversion unit connected to the dual port memory, and each of the plurality of lower devices has a test program. The device and the plurality of lower devices are respectively connected to the plurality of lower devices via the address conversion unit and a plurality of upper device interfaces connected thereto,
The plurality of lower devices are connected to each other by a lower device interface.

When the first test program in the first lower-level device accesses the test address, the address conversion unit performs the second test of the second lower-level device on the opposite side for performing the opposite test. The address is converted into a common area which is the same area as the program, and the first test program in the first lower device and the second test program in the second lower device are converted.
The test program is characterized by executing the test while mutually notifying the test execution states of its own program through the common area.

The test program in the host device is
For the first and second test programs in the first and second lower-level devices, a lower-level device opposite test start instruction is sent to the first and second areas which are the normal interfaces of the dual port memory. It is characterized by starting the test by writing in each.

Further, it is characterized by a multiprocessor system using the low-order device opposite test method.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a lower device opposed test method of the present invention.

The present embodiment shown in FIG. 1 comprises a host device 1 having a processor mounted therein and a plurality of lower devices 2, 2a, 2n each having a processor mounted therein.

The upper device 1 has a test program 11, a dual port memory 12 used as an interface area, and an address conversion unit 13 connected to the dual port memory 12, and the lower devices 2, 2a and 2n each have their own functions. It has test programs 3, 3a and 3n. The higher-level device 1 and the lower-level devices 2, 2a, 2n are the address conversion unit 1
3 and host device interfaces 15 and 15 connected thereto
The lower devices 2, 2a and 2n are respectively connected via a and 15n. The lower device 2 and the lower device 2a are connected to each other by the lower device interface 16.

FIG. 2 is a detailed block diagram showing the operation of the low-level equipment opposite test method of the present invention.

In FIG. 2, components corresponding to those shown in FIG. 1 are designated by the same reference numerals or symbols, and their description will be omitted.

Referring to FIG. 2, the address conversion unit 13
When the test program 3 in the lower-level device 2 accesses the test address, the address is converted into the common area 23 in the same area as the test program 3a of the lower-level device 2a on the opposite side which performs the counter-test. The test program 3 in the lower-level device 2 and the test program 3a in the lower-level device 2a will perform the test while mutually notifying each other of the test execution states of their own programs via the common area 23.
The test address means a virtual address when the dual port memory 12 is regarded as a virtual memory.

FIG. 3 is a flow chart showing the operation of FIG.

FIG. 3 (a) is a flow chart of the test program in the upper device, FIG. 3 (b) is a flow chart of the test program in the lower device 2, and FIG. 3 (c) is the lower device 2.
The flowchart of the test program in a is shown.

FIG. 4 is a diagram showing the operation of the test program between the lower devices.

Next, the operation of the present embodiment will be described in more detail with reference to FIGS. 2, 3 and 4.

The test program 11 in the higher-level device 1 issues a lower-level device opposite test start instruction to the test programs 3, 3a in the lower-level devices 2, 2a and the lower-level device 2 area 21, which is the normal interface of the dual port memory 12, and The test is started by writing in each of the lower device 2a areas 22 (step 11: S11).

The test program 3 in the lower-level device 2 reads the lower-level device 2 area 21, executes the process 1, and when completed, accesses the test address to the lower-level device 2 status 4 in the common area 23 of the dual port memory 12. The completion notice 5 is written (step 21: S21).

Further, the test program 3 in the lower device 2a
a reads the lower device 2a area 22, executes processing 2, and when completed, accesses the test address and writes the completion notification 5a to the lower device 2a status 4a in the common area 23 of the dual port memory 12 (step 31:
S31).

The test program 3 in the lower device 2 reads the lower device 2a status 4a in the common area 23 of the dual port memory 12, checks whether the process 2 of the test program 3a in the lower device 2a is completed, and it is completed. If not, the reading of the status of the lower device 2a 4a is repeated until completion (steps 22 and 23: S22, S2).
3).

Further, the test program 3 in the lower device 2a
a reads the lower device 2 status 4 in the common area 23 of the dual port memory 12, checks whether the process 1 of the test program 3 in the lower device 2 is completed, and if not completed, the lower device 2 status 4 is completed. Is read repeatedly (steps 32 and 33: S32 and S3).
3).

The test program 3 in the lower-level device 2 executes the process 3 if the process 2 of the test program 3a in the lower-level device 2a is completed, accesses the test address when the process 2 is completed, and accesses the test address of the dual-port memory 12. The completion notice 5 is written in the status 4 of the lower device 2 in the shared area 23 (step 24: S24).

Further, the test program 3 in the lower device 2a
If the process 1 of the test program 3 in the lower-level device 2 is completed, the process a is executed, and when completed, the test address is accessed and the common area 2 of the dual port memory 12 is accessed.
The completion notification 5a is written in the status 4a of the lower device 2a of No. 3 (step 34: S34).

The test program 3 in the lower device 2 reads the status 4a of the lower device 2a in the common area 23 of the dual port memory 12 and checks whether the process 4 of the test program 3a in the lower device 2a is completed. If not, the reading of the lower-level device 2a status 4a is repeated until completion (steps 25 and 26: S25, S2).
6).

The test program 3 in the lower device 2a
a reads the lower device 2 status 4 in the common area 23 of the dual port memory 12, checks whether the process 3 of the test program 3 in the lower device 2 is completed, and if it is not completed, the lower device 2 status 4 is completed. Is read repeatedly (steps 35, 36: S35, S3).
6).

The test program 3 in the lower device 2 executes the process 5 if the process 4 of the test program 3a in the lower device 2a is completed, and if completed, the dual port memory 1
2 write the completion notice to the lower device 2 area 21 (S2
7) Notify the test program 11 in the host device 1.

Further, the test program 3 in the lower device 2a
If the process 3 of the test program 3 in the lower-level device 2 is completed, the process a is executed, and if completed, the completion notification is written to the lower-level device 2a area 22 of the dual port memory 12 (S37). The test program 11 is notified.

The test program 11 in the upper device 1 reads the lower device 2 area 21 and the lower device 2a area 22 of the dual port memory 12 (S13) and ends the test.

As described above, the low-level device test program controls the test and performs the low-level device facing test. More specifically, when the dual port memory 12 of the higher-level device is accessed from the lower-level device side, an address conversion unit 13 that performs address conversion into a common area 23 accessible by a plurality of lower-level devices and the common area 23 are used. It has a test program 3 in the lower device 2 and a test program 3a in the lower device 2a for controlling the test by exchanging information to perform the lower device opposite test, and receives the control of the test program 11 in the upper device. Without lower device test program 3
Since the test is controlled by exchanging information between 3 and 3a, it is possible to simultaneously perform a plurality of lower device opposing tests.

That is, the test program in the lower device tests between the lower devices in the electronic device having a plurality of lower devices while controlling the test procedure.

Although the area of the dual port memory 12 is limited to the two lower devices 2 and 2a for the sake of description, it is not restricted to this.

It is also possible to carry out a low-level counter test by using the above-mentioned low-level device counter test method in an electronic system having a multiprocessor system configuration.

[0042]

As described above, according to the low-level device opposite test method of the present invention, the high-level device test program simply activates the test for all the low-level device test programs, and the sequential control is performed during the test. Since it is not necessary and a plurality of lower-layer device facing tests can be executed simultaneously, there is an effect that the total test time can be shortened when performing a plurality of lower-device facing tests.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a lower device counter test method of the present invention.

FIG. 2 is a detailed block diagram showing the operation of the lower device counter test method of the present invention.

FIG. 3 is a flowchart showing the operation of FIG.

FIG. 4 is a diagram showing an operation of a test program between lower devices.

[Explanation of symbols]

1 Upper device 2,2a, 2n Lower device 3,3a, 3n test program 4 Lower device 2 status 4a Lower device 2a status 5, 5a Completion notification 11 Exam Program 12 dual port memory 13 Address converter 15, 15a, 15n Host device interface 16 Lower device interface 21 Lower device 2 area 22 Lower device 2a area 23 common areas

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Claims (5)

(57) [Claims] 1. A plurality of lower-level devices each including a processor and one upper-level device including a processor, wherein the plurality of lower-level devices are connected to the plurality of lower-level devices via a dual port memory in the upper-level device. When performing an interface test between devices with a plurality of lower devices facing each other,
The address translation unit in the upper device directly exchanges information between test programs in the lower device via the same address in the dual port memory so that the plurality of lower devices can access the same address in the dual port memory. , A lower device counter test method characterized by performing a test while controlling the test procedure. 2. A higher-level device having a processor and a plurality of lower-level devices each having a processor, each of which has a test program, a dual port memory used as an interface area, and a dual port memory. An address translation unit connected to the memory, each of the plurality of lower devices has a test program, the upper device and the plurality of lower devices, the address conversion unit and a plurality of upper devices connected to it. A lower device counter test method, wherein each of the plurality of lower devices is connected via a device interface, and the plurality of lower devices are mutually connected by a lower device interface. 3. The address translation unit, when an access is made to a test address from a first test program in the first lower device, a second device of a second lower device on the opposite side for performing an opposite test. Address conversion to a common area which is the same area as the test program of the first test program in the first lower device and the second test program in the second lower device are performed in the common area. 3. The low-order device opposite test method according to claim 2, wherein the test is carried out while mutually notifying the test execution status of its own program via. Wherein said test program in the host system, the first, the first second in the lower device, for the second test program, the dual port memory sub system facing the test start instruction 4. The test is started by writing in each of the first area and the second area, which are the normal interfaces of the above.
Lower device counter test method described . 5. A multiprocessor system using the low-order device opposite test method according to claim 1. Description: