JP3436893B2 - Three-valued logic operation unit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logical operation device for assigning a predetermined truth value to a signal and performing a logical operation on the signal based on the assigned truth value. In addition, the present invention relates to a ternary logic system arithmetic unit capable of performing a complex logic operation with a simple and small system configuration by enabling a ternary logic system logical operation. 2. Description of the Related Art Generally, two truth values, true and false, are assigned to a signal used in a digital circuit. That is, "1" is set in accordance with the level of a signal level such as a voltage or luminous intensity.
(True) or "0" (false). For example, a truth value is assigned such as "1" when the signal voltage is 5V and "0" when the signal voltage is 0V. Then, in a logic operation circuit such as a logic gate, a logic operation (for example, an AND operation, an OR operation, a NOT operation, etc.) is performed based on these two truth values. Hereinafter, a logical operation based on the two truth values “1” and “0” is referred to as a binary logical system, and a digital circuit in such a binary logical system is referred to as a binary logical operation circuit. Here, in the above-mentioned binary logic operation circuit, the signal level when no signal is transmitted is generally the same as the signal level for the above-mentioned truth value.
For example, the signal voltage when no signal is transmitted is 0 V
In many cases, a truth value “0” is assigned to the voltage 0V. In such a case, when the signal voltage obtained in the digital circuit is 0 V, it is determined whether the 0 V represents the corresponding truth value "0" or indicates that the signal itself is not transmitted. (Hereinafter, this determination is referred to as signal validity determination, and the state in which a signal is being transmitted is referred to as "signal is valid"). For this purpose, as shown in FIG. It is necessary to provide a compensation circuit 101 separately from the logic circuit 100. That is, in a logic circuit that inputs _m signals X _{1 to} X _m and outputs n signals Y _{1 to} Y _n , the validity of each of the input signals X _{1 to} X _m is determined and a logical operation is performed. If you do
As shown in FIG. 12, a compensation circuit 1 is provided separately from the logic circuit 100.
01, and input each of the input signals X _{1 to} X _m to the compensation circuit 101.
UX _{1 to} UX _m (for example, the input signal X
₁ is if enabled the level of UX ₁ to H level, must enter a indicating the validity of the input signals X ₁₎ by If the input signal X ₁ not effective levels UX ₁ to L level is there. Compensation circuit 101 based on the signal UX ₁ ~UX _m determines the validity of each input signal X ₁ to X _m, to compensate for signal to perform logical calculation based only on the valid input signal. The compensation circuit 101 simultaneously outputs the effectiveness with respect to the output signal Y ₁ to Y _n serving operation result in the logic circuit 100 as a signal UY ₁ ~UY _n. If, for example, a specific unit in the digital circuit breaks down, the output from that unit becomes the ground potential, that is, 0V. Therefore, in order to make a digital circuit capable of judging a unit failure, a compensating circuit is required in the same manner as described above. [0005] As described above, the conventional 2
In the value logic operation circuit, the signal is “1” or “0”.
Was assigned to only two truth values,
In order to perform a complicated logical operation, many logical gates are required, and there is a problem that the circuit configuration becomes large. Also, when judging the validity of a signal or judging a failure of a specific unit in a circuit, it is necessary to provide a compensating circuit separately from the logic circuit as described above. There was a problem that it would. Such a problem is not particularly limited to the arithmetic circuit. For example, even when a binary logic system arithmetic device is configured using a computer program, there is a problem that the system becomes large. The present invention has been made in view of such conventional problems,
A logical operation device that assigns a predetermined truth value to a signal level and performs a logical operation on a signal based on the assigned truth value enables a logical operation of a ternary logical system to simplify complicated logical operations. It is another object of the present invention to provide a ternary logic system operation device that can be realized with a small system configuration. [0006] In order to solve the above-mentioned problems in the conventional binary logic system arithmetic unit, the present invention according to claim 1 has the following features.
Assigning a predetermined truth value to the signal voltage;
Logic that performs logical operation on signal voltage based on truth value
System operation device, wherein a truth value (1, 0) of "true, false"
In addition, there is a case where it cannot be determined as either true or false.
Taste “indecision” as the third truth value (NIL)
The potential generated when the element does not transmit a signal is included.
The third truth value (NIL) is assigned to the
The true truth value (1) and the false true value in two other voltage bands.
The signal voltage of the ternary signal to which the logical value (0) is assigned
Input means for inputting, and input by the input means
Truth value (0, 1, NI) corresponding to the signal voltage of the ternary signal
L), by the third truth value (NIL)
An operation means for determining the validity of the voltage and performing a logical operation;
The result of the logical operation performed by the operation means is a ternary signal
Output means for outputting as a signal voltage of
It is configured as a sign. Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings. In the first embodiment, the ternary logic operation device is configured as a ternary logic operation circuit. FIG. 1 is a block diagram of a ternary logic operation circuit according to the present embodiment. In a conventional binary logic system operation circuit, only truth values, that is, truth values of “1” and “0” are used. In the present embodiment, in addition to these two truth values, a new truth value of “undecidable” is added. Used. This “undecidable” (hereinafter referred to as “NIL”) is a logical concept meaning that neither “1” nor “0” can be determined. As described above, the logical operation circuit according to the present embodiment handles three truth values “1”, “0”, and “NIL”. Therefore, such a digital circuit is referred to as a ternary logical operation circuit. The signals assigned to the three truth values are
Value signal. As shown in FIG.
The value logic operation circuit receives one or two or more ternary signals by an input means, performs a logic operation described later on the input ternary signal by the operation means, and outputs the operation result by an output means. It is output as a ternary signal. Here, the relationship between the three truth values and the signal level (signal voltage in the present embodiment) will be described. FIG. 2 is a diagram showing the relationship between the signal voltage and the truth value in the present embodiment. As shown in FIG.
2.0 to +2.0 V is divided into three voltage bands, and the above-mentioned “1”, “0” and “NIL” are assigned to each voltage band. The widths of these voltage bands are equal (1.0 V width), and “1”, “NIL”, and “0” are assigned in descending order of voltage, and these voltage bands are symmetric with respect to the ground potential (0 V). That is, as shown in FIG. 2, "1" is applied to the voltage band of +1.0 to +2.0 V, "NIL" is applied to the voltage band of -0.5 to +0.5 V, and -2.0 to +2.0 V.
"0" is assigned to the voltage band of -1.0V. An interval of 0.5 V is provided between these voltage bands, and the truth value is not determined in this range. In the following, the midpoint voltage of each voltage band (+1.5 V, 0.0 V, -1.
5V) will be described as a representative value for each truth value. By the way, it is very likely that the output of the failed unit becomes the ground potential (0 V) as described above. In the present embodiment, in order to prevent a malfunction or the like due to the ground potential from such a failed unit, “0” is not assigned to a voltage band near 0 V, and the determination of “1” and “0” is performed. "N" means that
"IL" is assigned to -0.5 to +0.5 V (near ground potential). In this embodiment, a ternary logic gate as a ternary logic operation circuit will be described. The truth table of the logical operation described below is defined in consideration of empirical rules and the like. Table 1 shows the ternary logic system AN according to the present embodiment.
It is a truth table of D operation. This AND operation is an operation of two inputs and one output. Table 1 shows the first input in the left column and the second input in the upper column.
Represents the calculation result for the combination of the inputs. [Table 1] FIG. 3A shows a ternary AN in this embodiment.
FIG. 2 is a block diagram of a D gate 1. The AND gate 1 has 2
One of the inputs a ternary signal X _A1, X _A2, is output ternary signal Y _A. The AND gate 1 receives the input signals X _A1 , X _A2
And it outputs a lower voltage of the signal voltage as the output signal Y _A. For example, when the input signal X _A1 is “1” (signal voltage +1.5 V) and the input signal X _A2 is “NIL” (signal voltage 0.0 V), the low signal voltage of 0.0 V, that is, “NIL” is set. and outputs as the output signal Y _A. Note if the signal voltage of the input signal X _A1, X _A2 are the same, and outputs the voltage as the output signal Y _A. This enables an operation based on the truth table of the AND operation in Table 1. That is, AN
There is at least one of the output if it is "0" signal Y _A is "0" next to the D 3 value signals X _A1 to be input to the gate 1, X _A2, also both of the input signals X _A1, X _A2 is "1" field output signal Y _A is "1", the input signal X _A1, X _A2 is "NIL"
And the output signal Y _A if the combination of "1" or "NIL", "NIL" is "NIL". Next, Table 2 is a truth table of the OR operation of the ternary logic system in this embodiment. This OR operation also has two inputs and one
Table 2 shows the calculation results for the first input in the left column and the second input in the upper column. [Table 2] FIG. 3B shows a ternary OR according to the present embodiment.
It is a block diagram of a gate 2. When two ternary signals X _B1 and X _B2 are input to the OR gate 2, a ternary signal Y _B is output. The OR gate 2 outputs the higher one of the signal voltages of the input signals X _B1 and X _B2 as the output signal Y _B , contrary to the AND gate 1. For example, if the input signal X _B1 is “1” (signal voltage +1.5 V) and the input signal X _B2 is “NIL” (signal voltage 0.0 V), the signal voltage is high +1.5 V, that is, “1”. The output signal Y _B
Output as If the signal voltages of the input signals X _B1 and X _B2 are the same, the voltage is output as the output signal Y _B. This enables an operation based on the truth table of the OR operation shown in Table 2. That is, if at least one of the ternary signals X _B1 and X _B2 input to the OR gate 2 is “1”, the output signal Y _B becomes “1”, and the input signals X _B1 and X _B2
If both "0" output signal Y _B is "0" next to,
When the input signals X _B1 and X _B2 are “NIL” and “0” or “NI”
L ”and“ NIL ”, the output signal Y _B is“ N
IL ”. Here, in the present embodiment, the NOT operation of the conventional binary logic system is extended to the NOT1 operation described below.
NOT2 operation and NOT3 operation are defined. These are one-input, one-output operations. Table 3 is a truth table of the NOT1 operation of the ternary logic system in the present embodiment, Table 4 is a truth table of the NOT2 operation, and Table 5 is a truth table of the NOT3 operation. . [Table 3] [Table 4] [Table 5] FIG. 3C shows a ternary NO in this embodiment.
FIG. 3D is a block diagram of a T1 gate 3, FIG. 4D is a block diagram of a ternary NOT3 gate 4, and FIG. These NOT1 gates 3, NOT2
The gate 4 and the NOT3 gate 5 output ternary signals Y _C , Y _D , and Y _E when receiving ternary signals X _C , X _D , and X _E , respectively. NOT1 gate 3 outputs a voltage obtained by inverting the signal voltage of the input signal X _C with respect to ground voltage (0V) as the output signal Y _C. For example, when the input signal X _C is “1” (signal voltage +1.5 V), the signal voltage is inverted, and −1.5 V, that is, “0” is output as the output signal Y _C. This enables an operation based on the truth table of the NOT1 operation shown in Table 3. That is, if the ternary signal X _C input to the NOT1 gate 3 is “1”, the output signal Y _C
Is "0", the output signal Y _C if the input signal X _C is "0" becomes "1", the input signal X _C is the output signal Y _C if "NIL" is "NIL". The NOT2 gate 4 is a subunit 4 for inverting the signal voltage with respect to the midpoint voltage (-1.5 V) of "0".
a and a limiter 4b having the characteristics shown in FIG. The signal X _D input to the NOT2 gate 4 is inverted with respect to -1.5V by the subunit 4a, is further output as a signal the output signal Y _D having passed through the limiter 4b. For example, when the input signal _XD is “1” (signal voltage 1.5 V), first, the subunit 4 a
As a result, the signal voltage is inverted to -4.5V. Then, (see Fig. 4) 0.0 V as the output signal Y _D and passing the limiter 4b, or "NIL" is output. Table 4
The operation based on the truth table of the NOT2 operation shown in FIG. That is, the ternary signal X input to the NOT2 gate 4
_{If D} is “1”, the output signal Y _D becomes “NIL”, if the input signal X _D is “0”, the output signal Y _D becomes “0”, and if the input signal X _D is “NIL”, The output signal Y _D becomes “1”. The NOT3 gate 5 is a subunit 5 for inverting the signal voltage with respect to the midpoint voltage (+1.5 V) of "1".
a and a limiter 5b having the characteristics shown in FIG. The NOT3 gate 5 signal X _E input to invert against + 1.5V by the subunit 5a, further signal passed through the limiter 5b is output as an output signal Y _E. For example, if the input signal X _E is “NIL”
If the signal voltage is (signal voltage 0.0 V), the signal voltage is first inverted to +3.0 V by the subunit 5a. The -1.5V and is passed through a limiter 5b as an output signal Y _E,
That is, "0" is output. Thereby, N shown in Table 5 is obtained.
The operation based on the truth table of the OT3 operation is enabled. In other words, a ternary signal X _E to be input to the NOT3 gate 5 is "1"
, The output signal Y _E becomes “1”, if the input signal X _E is “0”, the output signal Y _E becomes “NIL”, and if the input signal X _E is “NIL”, the output signal Y _E becomes It becomes "0". Next, a ternary logic operation relay according to a second embodiment of the present invention will be described in detail with reference to the drawings.
The ternary logic operation relay in the present embodiment is configured using the above-described ternary logic gate. In the following description, when the AND gate, the OR gate, the NOT1, the NOT2 gate, and the NOT3 gate are referred to as the above-described three-valued AND gate, three-valued OR gate, and three-valued NOT
It means one gate, three-level NOT2 gate, and three-level NOT3 gate, respectively, and parts that are not particularly described are the same as those in the first embodiment. FIG. 5 is a diagram showing a circuit configuration of the first logical operation relay 6. The first logical operation relay 6 sets the output signal Y to “NIL” when the input signal A is “1”, and sets the input signal X to “NIL” when the input signal A is other than “1”. It is output as it is as output signal Y (Table 6). That is, by inputting "1" as the input signal A, a relay circuit that cuts off between the X and Y signals is realized. [Table 6] [Table 7] As shown in FIG. 5, the first logical operation relay 6 includes a NOT3 gate 61, an AND gate 62, and a NOT1 gate.
Gate 63, NOT2 gate 64, AND gate 65,
And an OR gate 66. Hereinafter, the input and output of signals in the first logical operation relay 6 will be described with reference to Table 7. First, a case where the input signal A is “1” will be described. When the input signal A is “1”, N
The signal L1 that has passed through the OT3 gate 61 becomes "1" (see the truth table of NOT3 in Table 5). In addition, the signal L2 that has passed through the AND gate 62 becomes “1” (see AN in Table 1).
See the truth table of D). The signal L3 further passing through the NOT1 gate 63 becomes "0", and the signal L4 passing through the NOT2 gate 64 becomes "NIL". In this case, if the input signal X is "1", the signal L5 passed through the AND gate 65 becomes "0", and the output signal Y
Becomes “NIL”. If the input signal X is "0", the signal L5 becomes "0" and the output signal Y becomes "NIL". If the input signal X is “NIL”, the signal L5
Becomes "0" and the output signal Y becomes "NIL". on the other hand,
Similarly, when the input signal A is “0”, if the input signal X is “1”, the output signal Y is “1” and the input signal X
Is "0", the output signal Y is "0", and if the input signal X is "NIL", the output signal Y is "NIL". When the input signal A is “NIL”, if the input signal X is “1”, the output signal Y is “1” and the input signal X
Is "0", the output signal Y is "0", and if the input signal X is "NIL", the output signal Y is "NIL". In this manner, the first logical operation relay realizes the logical operation shown in Table 6, and therefore, when "1" is input as the input signal A, a relay circuit that disconnects the XY signal is realized. Is done. Here, the configuration of another logical operation relay in this embodiment will be described. 6 is a diagram illustrating a circuit configuration of the second logical operation relay 7, FIG. 7 is a diagram illustrating a circuit configuration of the third logical operation relay 8, and FIG. 8 is a diagram illustrating a circuit configuration of the fourth logical operation relay 9. , FIG. 9 shows the fifth logical operation relay 1
FIG. 10 is a diagram showing a circuit configuration of the sixth logical operation relay 11. The second logical operation relay 7 outputs the input signal X as it is as the output signal Y when the input signal A is “1”, and outputs the output signal Y when the input signal A is other than “1”. "NIL" (Table 8). That is, by inputting "1" as the input signal A, a relay circuit for connecting the XY signals is realized. Table 9 shows the relationship between the input signals A and X and the output signal Y in the second logical operation relay 7. The input / output of this signal is the same as that of the above-described first logical operation relay, and therefore the description is omitted. [Table 8] [Table 9] The third logical operation relay 8 sets the output signal Y to "NIL" when the input signal A is "0", and outputs the input signal X when the input signal A is not "0".
Is directly output as the output signal Y (see Table 1).
0). That is, by inputting “0” as the input signal A, a relay circuit that cuts off between the X and Y signals is realized. Table 11 shows the relationship between the input signals A and X and the output signal Y in the third logical operation relay 8. Description of the input and output of this signal is omitted. [Table 10] [Table 11] The fourth logical operation relay 9 outputs the input signal X as it is as the output signal Y when the input signal A is "0", and outputs the output signal Y when the input signal A is other than "0". The signal Y is set to “NIL” (Table 12).
That is, by inputting "0" as the input signal A, X-
A relay circuit for connecting the Y signals is realized. Table 13 shows the relationship between the input signals A and X and the output signal Y in the fourth logical operation relay 9. Description of the input and output of this signal is omitted. [Table 12] [Table 13] The fifth logical operation relay 10 receives the input signal A
Is "NIL", the output signal Y is set to "NIL", and when the input signal A is other than "NIL", the input signal X is output as it is as the output signal Y (Table 14). That is, a relay circuit that cuts off between the X and Y signals by inputting “NIL” as the input signal A is realized. Table 15 shows the relationship between the input signals A and X and the output signal Y in the fifth logical operation relay 10. Description of the input and output of this signal is omitted. [Table 14] [Table 15] The sixth logical operation relay 11 receives the input signal A
Is “NIL”, the input signal X is output as it is as the output signal Y, and when the input signal A is other than “NIL”, the output signal Y is set to “NIL” (Table 16). . That is, by inputting "NIL" as the input signal A, a relay circuit for connecting the X and Y signals is realized. Table 17 shows the relationship between the input signals A and X and the output signal Y in the sixth logical operation relay 11. Description of the input and output of this signal is omitted. [Table 16] [Table 17] Although one embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and may be implemented in various forms within the scope of the technical idea. Hereinafter, these different embodiments will be described. In the above embodiment, the case where the ternary logical operation device is configured as a logical operation circuit has been described. However, the present invention is not limited to this, and the present invention relates to a case where the logical operation device is configured using a computer program. Is also applicable. For example, the ternary signal is input to a computer, the ternary signal is digitized, and a ternary logic operation is performed on the digitized ternary signal by a computer program. It is also possible to configure a logical operation device that converts the signal into an analog signal and outputs it as a ternary signal. Further, in the present embodiment, a signal voltage has been described as an example of a signal level, but the present invention is not limited to this and can be applied to any signal. For example, it can be applied to optical communication. The relationship between the signal voltage and the truth value is not limited to that shown in FIG. For example, as shown in FIG. 11, a signal voltage may be associated with a truth value. More specific voltage values are not necessarily those shown in the figure, and any voltage value may be used. The arrangement and combination of the respective logic gates in the ternary logic relays 6 to 11 are not limited to those shown in the drawings, and it goes without saying that any arrangement and combination can be considered. As described above, according to the present invention, in a logical operation device for assigning a predetermined truth value to a signal and performing a logical operation on the signal based on the assigned truth value, In addition, a third truth value different from the truth is assigned 3
A value signal is input, a predetermined logical operation is performed based on the truth value of the input ternary signal, and the result of the logical operation is output as the ternary signal. Since the logical operation of the extended ternary logical system can be performed, there is an effect that even if a complicated logical operation is performed, it can be realized with a simple and small system configuration. In addition, the third truth value is determined to be undecidable meaning that it cannot be determined to be either true or false, and the validity of the ternary signal can be determined based on the undecidable truth value. The introduction of the impossible truth value has the effect that the validity of the input signal can be easily determined with a small system configuration. Further, since the undeterminable truth value is assigned to the substantially minimum signal level of the ternary signal, the validity of the input signal can be reduced even when a specific unit in the digital circuit has failed. There is an effect that the judgment can be made easily.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a ternary logic operation circuit according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating a relationship between a signal voltage and a truth value according to the first embodiment of the present invention. FIGS. 3A and 3B are block diagrams of a logic gate according to the first embodiment of the present invention. FIG. 3A is a ternary AND gate, FIG. 3B is a ternary OR gate, FIG. d)
3 is a block diagram of a ternary NOT2 gate, and FIG. 3E is a block diagram of a ternary NOT3 gate. FIG. 4 is a diagram showing characteristics of the limiters according to FIGS. 3D and 3E. FIG. 5 is a diagram illustrating a circuit configuration of a first logical operation relay according to a second embodiment of the present invention. FIG. 6 is a diagram illustrating a circuit configuration of a second logical operation relay according to the second embodiment of the present invention. FIG. 7 is a diagram illustrating a circuit configuration of a third logical operation relay according to the second embodiment of the present invention. FIG. 8 is a diagram illustrating a circuit configuration of a fourth logical operation relay according to the second embodiment of the present invention. FIG. 9 is a diagram illustrating a circuit configuration of a fifth logical operation relay according to the second embodiment of the present invention. FIG. 10 is a diagram illustrating a circuit configuration of a sixth logical operation relay according to the second embodiment of the present invention. FIG. 11 is a diagram illustrating a relationship between a signal voltage and a truth value according to another embodiment of the present invention. FIG. 12 is a block diagram of a logic circuit with a compensation circuit in a conventional binary logic operation circuit. [Description of Signs] 1 Three-valued AND gate 2 Three-valued OR gate 3 Three-valued NOT1 gate 4 Three-valued NOT2 gate 4a Subunit 4b Limiter 5 Three-valued NOT3 gate 5a Subunit 5b Limiter 6 to 11 Three-valued logic relay X _A1 to X _E input signal Y _A to Y _E output signal

Claims (1)

(57) [Claim 1] A logical operation device that assigns a predetermined truth value to a signal voltage and performs a logical operation on the signal voltage based on the assigned truth value, In addition to the truth value (1, 0) of “, false”, “undecidable”, which means the case where neither “true” nor “false” can be determined, is set as a third truth value (NIL), and the logic element outputs a signal. Sending
The voltage range including the potential generated when the third
Assigns a truth value (NIL) and the other two voltage bands
To the true truth value (1) and the false truth value (0), respectively.
Input means for inputting a signal voltage of a ternary signal assigned truth values corresponding to the signal voltage of the ternary signal inputted by said input means (0, 1, NIL) for the third
The validity of the signal voltage by the truth value (NIL) of
A ternary logic system arithmetic device , comprising: arithmetic means for performing a logical operation; and output means for outputting a result of the logical operation performed by the arithmetic means as a signal voltage of a ternary signal.