JP3439652B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using an SOI substrate, and more particularly to a semiconductor device having a silicide portion and a method for manufacturing a semiconductor device using the SOI substrate, and more particularly to a semiconductor device in which silicidation is selectively formed. The present invention relates to a manufacturing method of.

[0002]

2. Description of the Related Art In recent years, with the increase in speed and power consumption of semiconductor devices, a so-called salicide process of forming a reaction layer (silicide layer) of a refractory metal and silicon in an active region and a gate in a self-aligned manner The demand is increasing. However, the semiconductor device is called a bulk (Bul)
k) When a substrate is used, when the salicide process is applied to the process including element isolation by locos, the silicide reaction between silicon and refractory metal proceeds, and the vicinity of the boundary between the field oxide film region and the active region However, for example, there is a problem in that a junction leak occurs in a shallow region of the diffusion layer. This is because it is difficult to completely separate the single transistors in the bulk substrate. On the other hand, a method for solving the problem of junction leak due to a bulk substrate is proposed in, for example, Japanese Patent Application Laid-Open No. 8-51086, which will be described with reference to FIG. A field oxide film 2 is formed on a silicon substrate 1, a diffusion layer 3 is formed therebetween by impurity diffusion, a carbon film (silicide prevention film) 4 for silicidation prevention is further deposited, and a resist pattern 5 is field-oxidized on the carbon film 4. It is selectively formed near the boundary between the film 2 and the diffusion layer 3 (see FIG. 5A).

Next, this resist pattern is used for selective etching to leave the silicide prevention film 4 near the boundary (see FIG. 5B). After that, resist pattern 5
Then, a refractory metal is deposited and heat treated to cause a silicide reaction to form a silicide layer 6 on the diffusion layer 3 to remove the unreacted refractory metal (FIG. 5C). reference). Here, the silicide prevention film 4 located near the boundary between the field oxide film 2 and the diffusion layer 3 suppresses the diffusion of the refractory metal and prevents the silicidation reaction. It becomes difficult to form a silicide layer in (3), which in turn reduces junction leakage.

[0004]

The situation of the semiconductor device using the SOI substrate is different from that using the bulk substrate. Since the SOI substrate is composed of a lower semiconductor layer, a buried oxide film, and an upper semiconductor layer, it has a buried oxide film, which is greatly different from the bulk substrate. Regarding a semiconductor device using an SOI substrate, there is no well structure like a semiconductor device using a bulk substrate. For example, a single transistor is completely insulating from other transistors (element isolation insulating film and buried oxide film).
It is considered that the elements are separated by. Therefore, it seems to be free from the problems of the bulk substrate. That is, when the silicide process is applied to an SOI substrate including a lower semiconductor layer, a buried oxide film, and an upper semiconductor layer, this substrate has a buried oxide film in addition to an element isolation oxide film, so that the insulating film is completely formed. Since the elements are separated and the transistors are located, it is considered that the junction leak does not pose a problem as a factor of the leak between the transistors.

By the way, when a silicide process is applied in manufacturing a semiconductor device using an SOI substrate, the following occurs. As a semiconductor device, transistors with different characteristics may be manufactured over the same substrate. For example, high-speed and low-speed characteristics may be produced. A case of manufacturing such a semiconductor device will be described below.

A pad oxide film and a SiN film are formed on the upper semiconductor layer of the SOI substrate by thermal oxidation, a mask is formed by a photolithography technique, a thermal oxidation process is performed, and the oxide film formed by oxidation is removed. Forming a thick region and a thin region of the upper semiconductor layer. After that, the SiN film and the thermal oxide film are removed, a pad oxide film and a SiN film are further formed by thermal oxidation, and after patterning, the pad oxide film formed between the thick region and the thin region by the Locos method is removed. An element isolation region of the upper semiconductor layer is formed in the field oxide film portion, and the SiN film is removed. After that, impurity ions are implanted for controlling the threshold value through the pad oxide film, and an ion implantation layer made of, for example, P-type impurities to be a channel region is formed in a region between the field oxide films of the upper semiconductor layer to be an active layer. Next, after removing the pad oxide film, a gate oxide film is formed, and a polysilicon film is further deposited and then patterned to form a gate region (gate electrode). Next, a silicon oxide film is deposited and sidewalls are formed on the sides of the gate region by anisotropic etching. After that, N-type impurities are implanted using the sidewall as a mask to form N-type impurity layers and N-type gate electrodes which are source and drain regions. next,
As appropriate, deposition of refractory metal such as Ti and heat treatment are performed,
A silicide layer is formed on the active layer and the gate electrode.

It was difficult to obtain desired characteristics with the transistor thus manufactured. For example, inconvenience has occurred in the withstand voltage performance of the transistor. Some transistors have poor breakdown voltage characteristics, for example, the breakdown voltage characteristics of the buried oxide film.

Therefore, the present invention provides a semiconductor device manufactured by using an SOI substrate, in which the deterioration of the withstand voltage characteristic is prevented, in particular, the deterioration of the withstand voltage characteristic of the buried oxide film of the substrate, and a manufacturing method thereof. The purpose is to do.

[0009]

The semiconductor device of the present invention comprises:
On an SOI substrate having an upper semiconductor layer on a buried oxide film, a first active region separated by a device isolation region by locos oxidation of the upper semiconductor layer, and the first active region
Sandwiching the channel region and the channel region formed in
Facing the source and drain regions and the channel region
A gate region formed of a polycrystalline silicon layer,
Source region, a surface of the drain region have a a compound of a refractory metal and silicon silicide, layer of the first active region
The thickness approaches the element isolation region due to the locos oxidation.
A semiconductor device which is thinner than the central region of the active region as in on the source region, the drain region and the isolation region, wherein said isolation region Seo
A silicide prevention film on the vicinity of the boundary between the source region and the drain region, and the source under the silicide prevention film.
A silicide is formed on the surface of the drain region and the drain region.
It is characterized by not being. The semiconductor device of the present invention is
An upper part consisting of a thick region and a thin region on the embedded oxide film.
On the SOI substrate having a semiconductor layer, the upper semiconductor layer
Is separated by the element isolation region by locos oxidation,
The first active region consisting of a thick region and the first active region consisting of a thin region
2 active regions and the first and second active regions formed
A channel region and a source region sandwiching the channel region,
The drain region and the polycrystalline region facing the channel region are
The gate region formed of the recon layer, the source region, and the drain region
A compound of refractory metal and silicon on the surface of the in-region
Each of the first and second active regions having a silicide
The film thickness of these is in the element isolation region by the Locos oxidation.
The semiconductor becomes thinner as it gets closer to the central region of the active region.
A device, wherein the source region in the first active region is
Region, on the drain region and the element isolation region,
Of the element isolation region and the source and drain regions
The vicinity of the boundary and the source region in the second active region
Range, has a silicide prevention film covering the drain region, wherein
Of the source region and drain region under the silicide prevention film
The feature is that no silicide is formed on the surface.
To do .

The semiconductor device of the present invention may preferably have a silicide prevention film between the gate region and the active region on a sidewall located on the side of the gate region.

The semiconductor device of the present invention is preferably the above
In the thick region in the active region away from the isolation region having a silicided portion facing the opening so as to face the silicide preventing film is selectively formed so as to have a predetermined opening, the Active near the element isolation region
The thin region of the conductive region may be a portion that does not react with the refractory metal (not silicidized) facing the silicide prevention film formed so as to cover the region. Also,
Its thickness in different active regions separated by the device isolation region
Different in thickness, the thick upper semiconductor layer and the thin upper semiconductor layer
A layer in the upper semiconductor layer of the thin film.
The silicide region is formed on the conductive region so as to cover the region.
Unreacted with the refractory metal facing the barrier film (silicided
It is preferable that there is a portion).

According to the method of manufacturing a semiconductor device of the present invention, the first active region is formed by performing locos oxidation for forming an element isolation region on the upper semiconductor layer of the SOI substrate having the upper semiconductor layer on the buried oxide film. Together with forming
The film thickness of the first active region approaches that of the element isolation region.
A step of reducing as compared with the central region of the active region as the
A channel region and the channel region in the first active region,
The source region and the drain region are formed to be sandwiched, and the channel is formed.
Gate region consisting of polycrystalline silicon layer facing the region
And a step of forming a sidewall on a side portion of the gate region, and above the source region, the drain region and the element isolation region, the element isolation region and the source region.
Region, a step of selectively forming a silicide prevention film on the vicinity of the boundary with the drain region, and after the refractory metal is deposited, heat treatment is performed to form the silicide prevention film.
The method further comprises the step of silicidizing the surfaces of the source region and the drain region which are not formed . Semiconductor of the present invention
The method of manufacturing the body device is such that a thick region is formed on the buried oxide film.
Substrate having an upper semiconductor layer composed of
For forming a device isolation region in the upper semiconductor layer of
By performing oxidation, the first active layer composed of the thick region is formed.
A second active region consisting of the active region and the thin region
And the film thickness of each of the first and second active regions
The closer to the element isolation region, the central region of the active region
And a step of thinning the first active region and the second active region
The channel region and the source region sandwiching the channel region.
Region, forming a drain region and facing the channel region.
And a gate region formed of a polycrystalline silicon layer,
Forming a side wall on the side of region, the first
In front of the source region and the drain region in one active region
Above the element isolation region, the element isolation region and the front
In the vicinity of the boundary between the source region and the drain region,
2 cover the source and drain regions in the active region
So as to selectively form the silicide prevention film,
After the refractory metal is deposited, heat treatment is performed to
In the first active region where the anti-reflection film is not formed
Silicide the surfaces of the source region and the drain region
It is characterized by having a step of

The semiconductor device manufacturing method of the present invention is
The step of selectively forming the recide prevention film is performed for the element
The thin area of the active area close to the remote area covers the area
Like forming an anti-silicide film
Or, it may be different from the element isolation region.
The thickness of the upper semiconductor varies depending on the active region
A layer and a thin upper semiconductor layer.
In the step of selectively forming the silicide prevention film.
And prevent silicide from covering the upper semiconductor layer of the thin film
Preferably, it comprises forming a film.

In the method of manufacturing a semiconductor device of the present invention, preferably, the step of selectively forming the silicide prevention film includes forming a silicide prevention film on the sidewall.

In the method for manufacturing a semiconductor device of the present invention, more preferably, the silicidation step may include silicidation of the gate region.

The operation of the present invention will be described below. The semiconductor device of the present invention has a silicide prevention film at least on the vicinity of a boundary between the element isolation region and the active region, and in the active region, the boundary between the silicide and the buried oxide film is formed. Since the buried oxide film of the SOI substrate has a region unreacted with the refractory metal under the vicinity thereof, defects such as defects occur near the boundary under the vicinity of the boundary due to the manufacturing process thereof, etc., and the withstand voltage characteristics are affected. Even if it causes such a problem, the unreacted region can prevent the breakdown voltage characteristic from further deteriorating.

Since the semiconductor device of the present invention has the silicide prevention film between the gate region and the active region on the sidewall located on the side of the gate region, the source of the semiconductor device The bridge short between the drain and the gate can be reduced.

In the semiconductor device of the present invention, the active region has a thick film region and a thin film region, and the thick region is opposed to the silicide prevention film selectively formed to have a predetermined opening. Having a silicidized portion facing the opening, and the thin region is a portion not reacting with the refractory metal facing the silicide prevention film formed so as to cover the thin region (not silicidized). Therefore, it is possible to prevent the breakdown voltage characteristic of the buried oxide film of the SOI substrate from being deteriorated. Specifically, even if the buried oxide film of the SOI substrate has a defect or the like near the bottom of the thin region due to its manufacturing process or the like and affects the withstand voltage characteristics, the unreacted region causes It is possible to prevent further deterioration of the withstand voltage characteristics.

In the method of manufacturing a semiconductor device of the present invention, a silicide prevention film is selectively formed on the active layer and the element isolation region, and near the boundary between the element isolation region and the active region. Since the step of forming and the step of heat-treating after depositing the refractory metal to silicify the portion of the active region facing between the silicide prevention films are performed, the silicide prevention film is further formed. Since the step of selectively forming may include forming a silicide prevention film on the active layer so as to cover a region facing the thin region, the active region may include: Between the silicide and the buried oxide film, a region unreacted with the refractory metal may be provided under the boundary and further under the thin region.

Therefore, it contributes to the provision of a semiconductor device having an improved withstand voltage characteristic, particularly a semiconductor device capable of preventing the withstand voltage characteristic of a buried oxide film from being deteriorated. And eventually SO
Even if the buried oxide film of the I substrate has a defect such as a defect under the boundary region or under the thin region due to the manufacturing process thereof, etc. Since the reaction region makes it possible to prevent further deterioration of the withstand voltage characteristic, only the SOI substrate having no defect can be used as the SOI substrate.
It may be possible to relax the requirements for substrate quality.

In the method of manufacturing a semiconductor device according to the present invention, the step of selectively forming the silicide prevention film includes forming a silicide prevention film on the sidewalls, so that a bridge between the gate and the drain or the source is formed. A short circuit can be prevented.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION As described above, the characteristics of the semiconductor device manufactured using the SOI substrate and applied with the silicide process have problems as described above. explain. Regarding the semiconductor device manufactured in this manner, as a schematic configuration thereof,
The cross section is shown in FIG. In this example, as the SOI substrate, the one prepared by implanting oxygen into the silicon substrate to form the buried oxide film 20 between the upper semiconductor layer 10 and the lower semiconductor layer 30 was used. In FIG. 6, reference numeral 10 denotes an upper semiconductor layer, which is formed as a channel region 10-1, a source / drain region 10-2, and a silicide layer 10-3. Reference numeral 60 is an element isolation region formed by a field oxide film, 70 is a gate oxide film, 8
0 is side wall, 80-1 is bridge short, 9
Reference numeral 0 is a gate region, and 90-1 is a silicide layer. In this figure, a transistor formed in a thick region where the upper semiconductor layer 10 is formed thick is shown on the left side, and a transistor formed in a thin region is shown on the right side.

In this figure, paying attention to a transistor formed in a thick region, the silicide layer 10-3 reaches the buried oxide film 20 in the vicinity of the element isolation region 60, but the side of the channel region 10-1 away from the buried oxide film 20. Does not reach the buried oxide film 2. Here, the source / drain region 10-2 becomes thinner as it approaches the element isolation region 60. Focusing on the transistor formed in the thin region, the silicide layer 10-3 reaches the buried oxide film 20 in all regions. The silicide layer 10-3 becomes thinner as it gets closer to the element isolation region 60. The degree of thinning is the same in both cases.

This is considered as follows. When forming a field oxide film, which is the element isolation region 60, on the upper semiconductor layer 10 of the SOI substrate, oxygen required for the oxidation is SiN patterned as a mask of the upper semiconductor layer 10.
Supplied through the membrane opening. Here, the amount of locos oxidation for forming the element isolation region is over-oxidized beyond the Si equivalent amount of the upper semiconductor layer 10 in order to achieve element isolation.
For example, when the upper semiconductor layer 10 has a thickness of 50 nm, the amount of oxidation just required for oxidation is 110 nm in terms of the SiO ₂ film thickness, but in the case of actual processing, 15 to 20% overoxidation is performed. Due to this over-oxidation, Si at the interface of the upper semiconductor layer 10 at the edge of the element isolation region 60 and the lower semiconductor layer 30 below the element isolation region 60 are sources of Si that is oxidized by the supply of oxygen during the over-oxidation. Si
Is used. Therefore, the unoxidized active region of the upper semiconductor layer 10 becomes thinner as it approaches the element isolation region 60. As a result, the unoxidized active region of the upper semiconductor layer 10 becomes thinner as it approaches the element isolation region 60 than in the central region.

When the silicide process is applied to the SOI substrate in such a state, the upper semiconductor layer (active region) 10
The silicide layer reaches the buried oxide film 20 from the point where it becomes thin to some extent. As a result, the silicide layer 10-3 reaches the buried oxide film 20 in the vicinity of the element isolation region 60 in the thick region and almost entirely in the thin region.

This transistor has a buried oxide film 20.
Of the silicide layer 10-3 and the lower semiconductor layer 30
Is insulated. However, there is a problem that the transistors have a mutual influence on the operation, and thus the transistor has a problem in the withstand voltage characteristic with respect to the lower semiconductor layer 30. From this, it was considered that the problem was the buried oxide film 20. The following can be considered as the factors.

In the SOI substrate, the buried oxide film 20 may have residual silicon layers, defects and the like scattered. In this case, if the residual silicon layer and the defects are scattered near the upper semiconductor layer 10 side and are not sufficiently separated from the upper semiconductor layer 10 by the buried oxide film 20, the silicide layer 10 is formed as described above. In a situation where -3 reaches the buried oxide film 20, the refractory metal suicides the residual silicon layer in the buried oxide film 20 and erodes the defects. As a result, it is considered that the breakdown voltage of the buried oxide film 20 is deteriorated or the upper semiconductor layer 10 and the lower semiconductor layer 30 are short-circuited.

If the SOI substrate is always carefully selected and used without any defect, it is difficult to notice such a factor. In the case of making a request to use the SOI substrate without being particularly carefully selected and proposing to meet the demand, a problem occurs in the breakdown voltage of the semiconductor device as described above, and a solution to the problem is required.

The present inventor has paid attention to the problem of the SOI substrate as described above and has created the present invention.

Therefore, according to the present invention, in the SOI substrate,
Before performing silicidation after performing element isolation on the upper semiconductor layer, a region where the film thickness of the upper semiconductor layer is partially thinned in the process of forming the element isolation region, for example, an element isolation region and an active region located between them. On the neighborhood of the boundary of
A silicide prevention film is formed on a region where the film thickness of the upper semiconductor layer is thinned, for example, a region where the film thickness is intentionally thinned like the region where the transistor on the right side in FIG. 3 is formed, and then silicidation is performed. This makes it possible to prevent the silicide layer from reaching the buried oxide film.
As a result, a semiconductor device capable of solving the above problems in the SOI substrate is obtained. Then, by forming a silicide prevention film on the side wall formed on the side portion of the gate region, a semiconductor device with further improved characteristics is obtained.

(Embodiment) An embodiment of the semiconductor device of the present invention will be described below with reference to FIGS. 1 and 2 which schematically show the manufacturing process thereof. As the SOI substrate, the lower semiconductor layer 30 having a thickness of, for example, 600 μm, the thickness of, for example, 10
A buried oxide film 20 having a thickness of 0 nm and a thickness of, for example, 50 to 60
The upper semiconductor layer 10 having a thickness of 10 nm is used in this order.
The SOI substrate is manufactured by implanting oxygen into a silicon substrate and then heat-treating it to form a buried oxide film 20.

A SiO ₂ film having a thickness of, for example, 7 n is formed on the SOI substrate.
After the m deposition, a SiN film having a thickness of, for example, 85 nm is further formed by the low pressure CVD method. By the Photo-etching process, patterning to open a portion for forming a thin region of the photoresist, further, SiN film and the SiO
After etching the _two films, thermal oxidation is performed to form a surface oxide film on the upper semiconductor layer 10. First, the SiN film is removed by using an etchant such as phosphoric acid, and the surface oxide film is further removed by an oxide film etchant such as HF. Used to remove (see FIG. 1 (a)). In this way, the film thickness is adjusted so that the upper semiconductor layer 10 has a thin region and a region thicker than that.
Here, the thin region has a film thickness of, for example, 40 nm, and this region is not shown.

Next, thermal oxidation is performed to form a pad oxide film 40 having a thickness of, for example, 7 nm, and Si is further formed by a low pressure CDV method.
The N film 50 is formed to have a thickness of, for example, 85 nm ((FIG. 1
See (b). ). Then, a photo-etching process for determining the element isolation region and the active region is performed, and the SiN film 5 is formed.
0 is patterned (see FIG. 1C). Here, the SiN film is opened in a portion facing the element isolation region.

Next, the element isolation region 60 is formed by using the Locos method.
Are formed (see FIG. 1D). The oxidation by this Locos method is dry O ₂ oxidation, and the substrate temperature is 1100 ° C.
It takes 90 minutes. At this time, the region of the upper semiconductor layer 10 which is not oxidized (active region) is the element isolation region 6
The closer it is to 0, the thinner it becomes compared to the central region. This is because bird's beaks enter the surface of the upper semiconductor layer 10 and the interface between the buried oxide film 20 at the edge portion of the active region during thermal oxidation, so that the film thickness of the upper semiconductor layer 10 forming the active region becomes thin. Because. Here, the amount of locos oxidation for forming the element isolation region is over-oxidized more than the Si equivalent amount of the upper semiconductor layer in order to always achieve element isolation. For example, when the upper semiconductor layer has a thickness of 50 nm, the amount of oxidation just required for the oxidation is 110 nm in terms of the SiO ₂ film thickness, but in the case of actual processing, 15% to 20% overoxidation is performed.

The central portion of the upper semiconductor layer 10 has a thickness of, for example, about 50 nm, and the element isolation region 60 is formed.
The thinnest part in the vicinity of is about 45 nm, for example. The upper semiconductor layer 10 is, for example, approximately 5 nm thinner than the central portion in the vicinity of the element isolation region 60, and the central portion is not substantially thinner than the original thickness or approximately 5 n.
It has become thinner.

Next, the SiN film 50 is removed using an etchant such as phosphoric acid. P-type impurity ions are implanted into the upper semiconductor layer 10, which is an active region surrounded by the element isolation region 60, through the pad oxide film 40 from the direction normal to the semiconductor substrate for controlling the threshold value (FIG. 1 (e)). )reference). Here, for example, when the pad oxide film 40 has a thickness of 5 to 10 nm, the ion implantation conditions for the P-type impurities are ¹¹ B ⁺ ions of 5 to 15 K so as to form a peak in the center of the upper semiconductor.
The eV or ⁴⁹ BF ₂ ⁺ ion is 20 to 70 KeV, and the implantation amount is 0.2 to 1 × 10 ¹³ ions / cm ² .

Next, after removing the pad oxide film 40, a gate insulating film 70 which is a silicon oxide film is deposited in the active region. Here, the gate insulating film 70 has a thickness of 7 to 10 n if the channel length of the transistor to be manufactured is 0.35 μm.
m. Next, a polysilicon film having a thickness of 200 nm is formed on the entire surface of the gate insulating film 70 by using a low pressure CVD method, and then patterned by a photoetching process to form a gate region (gate electrode) 90. Further, a silicon oxide film is deposited on the entire surface of the semiconductor substrate by the CVD method or the like, and the sidewall 80 is formed on the side surface of the gate region by anisotropic etching.

Next, ³¹ P + ions, which are N-type impurities, are implanted into the entire surface of the semiconductor substrate from the direction normal to the semiconductor substrate using the gate region 90 and the sidewalls 80 as masks to form the N / source regions. Type impurity diffusion layer 1
0-2 and a gate region (gate electrode) 90 are formed (see FIG. 2F).

Next, as a film for preventing silicidation (silicide prevention film), a silicon oxide film 100 having a thickness of, for example, 20 to 50 nm may be formed on the entire surface of the semiconductor substrate by the CVD method. Deposit 500Å (see Fig. 2 (g)). The silicide prevention film is not limited to the silicon oxide film, but can be any of the SiO ₂ and SiN films.
Examples thereof include a heavy structure, and the thickness thereof is, for example, SiO.
₂ film is 5 ~ 10nm thick, SiN film is 10 ~ 40nm thick
nm may be sufficient. In short, it is sufficient that it can be wet-etched like a silicon oxide film and can prevent silicide.

Then, the photoresist 110 is patterned by a photo-etching process so as to open a region to be silicidized (silicided region) (FIG. 2).
(See (h)). This opening is formed facing the gate region and the source / drain. When this patterning is performed, a photoresist 110 is formed on the active region and the element isolation region 60 so that the silicon oxide film 100 is not etched at least in the etching process in the vicinity of the boundary between the active region and the element isolation region. Patterning is performed so that it remains.

At this time, patterning is performed so that the photoresist 110 remains on the thin region of the upper semiconductor layer 10 and also on the sidewall 80. Here, the photoresist 110 is also formed on the sidewall 80.
The ion implantation is performed as described above to form the source / drain regions, so that the sidewall 8 is left.
The oxide film in the 0th part is damaged, and H in the later process
Since the etching rate of the oxide film such as F is faster than that of the silicide prevention film, when the gate region is silicidized,
This is because it is likely that it becomes difficult for the sidewall 80 to secure a sufficient film thickness for preventing a bridge short between the gate region and the source / drain regions. When the upper semiconductor layer 10 of the semiconductor substrate is provided with a region for obtaining a resistance element, a bipolar element, or the like, the photoresist 110 is left even for a region that is inconvenient for these elements if silicided.

Next, the silicon oxide film 100, which is a silicide prevention film, is etched using an oxide film etchant such as HF with the photoresist 110 as a mask (see FIG. 1H). At this time, the silicon oxide film 100 is etched so as to face the silicided region, and subsequently, the upper semiconductor layer 10 is also removed with respect to the remaining film of the sidewall oxide film and the silicon oxide film which is the gate oxide film 70.
Etch until it reaches. When the silicon oxide film 100, which is the silicide prevention film, is etched by dry etching, the surface of the upper semiconductor layer 10 is damaged, and overetching is required to completely remove the silicide prevention film. That is, the upper semiconductor layer 10 is thinned to a thickness corresponding to over-etching, and reaction variation of silicidation in the subsequent step or silicide reaches the buried oxide film 20, and further, the upper semiconductor layer 10 is thinned. As a result, the upper semiconductor layer 10 is removed in the etching in the contact hole forming step which will be performed later.
May penetrate through. Therefore, the etching for opening the silicidation region is performed by wet etching without damage.

Next, after removing the photoresist 110, Ti, which is a refractory metal, is sputtered to deposit a refractory metal layer 120 (see FIG. 2 (i)). For example, when the original thickness of the upper semiconductor layer 10 is 50 to 60 nm and the thickness of the thin region is about 40 nm, the thickness of the refractory metal layer is 15 to 2 because the semiconductor layer is not completely silicided.
5 nm. Although Ti has been given as an example of the refractory metal for silicidation, the present invention is not limited to this, and for example, Co or N may be used.
You may use i etc.

Then, in order to react Si and Ti, heat treatment is performed at 650 ° C. for about 40 seconds in a lamp annealing device, and titanium and silicon are respectively added to the upper part of the gate region and the silicided regions of the source / drain regions. A silicide layer 90 'and a silicide layer 10-2' are formed by silicidation. Next, an ammonia-hydrogen peroxide treatment is performed to remove unreacted Ti. Further, annealing is performed at 850 ° C. for about 10 seconds to reduce the resistance of these silicide layers for the purpose of changing the phase of the silicide layers (see FIG. 2 (j)).

In FIG. 2 (j), a region corresponding to the thick region of the upper semiconductor layer 10 is shown, so that the thick region and the thin region are shown together in FIG. In this figure,
A transistor formed in the thick region is shown on the left side, and a transistor formed in the thin region is shown on the right side. Focusing on the transistor formed in the thick region, the active region is thin near the boundary with the element isolation region 60, but the silicide layer 1 in which the active layer is formed is formed.
0-2 ′ is the buried oxide film 20 even in the vicinity of the boundary.
Has not reached. The thickness of the silicide layer 10-2 'is, for example, about 30 nm.

Here, when the original thickness of the thick region of the upper semiconductor layer 10 is 50 to 60 nm, for example, the silicide layer 10
-2 'is the element isolation region 60 at the end on the element isolation region 60 side.
From 0.2 .mu.m, for example, 0.
It is sufficient if it is about 1 μm or more. In addition, here 0.1 μm
In the following case, there is a demerit that the sufficient width of the silicide prevention film cannot be obtained due to the process variation in the wet etching of the silicide prevention film 100. To this end, the silicide prevention film 100 is provided near the boundary between the active layer and the element isolation region 60 as described above, and has a length of, for example, 0.2 μm toward the gate region 90 side from the boundary. Is set to 0.
It may be about 1 μm or more. When the thickness is 0.1 μm or less, there is a demerit (inconvenience) that a sufficient width of the silicide prevention film cannot be obtained due to process variation during wet etching of the silicide prevention film. The silicide prevention film 100 may have a length of, for example, 0.2 μm in the direction opposite to this direction from the boundary, or may have a length of 0.1 μm or more. Here, 0.1
When it is less than μm, there is a demerit (inconvenience) that a sufficient width of the silicide prevention film cannot be obtained due to process variation during wet etching of the silicide prevention film.
Etc. Further, focusing on the transistor formed in the thin region, no silicide layer is formed in the active layer.

In both transistors, a silicide layer 90 'is formed above the gate region 90. In addition, the presence of the silicide prevention film 100 on the sidewalls 80 causes the source / drain regions 10 to be formed.
Since no silicide rises from −2 to the gate region 90, a bridge short is not formed.

As described above, the source / drain regions 10-2, which are the active layers, are left in an unsilicided state where Ti and Si have not reacted with the buried oxide film 20. . Therefore, not only is the silicon remaining in the buried oxide film 20 prevented from being silicidized, but also the defects in the buried oxide film 20 are prevented from being eroded.

After this, it goes without saying that a contact is formed in these silicide layers to form a transistor by a known technique.

FIG. 4 shows the withstand voltage characteristics of the buried oxide film in the transistor of this embodiment. In this figure, the horizontal axis represents voltage and the vertical axis represents current. The characteristics of the transistor shown in FIG. 3 of the present invention are indicated by circles, and the characteristics of the transistor shown in FIG. 6 are indicated by squares. From this figure, it is understood that the buried oxide film of the transistor of the embodiment of the present invention has excellent withstand voltage characteristics.

In the above example, the case where the silicide prevention film is redeposited after the gate sidewall is formed has been described, but the present invention is not limited to this.
It is also possible to use the oxide film itself for the gate sidewall as the anti-silicide film, for example, during anisotropic etching when forming the gate sidewall,
It can be realized by leaving about 500 to 600 Å of the silicon oxide film on the active region so as to become a silicide prevention film in a later process.

[0052]

According to the present invention, in a semiconductor device,
It is possible to prevent the breakdown voltage characteristic of the buried oxide film of the SOI substrate from being deteriorated, and further, it is possible to prevent the bridge short circuit between the gate and the source / drain. According to the method, SO
Even when the residual silicon or the defect in the buried oxide film peculiar to the I substrate is present, the residual silicon in the buried oxide film is not silicidized and the refractory metal is not eroded in the defect portion. This contributes to the provision of a semiconductor device in which the breakdown voltage of the buried oxide film or the short-circuit between the upper semiconductor layer and the lower semiconductor layer is prevented.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for schematically explaining a manufacturing process of an embodiment of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view for schematically explaining the manufacturing process of the embodiment of the semiconductor device of the present invention.

FIG. 3 is a cross-sectional view schematically illustrating the configuration of the embodiment of the semiconductor device of the present invention.

FIG. 4 is a withstand voltage characteristic diagram of a buried oxide film according to an embodiment of a semiconductor device of the present invention.

FIG. 5 is a cross-sectional view for schematically explaining the manufacturing process of the embodiment of the conventional semiconductor device.

FIG. 6 is a cross-sectional view schematically illustrating the configuration of a semiconductor device before application of the present invention.

[Explanation of symbols]

10 upper semiconductor layer 20 buried oxide film 30 lower semiconductor layer 40 pad oxide film 50 SiN film 60 element isolation region 70 gate insulating film 80 sidewall 90 gate region 90 ′ silicide layer 100 silicon oxide film (silicide prevention film) 10-1 channel Region 10-2 Source / Drain Region 10-2 ′ Silicide Layer 120 Refractory Metal

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 29/786 H01L 21/336

Claims (9)

(57) [Claims] 1. On an SOI substrate having an upper semiconductor layer on a buried oxide film, the locos oxidation of the upper semiconductor layer is performed.
The first active region separated by the element isolation region according to
The channel region formed in the first active region and the cha
A source region and a drain region sandwiching the channel region;
Gate region made of a polycrystalline silicon layer facing the channel region
Possess a band, the source region, the silicide is a compound of a refractory metal and silicon on the surface of the drain region, the second
The film thickness of one active region is equal to
The closer it is to the remote area, the thinner it becomes compared to the central area of the active area.
A semiconductor device are I, in on the source region, the drain region and the isolation region, the source region and the element isolation region, drain
There is a silicide prevention film on the vicinity of the boundary with the in region, and the source region and the drain region under the silicide prevention film are provided.
A semiconductor device characterized in that no silicide is formed on the surface of the region . 2. A thick region and a thin region on the buried oxide film.
On an SOI substrate having an upper semiconductor layer consisting of
The upper semiconductor layer is formed by the element isolation region formed by locos oxidation.
Separated from the first active region consisting of the thick region and thin
A second active region comprising a region and the first and second active regions
The channel region formed in the region and the channel region
The source and drain regions and the channel region.
Facing the gate region made of a polycrystalline silicon layer,
Refractory metal and silicon on the surface of the source and drain regions
A silicide that is a compound of
The thickness of each of the conductive regions is
The closer it is to the element isolation region, the more it is compared to the central region of the active region.
A thin semiconductor device, comprising: the source region and the drain region in the first active region.
The element isolation region above the region and the element isolation region.
Near the boundary between the region and the source region, the drain region,
The source region and the drain region in the second active region
A silicide prevention film covering the region, and the source region and the drain region under the silicide prevention film.
The feature is that no silicide is formed on the surface of the area.
Semiconductor device to be collected . 3. A semiconductor device according to claim 1 or 2, characterized in that it has a silicide barrier layer also on the side wall located on the side of the gate region. 4. The silicide prevention film is formed of the first active material.
Predetermined on the source region and the drain region in the region
Selectively formed to have an opening, the opening
Is closer to the element isolation region in the first active region.
4. The semiconductor device according to claim 1, wherein the semiconductor device does not overlap with a region that becomes thinner . 5. A first active region is formed by performing locos oxidation for forming an element isolation region on the upper semiconductor layer of an SOI substrate having an upper semiconductor layer on a buried oxide film.
And the film thickness of the first active region is
The closer it is to the element isolation region, the more it is compared to the central region of the active region.
A step of thinning , a channel region and the channel region in the first active region.
Forming a source region and a drain region sandwiching the region,
Gate region made of a polycrystalline silicon layer facing the channel region
And frequency, and a step of forming a side wall on the side of the gate region, there is on the source region, the drain region and the isolation region, the source region and the element isolation region, drain
A step of selectively forming a silicide prevention film on the vicinity of the boundary with the in region; and a heat treatment after depositing a refractory metal to form the source region and the drain where the silicide prevention film is not formed. A method of manufacturing a semiconductor device, comprising the step of siliciding the surface of the region. 6. A thick region and a thin region on the buried oxide film.
An SOI substrate having an upper semiconductor layer comprising
Locos oxidation is performed on the upper semiconductor layer to form an element isolation region.
By performing the first active region consisting of the thick region
And forming a second active region consisting of the thin region
The thickness of each of the first and second active regions
The closer to the element isolation region, the more
And thinning the first and second active regions into the channel region and the channel.
A source region and a drain region sandwiching the channel region are formed,
Consisting of a polycrystalline silicon layer facing the channel region
Gate regions and sidewalls on the sides of the gate regions
Forming a said source region in the first active region, a drain territory
The element isolation region above the region and the element isolation region.
Near the boundary between the region and the source region, the drain region,
The source region and the drain region in the second active region
A process to selectively form a silicide prevention film to cover the area
And extent, after depositing a refractory metal, a heat treatment is performed the Shirisai
In the first active region where the anti-reflection film is not formed
Silicide the surfaces of the source region and the drain region
A method of manufacturing a semiconductor device, comprising the steps of: 7. In the step of selectively forming the silicide prevention film, a portion of the first active region corresponding to the element is formed.
7. The method of manufacturing a semiconductor device according to claim 5, wherein the suicide prevention film is formed so as to cover a region that becomes thinner as it gets closer to the separated region . 8. The semiconductor device according to claim 5, wherein in the step of selectively forming the silicide prevention film, the silicide prevention film is also formed on the sidewalls. Manufacturing method. 9. A process for the silicidation claim 5, characterized in that it comprises a silicidation of the gate <br/> preparative region
9. The method for manufacturing a semiconductor device according to any one of items 8 to 8.