JP3443154B2 - Asynchronous reset method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous reset system, and more particularly to an asynchronous reset system for asynchronously resetting a synchronous circuit operating in synchronization with a system clock signal according to an asynchronous reset signal generated at an arbitrary timing. . When initializing the entire system, the entire system may be forcibly reset by an asynchronous system reset signal, but a specific synchronous circuit (flip-flop circuit, register circuit, counter circuit, other predetermined function) during system operation. There is often a case where it is desired to reset only the LSI circuit etc. which realizes the above) asynchronously and without adversely affecting the operation of other systems.

[0002]

2. Description of the Related Art FIG. 8 is a diagram for explaining the prior art. In the figure, 2 is a register circuit (REG) and 7 is an AND gate circuit (A). In FIG. 8A, for example, the register circuit 2 which is a system synchronization circuit sets the input data ID at each rising edge of the system clock signal CK and outputs the output data OD. The system reset signal SRS and the asynchronous reset signal XRS are directly input to the reset terminal of the register circuit 2 and are forcedly reset regardless of the clock signal CK (asynchronous) by the generation of either one.

In this case, the system reset signal SRS
Since it is used for the purpose of initializing the entire system, there is no problem, but since the asynchronous reset signal XRS is used for the purpose of resetting only the register circuit 2 during the operation of the system, it is surely reset at each desired timing. Needs to be done. In this regard, as shown in FIG. 8B, when the asynchronous reset signal XRS is generated outside the rising edges of the clock signal CK, the output data OD of the register circuit 2 is reliably reset every time. , The purpose of asynchronous reset can be achieved. That is, the system outputs the output data OD at each asynchronous reset timing.
When = 0, the operation can be continued without malfunction.

However, as shown in FIG. 8C, when the asynchronous reset signal XRS is generated in such a manner that it overlaps with the clock signal CK, the register circuit 2 has a delicate timing (setup / hold timing). The output data OD of is not reset, and indefinite data may be output. For this purpose, the system (CPU
Output data OD = at each necessary timing required by
It may not be 0 and may adversely affect the operation of the system.

This problem is not limited to the register circuit 2,
It may occur in any other synchronization circuit (flip-flop circuit, counter circuit, other LSI circuit that realizes a predetermined function, etc.).

[0006]

As described above, conventionally, the synchronous circuit is directly forcibly reset by the asynchronous reset signal XRS, so that there is a problem that the output of the synchronous circuit becomes indefinite. The object of the present invention is to ensure that the contents of the synchronous circuit are ensured no matter what timing the asynchronous reset signal is input.
It is to provide an asynchronous reset method that can be reset.

[0007]

The above problems can be solved by the structure shown in FIG. That is, the asynchronous reset method of the present invention (1) uses the asynchronous reset signal XR of the input.
With latches holding the S, the subsequent comprising a synchronizing pulse generating circuit 3 in synchronization with the system clock signal CK to generate a synchronizing pulse signal DP of one clock period by having the clock synchronization set function of the data in the system < The input data of the register circuit 2 is configured to be masked by the synchronization pulse signal DP.

The above problem can be solved by the structure of FIG. That is, the asynchronous reset method of the present invention (2) includes the synchronous pulse generating circuit 3 of the present invention (1), and supplies a synchronous pulse signal to the load energizing terminal LD of the synchronous circuit 5 having a clock synchronous load function of data in the system. D
It is configured to add P. The above problem is solved by the configuration of FIG. That is, the asynchronous reset method of the present invention (3) includes the synchronous pulse generating circuit 3 of the present invention (1), and the reset energizing terminal C of the synchronous circuit 6 having the clock synchronous reset function in the system.
The configuration is such that the synchronization pulse signal DP is added to R.

The above problem can be solved by the configuration of FIG. That is, according to the asynchronous reset method of the present invention (4), the system clock signal CK, the asynchronous reset signal XRS, and the gate signal GS that is generated in synchronization with the asynchronous reset signal and has a predetermined spread before and after it. Based on the level of the gate signal,
One of the stem clock signal and the asynchronous reset signal
With selecting, when having a clock signal and the asynchronous reset signal and overlaps part of the system, its weight
A clock synthesis circuit 4 is newly formed by blocking the output of the clock signal from immediately after the occurrence of the clock signal until the generation of the next clock signal, and a clock synchronization setting function for data in the system is provided. br /> register the synthesized clock signal CK' the clock input terminal of the circuit 2 is added, and in which the input data was configured to masked by the gate signal GS.

The above problem can be solved by the structure of FIG. That is, the asynchronous reset method of the present invention (5) includes the clock synthesis circuit 4 of the present invention (4), and supplies the gate signal GS to the load energizing terminal LD of the synchronization circuit 5 having the clock synchronous load function of data in the system. In addition, a synthetic clock signal CK is applied to its clock input terminal.
'Is added.

The above problem can be solved by the structure of FIG. That is, the asynchronous reset method of the present invention (6) includes the clock synthesizing circuit 4 of the present invention (4), adds the gate signal GS to the reset energizing terminal CR of the synchronous circuit 6 having the clock synchronous reset function in the system,
In addition, the composite clock signal CK 'is added to its clock input terminal.

[0012]

In the asynchronous reset method of the present invention (1) of FIG. 1A, the synchronous pulse generation circuit 3 latches and holds the input asynchronous reset signal XRS, and the clock signal of the subsequent system. 1 clock cycle in synchronization with CK
Minute sync pulse signal DP is generated. As a result, normally, the input data ID is set in the register circuit 2 by the clock signal CK. Asynchronous reset signal XRS
If There generated in an arbitrary timing, the subsequent because the input data by one clock period of the synchronizing pulse signal DP synchronized with the clock signal CK is masked by the mask circuit 1, the register circuit 2 reliably reset (data 0 Set).

In the asynchronous reset method of the present invention (2) of FIG. 1B, a synchronous circuit (for example, a counter circuit having a data parallel load function) 5 having a data clock synchronous load function is usually a clock signal CK. Count up in sync with. Further, according to the present invention, since the above-mentioned synchronous pulse signal DP is applied to the load energizing terminal LD of the counter circuit 5, even if the asynchronous reset signal XRS is generated at an arbitrary timing, the subsequent clock signal CK is generated. The counter circuit 5 can be surely reset (count value CN = 0) by the synchronization pulse signal DP of one clock cycle synchronized with.

In the asynchronous reset method of the present invention (3) of FIG. 1C, a synchronous circuit (for example, a counter circuit) having a clock synchronous reset function in the system.
6 usually counts up in synchronization with the clock signal CK. Further, according to the present invention, since the above-mentioned synchronous pulse signal DP is applied to the reset energizing terminal CR of the counter circuit 6, even if the asynchronous reset signal XRS is generated at an arbitrary timing, the subsequent clock signal CK is generated. The counter circuit 5 is surely reset (count value CN = 0
You can.

Further, in the asynchronous reset system of the invention (4) of FIG. 2A, the clock synthesizing circuit 4 includes a system clock signal CK and an asynchronous reset signal XRS.
And a gate signal GS which is generated in synchronism with the asynchronous reset signal and has a predetermined spread before and after the asynchronous reset signal , according to the level of the gate signal GS of the system.
One of the clock signal CK and the asynchronous reset signal XRS
Whichever of the two is selected and the clock signal CK of the system
When the asynchronous reset signal XRS and the asynchronous reset signal XRS have an overlapping portion, immediately after the overlapping portion until the next clock signal is generated.
By inhibiting the output of the clock signal of, the new synthesized clock signal CK 'is formed.

As a result, normally, the input data ID is the clock signal CK incorporated in the combined clock signal CK '.
Is set in the register circuit 2 by. When the asynchronous reset signal XRS is generated at any timing,
The input data ID is masked by the gate signal GS having a width slightly wider than the asynchronous reset signal XRS, and the clock terminal of the register circuit 2 receives the asynchronous reset signal XRS incorporated in the composite clock signal CK 'at this timing. Therefore, the register circuit 2 is surely reset (data 0 is set).

According to the present invention (4), since the register circuit 2 is reset in synchronization with the asynchronous reset signal XRS, there is no delay in the reset operation. The same applies to the following inventions (5) and (6). Further, in the asynchronous reset method of the present invention (5) of FIG. 2B, a synchronous circuit (for example, a counter circuit with a parallel data loading function) 5 having a clock synchronous loading function of data in the system is usually a synthetic clock signal CK. It counts up in synchronization with the clock signal CK incorporated in ‘ According to the present invention, the load energizing terminal L of the counter circuit 5 is
Since the gate signal GS is added to D and the composite clock signal CK 'is added to its clock input terminal, even if the asynchronous reset signal XRS is generated at an arbitrary timing, it is incorporated in the composite clock signal CK'. The counter circuit 5 can be reliably reset (count value CN = 0) by the asynchronous reset signal XRS.

Further, in the asynchronous reset method of the present invention (6) of FIG. 2C, a synchronous circuit (for example, a counter circuit) having a clock synchronous reset function in the system.
6 normally counts up in synchronization with the clock signal CK incorporated in the combined clock signal CK '. And according to the present invention, the reset energizing terminal CR of the counter circuit 6 is
Since the gate signal GS is added to and the combined clock signal CK 'is added to the clock input terminal,
Even if the asynchronous reset signal XRS is generated at an arbitrary timing, the counter circuit 6 can be reliably reset (count value CN = 0) by the asynchronous reset signal XRS incorporated in the combined clock signal CK ′.

[0019]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals denote the same or corresponding parts throughout the drawings. FIG. 3 is a diagram showing the configuration of the asynchronous reset system of the first embodiment. In the figure, 1 is a sector (SEL) which is an example of a mask circuit, 2 is a register (REG), 3 is a synchronous pulse generation circuit, and 31 is an inverter. Circuits (I) and 32 are set / reset (latch) type flip-flop circuits (SRF), and 33 and 34 are D
(Delay) type flip-flop circuit (DF
F) and 35 are AND gate circuits (A).

FIG. 4 is a timing chart of the asynchronous reset system of the first embodiment. Normally, the sync pulse signal D
Since P is at the LOW level, the selector 1 selects and outputs the input data ID. Therefore, the register 2 sets the input data ID at each rising edge of the clock signal CK and outputs the corresponding output data OD. When the asynchronous reset signal XRS is input at the timing shown in the figure, the flip-flop circuit 32 is set at the falling edge.
The flip-flop circuit 33 outputs the subsequent clock signal CK.
Is set at the rising edge of, and further operates in cooperation with the flip-flop circuit 34 and the AND gate circuit 35 to generate the HIGH level synchronizing pulse signal DP for one clock cycle. As a result, the selector 1 selects and outputs "0" data in this section, and the register 2 is reliably reset (output data OD = 0 is set) at the rising edge of the clock signal CK at the end of this section. . After that, it returns to the normal operation.

Note that this relationship is related to the asynchronous reset signal XR.
It does not change even if the generation position of S moves to point A. on the other hand,
If it is delayed from the position of point B, the generation of the synchronization pulse signal DP is delayed by one clock cycle. Further, in the present embodiment, after the asynchronous reset signal XRS is generated, there is a maximum delay of 2 clock cycles until the actual reset, but when the frequency of the clock signal CK is high, this delay is not a serious problem. Further, such a synchronizing pulse generating circuit 3 can be configured by a simple circuit.

FIG. 5 is a diagram showing the configuration of the asynchronous reset system of the second embodiment, in which 4 is a clock synthesis circuit and 4 is a clock synthesis circuit.
1 to 43 are D (delay) type flip-flop circuits (DFF), 44 are set / reset (latch) type flip-flop circuits (SRF), 45 is a selector (SEL), and 46 to 49 are AND gate circuits (A). ), 5
Reference numeral 0 is an OR gate circuit (O), and 51 and 52 are inverter circuits (I).

In the clock synthesis circuit 4, the selector 4
5 selects (exclusively synthesizes) the clock signal CK while the gate signal GS is HIGH level, and the gate signal GS is L
During the OW level, the asynchronous reset signal XRS is selected (combined exclusively) and output. The AND gate circuit 46 detects the presence or absence of the overlap between the clock signal CK and the asynchronous reset signal XRS, and if there is the overlap, the flip-flop circuit 41 is set and cooperates with the following circuits, and thereafter A control signal SR-Q for preventing synthesis of the clock signal CK is formed. In order to perform such signal processing at high speed, the clock synthesizing circuit 4 has a clock signal MC that is sufficiently faster than the clock signal CK.
K has been entered. The details of the operation will be described below with reference to the timing chart.

FIGS. 6 and 7 are timing charts (1) and (2) of the asynchronous reset method of the second embodiment. Figure 6
, The asynchronous reset signal XRS is the gate signal GS
Together with the system (for example, the CPU of the control unit), and the gate signal GS is the asynchronous reset signal X.
Each RS has a predetermined width before and after the RS.

When the asynchronous reset signal XRS is input at the timing A, for example, the asynchronous reset signal XRS
, And the HIGH level portion of the clock signal CK have no overlapping portion, the flip-flop circuit 41 is not set. Therefore, the flip-flop circuit 44 remains set, and the control signal SR-Q of its output is maintained at the HIGH level. As a result, the clock signal CK is selected while the gate signal GS is at the HIGH level, and the asynchronous reset signal XRS / (however, / is provided when the gate signal GS is at the LOW level).
Represents an inverted signal) to form a composite clock signal CK 'in this section.

On the other hand, in the selector 1, the gate signal GS is HI.
The input data ID is selected in the section of GH level, and the data of "0" is selected in the section of the gate signal GS being LOW level. Therefore, the register 2 in the above section synchronizes with the input data I in synchronization with the rising edge of the clock signal CK.
Since D (= a) is set and data of "0" is set in synchronization with the subsequent fall of the asynchronous reset signal XRS, the asynchronous reset of the register 2 is surely performed in real time.

When the asynchronous reset signal XRS is input at the timing B, since the LOW level portion of the asynchronous reset signal XRS and the HIGH level portion of the clock signal CK have an overlapping portion, the flip-flop circuit 41 has a gate. The signal GS is quickly set by the high-speed clock signal cut out by the AND gate circuit 47 in the LOW level section. As a result, the flip-flop circuit 42 and the AND gate circuit 48 jointly generate a pulse signal of one clock cycle of the clock signal MCK.

When the flip-flop circuit 44 is forcibly reset by the pulse signal, the control signal SR-Q of its output becomes the LOW level, whereby the subsequent output of the selector 45 is blocked. That is, in this case, the output of the latter half portion of the clock signal CK appearing at the timing B'is blocked by the AND gate circuit 49. The flip-flop circuit 43 receives the next clock signal CK.
The signal which is reset by the rise of the signal and becomes HIGH level forcibly sets the flip-flop circuit 44.

Therefore, the register 2 in the above section synchronizes with the input data I in synchronization with the rising edge of the clock signal CK.
Since D (= d) is set and data of "0" is set in synchronization with the subsequent fall of the asynchronous reset signal XRS, the asynchronous reset of the register 2 is surely performed in real time. In FIG. 7, when the asynchronous reset signal XRS is input at the timing of C, first, the LOW level portion of the first half of the asynchronous reset signal XRS is cut out and combined and output as the combined clock signal CK ′.
Further, the latter LOW level portion of the asynchronous reset signal XRS has an overlapping portion with the HIGH level portion of the clock signal CK, so the flip-flop circuit 4
1 is set quickly by a high speed clock signal. As a result, a pulse signal is generated and the control signal SR-
Q becomes LOW level until the next rising of the clock signal CK, and thereby the output of the latter half of the clock signal CK appearing at the timing of C ′ is blocked.

Therefore, the register 2 in the above section is set with data "0" in synchronization with the fall of the asynchronous reset signal XRS, and the asynchronous reset of the register 2 is surely performed in real time. Although the above embodiment has shown an example of application to the register circuit 2 operating in synchronization with the system clock signal CK, other types of synchronizing circuits (flip-flop circuit, counter circuit, other predetermined functions) It can be easily realized based on FIGS. 1 and 2 and the description thereof.

Although a plurality of preferred embodiments of the present invention have been described above, the synchronizing pulse generating circuit 3, the clock synthesizing circuit 4, the mask circuit 1 and the like can be implemented in various modes without departing from the concept of the present invention. It goes without saying that it can be configured.

[0032]

As described above, since the asynchronous reset method of the present invention has the above-mentioned structure, the contents of the synchronous circuit can be surely maintained no matter what timing the asynchronous reset signal is input.
It can be reset to.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram for explaining the principle of the present invention.

FIG. 3 is a diagram showing a configuration of an asynchronous reset system according to a first embodiment.

FIG. 4 is a timing chart of the asynchronous reset method of the first embodiment.

FIG. 5 is a diagram showing a configuration of an asynchronous reset system according to a second embodiment.

FIG. 6 is a timing chart (1) of the asynchronous reset method according to the second embodiment.

FIG. 7 is a timing chart (2) of the asynchronous reset method according to the second embodiment.

FIG. 8 is a diagram illustrating a conventional technique.

[Explanation of symbols]

1 Mask circuit 2 registers 3 Synchronous pulse generation circuit 4 clock synthesis circuit 5,6 Synchronous circuit

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Claims (6)

(57) [Claims] 1. A latch holding asynchronous input reset signal
To together, comprising a synchronizing pulse generating circuit for generating the subsequent one clock period of the synchronizing pulse signal in synchronization with the clock signal of the system, have a clock synchronization set function of the data in the system
The asynchronous reset method is characterized in that the input data of the register circuit is masked by a synchronous pulse signal. 2. An asynchronous reset comprising the sync pulse generating circuit according to claim 1, wherein a sync pulse signal is applied to a load energizing terminal of a sync circuit having a function of clock synchronous loading of data in a system. method. 3. An asynchronous reset system comprising the synchronous pulse generating circuit according to claim 1, wherein a synchronous pulse signal is applied to a reset energizing terminal of a synchronous circuit having a clock synchronous reset function in a system. 4. A system clock signal, an asynchronous reset signal, and a signal generated in synchronization with the asynchronous reset signal,
And based on the gate signal having each predetermined spread before and after that , according to the level of the gate signal,
Select one of the clock signal and the asynchronous reset signal
In addition, if the clock signal and the asynchronous reset signal of the system have an overlapping portion, immediately after the overlapping portion.
Following by blocking the output of the clock signal to the generation of the clock signal, a clock synthesis circuit for forming the newly synthesized clock signal, have a clock synchronization set function of the data in the system from the
Said composite clock signal to the clock input terminal of the register circuit to the addition, and asynchronously reset method, characterized in that the input data is configured to mask by the gate signal. 5. A clock synthesizing circuit according to claim 4, wherein a gate signal is applied to a load energizing terminal and a synthetic clock signal is applied to a clock input terminal of a synchronizing circuit having a function of synchronously loading data in a system. Asynchronous reset method characterized in that 6. The clock synthesizing circuit according to claim 4, wherein a gate signal is applied to a reset energizing terminal of a synchronous circuit having a clock synchronous reset function in a system, and a synthetic clock signal is applied to its clock input terminal. Asynchronous reset method characterized by the above.