JP3443988B2 - Signal generation circuit for vertical contour enhancement circuit and time compression / line synthesis circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] [Industrial applications]The present invention provides a method for enhancing the vertical contour of a video signal.
Signal generation circuit for time adjustment circuit and time compression / line synthesis circuit
It is about. [0002] 2. Description of the Related Art In recent years, high image quality in the vertical direction by sequential scanning has been achieved.
And aspect ratio of screen from conventional 4: 3 to 16: 9
Next-generation TV system pursuing widening
I have. Wide, compatible with such next-generation TV systems
Screen-compatible progressive scan imaging deviceInThe conventional imaging device
Must handle signals wider than the
Conventional digital signal processing circuit to reduce
Special use such as time compression / line synthesis circuit
A processing circuit is provided. [0003] Such a conventional sequential running for a wide screen.
Inspection imaging apparatus and time compression /
The line synthesis circuit will be described in detail with reference to FIGS.
I will explain it. FIG. 3 shows a conventional wide-screen progressive scanning camera.
FIG. 2 is a block diagram illustrating a configuration of an image device. In the figure,
Obtained by photoelectrically converting the image of the subject with the image sensor 24.
The obtained progressive scanning image signal is output to the analog signal processing circuit group 2
In step 5, adjust the black and white levels,
-Processing is performed. This analog signal is A / D converted
The signal is converted into a digital signal by the device 26. AD conversion
The progressive scanning image signal output from the unit 26 is divided into lines.
.Input to the time expansion circuit group 27 for each horizontal scanning line
And odd-numbered lines (1, 3, 5,...
Line (2, 4, 6 ... th scan line) signal sequence
Each signal sequence is divided into one horizontal scanning time
From one interlaced scanning system to one horizontal scanning time
Output in synchronization with the horizontal scanning of the interlaced scanning system.
Is forced. The time-expanded odd-numbered video signal is
The digital signal processing circuit group 28 has a time-stretched even-numbered line.
The video signal is supplied to a digital signal processing circuit group 29.
Gamma correction, blanking, matrix
Various types of digital processing such as pixel processing, vertical / horizontal contour enhancement processing, etc.
Is processed and output as a luminance signal and color difference signal.
It is. The digital signal processing circuit groups 28 and 29
FIG. 4 shows the configuration of the vertical contour emphasizing signal generation circuit of FIG. FIG.
, Input from a signal processing circuit of a preceding stage not shown
The R, G, and B imaging signals obtained by scanning the input signal one horizontal line
Write to memories 38, 39 and 40 which delay the inspection time
Is delayed by one horizontal scanning time of the interlaced scanning system.
You. R and G imaging signals output from memories 38 and 39
Is further input to the next memories 41 and 42, and
The horizontal scanning time is delayed. Also, there is no delay (0
H delay), the R and G imaging signals are added by the adder 43.
The result is a 0H delayed high-range luminance signal. One horizontal scan time
The delayed (1H delay), R and G imaging signals are added
And a 1H-delayed high-frequency luminance signal.
Then, two horizontal scanning time delays (2H delay), R and
And the G image signal are added by an adder 45 and delayed by 2H.
It becomes a high-frequency luminance signal. 0H and 2H delay high frequency luminance signal
Is 1H- (0H + 2H) / 2 for the vertical contour enhancement signal.
Addition to configure a bandpass filter (BPF)
And the vertical BP of (0H + 2H) / 2
It is output as an F creation signal. Also, the vertical contour enhancement signal
To construct a low-pass filter (LPF) for the signal
The selector 47 selects (0H + 2H) / 2, 0H high-frequency luminance
Signal, 1H high-range luminance signal, 2H high-range luminance signal, vertical L
One signal is selected by the PF selection signal, and the vertical LPF
It is output as a service signal. In addition, vertical contour emphasis signal creation
The R, G, and B imaging signals output from the circuit are converted to vertical BPF
Create vertical signal and vertical LPF signal
In order to match, they are output after being delayed by one horizontal direction. In FIG. 3, a digital signal processing circuit group
Odd lines and evens digitized at 28, 29
Each signal sequence of several lines is a time compression / line synthesis circuit group
At 30, the phase relationship before the time extension is
One horizontal scanning time from one horizontal scanning time of the line scanning system
The time is compressed to the scanning time, and the line
Is done. The time compression / line synthesis circuit group 30
The description will be made with reference to FIG. As shown in FIG.
The time compression / line synthesizing circuit group 30 has memories 48, 4
9 and a selector 50. FIG.
ThailandMiAs shown in FIG.
Extended to interlaced scanning systems with different frequencies
Odd line and even line output at the same timing
The two signal series are stored in the memory 48 and the memory 4
9 respectively. In the memory 48, write
After one horizontal scanning time from the start of
The reading is started at twice the frequency of the time. Memory 49
Then, after two horizontal scanning times of the sequential scanning system from the start of writing
Then, reading is started at twice the frequency of writing.
Output signals from the memories 48 and 49 are
Input to the selector 50, and the selector 50
Outputs signal from memory. In this manner, the image signal of the progressive scanning system is
Line division / time extension circuit group 27
Between two lines of the interline scanning system
The signal sequence is a digital signal compatible with the conventional TV system.
Digitally processed by the processing circuits 28 and 29 and time compressed
An image signal of the original sequential scanning system by the line combining circuit group 30;
Returned to the issue. In FIG. 4, a time compression / line synthesis circuit is shown.
The progressive scanning image signal output from the group 30 is converted into a digital signal.
The signal is converted into an analog signal by the detector 31 and output. The digital signal processing circuit groups 28 and 29
The two signal sequences subjected to digital processing are converted to a pixel synthesis circuit.
It is also input to the group 32. Odd by the pixel synthesis circuit group 32
The signal sequences of the two systems of several lines and even lines are added,
The signal is output as one signal, and the signal
The conversion circuit group 33 changes the aspect ratio from 16: 9.
4: 3 converted and analog by DA converter 31
Is converted into a signal, and the video signal of the interline scanning system is
can get. The digital signal processing circuits 28 and 29
The two signal sequences subjected to the digital processing are color difference signals VL.
It is also input to the PF circuit group 35. Color of two signal series
The difference signal is input by the color difference signal VLPF circuit group 35.
Delayed by one horizontal scanning time in the tarlace scanning system (n-
1) The signal of the line and the n-th line input simultaneously
1: 2: 1 drop on three lines of the (n + 1) th line signal
Direct LPF processing is performed and output as one system signal.
You. The luminance signals of the two signal sequences are output as they are.
You. One system output from the color difference signal VLPF circuit group 35
Color difference signal and luminance signal of two signal sequences are mapped
It is input to the circuit group 36. 3 in the mapping circuit group 36
Optical fiber with two signal sequences
To transmit one system of the luminance signal and the color difference signal
The remaining one system of the luminance signal is compressed to odd pixels (1, 3,
5th pixel) and even-numbered pixels (2, 4, 6,.
), And these two pixel-divided signal sequences are
The time-compressed luminance signal is time-compressed, respectively.
Mapping by inserting it into the non-signal part of the color difference signal
Perform Two systems output from the mapping circuit group 36
Signal sequence is converted from parallel to serial by the optical transmission unit.
Transmitted as an optical signal through an optical fiber, and
Real / parallel conversion and de-mapping circuit group 3
7 is input. In the de-mapping circuit group 37, the second system
Luminance signal, color difference signal, odd pixel and even number
Separate the reinforcement signal divided into pixels and time-expand each.
The reinforcement signal is composed of the odd and even pixels.
The luminance signal, color difference signal and
Output as a reinforcement signal. [0012] SUMMARY OF THE INVENTION
In conventional wide-screen progressive scanning imaging devices,
To use the digital signal processing circuit group of
Scan signal, interlace scan signal, interlace scan
Obtain output form suitable for various devices such as inspection signal + reinforcement signal
The line synthesis and time compression circuits required for
Because it is configured exclusively using general-purpose memory,
The problem of large size and high manufacturing cost
Even if a dedicated LSI is developed, the development cost
There was a problem that becomes high. The present invention has been made to solve such a problem.
The vertical contour correction signal generation circuit of the digital signal processing circuit
Circuit was used to create an LSI with only a small number of circuits.
Inexpensive by realizing a line synthesis / time compression circuit
Provides a small-scale circuit synthesis and time compression circuit
And the line synthesis / time compression circuit
The use of roads makes it possible to use
With the aim of providing a progressive scan imaging device that supports
are doing. [0014] [MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
In addition, the time compression / line synthesis circuit according to the present invention provides the first imaging
First input means for inputting a signal, and the first input means
1 that holds the input image signal for one line
A vertical contour emphasizing signal generating circuit having a storage means;
A second input means for inputting an image signal of the first type;
Output signal of the storage means and output from the second input means.
A first signal receiving an imaging signal and outputting a selected signal;
Signal switching circuit, and an output signal of the first signal switching circuit.
And a second memory for holding one line of imaging signals
Means, an output signal of the first storage means and the second storage means.
Input signal and output the selected signal
A second signal switching circuit, and a second signal switching circuit
Output means for outputting an output signal; and the first storage means
Controlling writing and reading of the second storage means;
And control means. [0015] According to the present invention, the time compression / ratio
According to the in-synthesis circuit, two horizontal scanning times
Time-expanded, two lines of odd and even lines
So that the image signal sequence of
And compress the odd and even lines of the imaging signal sequence.
As a time compression / line synthesis circuit for in-synthesis and output
Operation and switching the operation mode.
Also, it operates as a vertical contour emphasizing signal generating circuit. A time compression / line synthesis circuit will be described below.
The operation will be described. Odd lines (1, 3, 5, ...
Line) and even-numbered lines (2, 4, 6, ... line)
And the time is extended to the two horizontal scanning times of the sequential scanning system.
Of odd two lines of the imaging signal sequence,
The image signal is the first image signal, and the image signal of the even line is the second image signal.
The first input means and the second input means
Give to the column. The second imaging signal input to the second input means
Output from the first signal switching circuit,
The image signal of the line is stored in the first storage means.
Simultaneously writing the image signal into the second storage means;
The imaging signal of the odd line and the even line
Are the phase relationships before time expansion (1, 2, 3, 4,...).
Alternately in the order of the first and second lines).
By reading out the imaging signal written in the storage means of
The time is compressed to one horizontal scanning time of the progressive scanning system.
Odd and even lines with the phase relationship before decompression
Is output. And a second signal switching circuit
Are switched every horizontal scanning time of the sequential scanning system, and the first
Storage means during read operation of the second storage means and the second storage means
Is output from the second signal switching circuit.
Video signal that has been time-compressed and line-combined into one system
Is obtained, and the time-compressed and line-synthesized video signal is
Output from output means. Next, operation as a vertical contour emphasizing signal generating circuit will be described.
Explain the work. First signal switching circuit to first storage means
And outputs the first signal from the second signal switching circuit.
By outputting the output signal from the storage means,
First imaging signal (0H delay signal) input to the input means
Is delayed by one horizontal scanning time (1H) in the first storage means.
Obtaining a 1H delay signal and storing the 1H delay signal in a second storage means
Is further delayed by one horizontal scan time, for a total of two horizontal scan times
(2H) Obtain a delayed 2H delay signal. The 0H delay signal
Signal, the 1H delay signal and the 2H delay signal
Adder and signal cutoff included in vertical contour enhancement signal creation circuit
To create a vertical contour emphasis signal
At the same time, the 1H delay signal is output from the output means. [0018] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
I will explain it. FIG. 1 shows the time pressure in the first embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a compression / line synthesis circuit. In FIG. 1, a memory control circuit 7 is shown.
No, vertical contour strength as time compression / line synthesis circuit
Operation switching signal for switching the operation as the tone signal creation circuit
Write to memories 1, 2, 3, 4, 5, and 6 accordingly.
And a control signal for controlling the read operation. The selectors 13, 14, 15, 16, 17,
Reference numeral 18 designates two input signals according to the operation switching signal.
Select and output. The memory 1 stores the signal input to the input terminal 61.
The signal is delayed and output. The selector 13 has an input terminal 62
Of the signal input to the
Outputs flicker. Memory 4 is output from selector 13
The delayed signal is output. Selector 16 is a memo
Signal output from memory 1 and memory 4
One of the signals is output to the output terminal 67. The memory 2 stores the signal input to the input terminal 63.
The signal is delayed and output. The selector 14 has an input terminal 64
Of the signal input to the
Outputs flicker. Memory 5 is output from selector 14
The delayed signal is output. Selector 17 is a memo
Signal output from memory 2 and output from memory 5
One of the signals is output to the output terminal 68. The adder 8 outputs the signal input to the input terminal 61.
And the signal input to the input terminal 62 are added. Adder 9
Is the signal output from memory 1 and the output from memory 2
The added signals are added. Adder 10 exits memory 4.
The input signal and the signal output from the memory 5 are added.
You. The adder 11 includes a signal output from the adder 8 and the adder
10 are added to the output terminal 69 and the cell.
Output to the collector 12. The selector 12 selects a vertical LPF (not shown).
The signal output from the adder 8 according to the signal, the adder 9
, The signal output from the adder 10 and the like.
One of the signals output from the adder 11 and the output terminal
Output to the child 70. The memory 3 stores the signal input to the input terminal 65.
The signal is delayed and output. The selector 15 has an input terminal 66
Of the signal input to the memory and the signal output from the memory-3
Outputs flicker. Memory 6 outputs from selector 15
The delayed signal is output. Selector 18 is a memo
Signal output from memory 3 and output from memory 6
One of the signals is output to the output terminal 71. Hereinafter, a time compression / line synthesis circuit will be described.
The operation will be described. Odd lines (1, 3, 5, ...
) And even lines (2, 4, 6, ... line)
Line is divided into a series of
R, G, B imaging signals time-expanded during one horizontal scanning time
, An R line imaging signal of an odd line is input to an input terminal 61,
G imaging signal to input terminal 63, B imaging signal to input terminal 6
5 and input the R image signal of the even line to the input terminal.
62, a G imaging signal to an input terminal 64, and a B imaging signal to an input terminal 64.
To the force terminals 66 respectively. Odd line R, G, B
The imaging signal is input to memories 1, 2, and 3, and the even lines
R, G, and B imaging signals are input to selectors 13, 14, and 15.
Is forced. The selectors 13, 14, and 15 output the operation switching signal
Therefore, R, G, and B image signals of even lines are output.
, The R, G, B image signals of the even lines are
Input to the memories 4, 5 and 6. Memory 1, 2, 3
And memories 4, 5, and 6 write the input signal at the same time.
Start at time and write at interlaced pixel frequency
I do. And memory 1, 2, 3 is from the start of writing
Readout starts one horizontal scanning time later in the progressive scanning system,
One horizontal scanning time in sequential scanning system at twice the frequency of writing
And read it out. Write to memory 4, 5, 6
Read out after two horizontal scanning times of the sequential scanning system from the start
Start and sequentially scan the horizontal system at twice the frequency of writing
Reading is performed over a scanning time. Output from memory 1
R imaging signal of odd line and output from memory 4
The R image signal of the even line is supplied to the selector 16 by the memory
G imaging signal of odd line output from 2 and memory 5
The G image signal of the even line output from the
And the B image pickup signal of the odd line output from the memory 3
And the B image signal signal of the even line output from the memory 6.
, Respectively. Selector 16, select
The reader 17 and the selector 18 are performing a read operation
Operation switching signal to output the memory output signal
Therefore, the imaging signal of the odd line and the imaging signal of the even line are controlled.
The image signal sequence is line synthesized, and the time
If the compressed and line-combined R image signal is
The time-compressed and line-combined G image signal is output to an output terminal
The time-compressed and line-combined B image signal from
Each is output. Note that the adders 8, 9, 10, 11 and
The selector 12 operates as a time compression / line synthesis circuit
Has nothing to do with. Next, a vertical contour emphasizing signal generating circuit
The operation will be described. R, G, B
The R signal to the input terminal 61 and the G signal to the input terminal 63
To the input terminal 65. 3 systems
The imaging signal takes one horizontal scanning time by the memory 1, 2, 3.
(1H) Delayed and input to selectors 13, 14, and 15
It is. The selectors 13, 14, 15 are operated by the operation switching signal.
Output the signals output from the memories 1, 2, and 3.
Control is performed as described above, the three systems of imaging signals are stored in the memory 4,
Delayed by 1H by 5 and 6 for a total of 2 horizontal scans
The output is delayed for a period (2H). Also, memory 1,
1H delayed R, G, B imaging output from 2, 3
The signal is sent from the memory 1, 2, 3 by the operation switching signal.
Selector 1 controlled to output the output signal
Output terminals 67, 68, 71 via 6, 17, 18
Output from The signals input to the input terminals 61 and 63 are
And undelayed (0H delay) R and G imaging signals
Are added by the adder 8 and the 0H-delayed high-frequency luminance signal
Is given to the adder 11. Memory 1 and memo
1H delayed R and G captures output from
The image signal is added by the adder 9, and the 1H delay high band luminance
The signal is supplied to the selector 12 as a signal. And memory
4 and 2H delayed R output from memory 5
And the G image signal are added by the adder 10 to obtain 2H
Adder 11 and selector 12 as a delayed high-frequency luminance signal
Given to. 0H delay high band luminance signal and 2H delay height
The area luminance signal is added by the adder 11, and the vertical BPF
The signal is supplied to the selector 12 as a creation signal and the output terminal
It is output from the child 69. In the selector 12, the vertical BPF
Creation signal, 0H delay high-range luminance signal, 1H delay high-range luminance
Signal, one of the 2H-delayed high-range luminance signals is vertical
The signal for vertical LPF creation is selected according to the LPF selection signal.
The signal is output from the output terminal 70 as a signal. As described above, according to the first embodiment of the present invention,
Memory of vertical contour enhancement signal generation circuit of progressive scanning imaging device
Selector and memory using memory and peripheral circuits
By providing a control circuit, the conventional vertical contour enhancement signal
Time compression / line synthesis circuit that can also be used as a creation circuit
Can be realized. FIG. 2 shows the time pressure in the second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a compression / line synthesis circuit. In FIG. 2, a memory control circuit 7 is shown.
No, the effective number of pixels in one line exceeds the number of pixels in the memory
Time compression and line synthesis circuit
Operation When the number of effective pixels in one line is within the number of pixels in the memory
As a time compression / line synthesis circuit for an image signal
Operation and the conventional vertical contour enhancement signal creation circuit
According to the operation switching signal for switching the operation, the memory 1,
2, 3, 4, 5, and 6 control write and read operations.
Control signal to be controlled. The selectors 13, 14, 15, 16, 17,
Reference numerals 18 and 23 designate two input signals in response to the operation switching signal.
Select one of the numbers and output. The inter-pixel division circuits 19 and 20 are used to switch the operation.
According to the signal, the odd-numbered pixels (1,
3rd, 5th, etc. pixels) or output
The captured image signal is output as it is. Inter-pixel division circuit 2
Reference numerals 1 and 22 denote input imaging according to the operation switching signal.
Outputs only the even pixels (2, 4, 6,...) Of the signal
Or output the input image signal as it is.
You. The inter-pixel division circuit 19 is input to an input terminal 61.
Output or input only the odd-numbered pixels of the
The input imaging signal is output as it is. Pixel division circuit 2
0 is only the odd-numbered pixels of the imaging signal input to the input terminal 62
Or output the input image signal as it is.
Power. The pixel division circuit 21 is input to the input terminal 63
Outputs or inputs only the even pixels of the imaging signal.
The captured image signal is output as it is. The pixel dividing circuit 22 is turned on.
Only the even pixels of the image signal input to the input terminal 64 are output
Or output the input image signal as it is.
You. The memory-1 is output from the pixel dividing circuit 19.
And outputs the delayed signal. The selector 13 corresponds to the pixel
The signal output from the dividing circuit 20 and the signal output from the memory 1
Output one of the signals. Memory 4 is a selector
13 is output with a delay. SEREC
Is the signal output from memory 1 and memory 4
One of the signals output from the
Output to the The memory-2 is output from the pixel dividing circuit 21.
And outputs the delayed signal. The selector 14 is provided for each pixel.
The signal output from the splitting circuit 22 and the signal output from the memory 2
Output one of the signals. Memory 5 is a selector
14 is output with a delay. SEREC
17 is the signal output from the memory 2 and the memory 5
One of the signals output from the
Output to the The selector 23 outputs from the selector 16
Between the output signal and the signal output from the selector 17
Output to the output terminal 67. The adder 8 is output from the pixel dividing circuit 19
The signal output from the pixel dividing circuit 21
You. The adder 9 stores the signal output from the memory 1 and the memory
-2 are added together. Adder 10 is a note
Signal output from memory 4 and output from memory-5.
Add the signals. The adder 11 is output from the adder 8
A signal and a signal output from the adder 10 are added and an output terminal
69 and the selector 12. The selector 12 selects a vertical LPF (not shown).
The signal output from the adder 8 according to the signal, the adder 9
, The signal output from the adder 10 and the like.
One of the signals output from the adder 11 and the output terminal
Output to the child 70. The memory 3 stores the signal input to the input terminal 65.
The signal is delayed and output. The selector 15 has an input terminal 66
Of the signal input to the
Outputs flicker. Memory 6 outputs from selector 15
The delayed signal is output. Selector 18 is a memo
Signal output from memory 3 and output from memory 6
One of the signals is output to the output terminal 71. Hereinafter, the number of effective pixels in one line is
Time compression and line synthesis times for image signals exceeding prime numbers
The operation as a road will be described. Odd line and even la
Line is divided into two signal series
Imaging signal time-expanded during one horizontal scan time of the in-scan system
, The odd-numbered imaging signal is supplied to the input terminal 61 and
An even line imaging signal is input to the input terminal 63.
And input terminal 64 respectively. Pixel division circuit 1
9 and the pixel division circuit 20 are input by an operation switching signal.
Is controlled to output only the odd pixels of the
And the odd-numbered line imaging signal input to the input terminal 61
And the imaging signal of the even line input to the input terminal 62 is
Odd number by the pixel division circuit 19 and the pixel division circuit 20
It becomes a signal of pixel only and is stored in memory 1 and memory 2.
Write at half the interlace pixel frequency
Be included. The pixel dividing circuit 21 and the pixel dividing circuit 2
2 is an even image of the imaging signal input by the operation switching signal
Controlled to output only element, input to input terminal 63
Input to the odd-numbered line imaging signal and the input terminal 64
The obtained imaging signal of the even line is
The pixel dividing circuit 22 generates a signal of only even-numbered pixels,
Through the selector 13 and the selector 14, the memory 4 and the
And the memory 5 has 1/1 of the interlaced pixel frequency.
Written at a frequency of 2. Memory 1, 2 and memory
3 and 4 start writing at the same time. And odd lines
And the phase relationship between the imaging signals of the even lines before the time expansion (1,
(2, 3, ... line order)
And the memory 2 is one horizontal scanning system from the start of writing.
Starts reading with a delay of scanning time, twice as long as writing
The reading is performed in the sequential scanning system at the frequency over one horizontal scanning time.
Memory 4 and memory 5
Starts reading after a delay of two horizontal scanning times of the next scanning system, and
Is the horizontal scanning time for the sequential scanning system at twice the frequency of the scanning
And read. Selector 16 and selector 17
Indicates the output signal of the memory that is performing the read operation.
It is controlled by the operation switching signal to output
Odd-numbered pixel imaging signal of odd-numbered line output from memory 1
And odd-numbered pixels of even-numbered lines output from memory 4
The image signal is line-synthesized by the selector 16 and
Given to the selector 23 as an odd pixel image pickup signal,
In addition, odd-numbered pixels output from memory 2
Image signal and even picture of even line output from memory 5
The elementary imaging signals are line-synthesized by the selector 17 and
Given to the selector 23 as an even pixel image pickup signal of the system
You. The selector 23 operates in the sequential scanning system in accordance with the operation switching signal.
Control so that the input signal is switched and output at the pixel frequency.
Therefore, the odd pixel imaging signal and the even pixel imaging signal are
For one system of imaging signals (in order of 1, 2, 3,... Pixel),
The pixels are combined and output from the output terminal 67. Thus, the number of effective pixels in one line is
For two types of imaging signals exceeding the number of pixels in the memory
In addition, each imaging signal is further divided into two systems of odd-numbered pixels and even-numbered pixels.
By dividing into signal series and processing and combining pixels,
Time compression and line synthesis can be performed. It is to be noted that the image pickup signal is divided into n series of signals by pixels.
By dividing and processing, n times the number of memory pixels
It can be said that it can support image signals with the number of horizontal effective pixels.
Needless to say. Next, the number of effective pixels in one line is
Time compression and rasterization when handling image signals within the number of pixels
In-synthesis circuit and conventional vertical contour enhancement signal creation circuit
This operation will be described. When performing the above operations,
Pixel thinning circuits 19, 20, 21, and 22 convert input signals into
It is controlled by the operation switching signal to output as it is.
You. The selector 23 is always output from the selector 16.
Is controlled by the operation switching signal to output the
You. The operation of other circuits is the same as in the first embodiment. As described above, according to the second embodiment of the present invention,
Memory of vertical contour enhancement signal generation circuit of progressive scanning imaging device
Pixel division circuit and selector
And one line by providing a memory control circuit
Image signals whose effective pixel count exceeds the memory pixel count
A compliant time compression / line synthesis circuit can be realized. [0047] According to the present invention, the time compression / line combination
According to the configuration circuit, the conventional vertical contour enhancement signal generation circuit
Selector and memo using memory and peripheral circuits
LSI control without special development
Achieving a low cost and compact conventional vertical
Time compression / ramp that can also be used as a contour emphasis signal creation circuit
An in-synthesis circuit can be provided. Further, the image signal for one system is divided into pixels.
A pixel dividing circuit and image pickup signals of two systems divided into pixels are displayed.
By adding a selector for elementary synthesis, one line
It can also handle imaging signals where the effective pixel count exceeds the memory pixel count.
Inexpensive and compact time compression and line synthesis
Roads can be provided. [0049]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a time compression / line synthesis circuit according to a first embodiment of the present invention. FIG. 2 is a time compression / line synthesis according to a second embodiment of the present invention. FIG. 3 is a block diagram illustrating a configuration of a conventional image pickup apparatus. FIG. 4 is a block diagram illustrating a configuration of a conventional time compression / line combining circuit and a timing chart thereof. FIG. Block diagram showing the configuration of the contour emphasis signal creation circuit [Description of reference numerals] 1, 2, 3, 4, 5, 6 Memory 7 Memory control circuit 8, 9, 10, 11 Adders 12, 13, 14, 15, 16 , 17, 18 selectors 19, 20, 21, 22 pixel dividing circuit 23 selectors 61, 62, 63, 64, 65, 66 input terminals 67, 68, 69, 70, 71 output terminals

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-296283 (JP, A) JP-A-4-227392 (JP, A) JP-A-6-90466 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H04N ^7/ 00-7/01 H04N 5/262-5/278

Claims (1)

(57) [Claim 1] A red imaging signal obtained from an imaging device is
In order to delay the horizontal scanning time, the red
First storage means for storing an image signal, the first storage means
In order to further delay the output signal of
A second storage means for storing the output signals for the lines,
One horizontal scanning time for the green image signal obtained from the image sensor
Storing the imaging signal for one line to delay
A third storage means for further outputting an output signal of the third storage means;
Output for one line to delay one horizontal scan time
Fourth storage means for storing the force signal, before being delayed
The red image signal and the green image signal that is not delayed
Adder, which adds the output signal of the first storage means.
The red imaging signal delayed by one horizontal scanning time
One horizontal scanning time delay which is an output signal of the third storage means.
A second adder for adding the obtained green imaging signal and
The second horizontal scanning time delay which is the output signal of the second storage means
The obtained red image signal and the output signal of the fourth storage means.
Add a green image signal delayed by two horizontal scanning times
A third adder, wherein the first, second and third adders are provided.
Signal generation for the vertical contour emphasis circuit that generates the output signal of the arithmetic unit
Circuit for thinning out even-numbered pixels of an odd-numbered line of an imaging signal
Pixel thinning means, output signal of the first pixel thinning means
The first storage means for storing an even number of the imaging signal.
Second pixel thinning means for thinning even-numbered pixels of IN,
The output signal of the first storage unit and the second pixel thinning-out
And an output signal of the second pixel thinning means.
A first signal switching means for selecting an output signal of the first
The second storage means for storing an output signal of the signal switching means.
Stage, the output signal of the first storage means and the second storage means
And a second signal for selecting one of
Signal switching means, between odd pixels of even lines of the imaging signal
Third pixel thinning means for performing thinning, the third pixel thinning means
The third storage means for storing an output signal of the
Fourth thinning out of odd pixels of even lines of an imaging signal
A pixel thinning means, an output signal of the third storage means,
The output signal of the fourth pixel thinning means is input and the fourth
Signal switching for selecting the output signal of the pixel thinning means
Before storing the output signal of the third signal switching means.
The fourth storage means, the output signal of the third storage means and the
The output signal of the fourth storage means is input and any one is selected.
Fourth signal switching means for selecting and the second signal switching
And an output signal of the fourth signal switching means.
Provided with fifth signal switching means for selecting any one of
The second signal switching means captures an odd-numbered pixel of an odd-numbered line.
The image signal and the image signal of the odd-numbered pixel of the even-numbered line are converted into an odd number
A line is synthesized as a pixel imaging signal, and the fourth signal is switched.
The means is an even pixel imaging signal of an odd line and an even pixel of an even line.
The several-pixel imaging signal is written as one system of even-pixel imaging signals.
And synthesizing the signal, and the fifth signal switching means outputs the odd number of the one system.
The pixel imaging signal and the one-system even-numbered pixel imaging signal are combined into one system.
Compression / line synthesis circuit for synthesizing a pixel image signal
The vertical contour enhancement circuit signal generation circuit and the time compression and
The first, second, third and fourth
Select one of the circuits by sharing the storage means.
A signal for a vertical contour enhancement circuit characterized by being selectively used.
Signal generation circuit and time compression / line synthesis circuit.