JP3447489B2 - Power amplifier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier device, and more particularly to an integrated power amplifier device.

[0002]

2. Description of the Related Art A typical circuit of an integrated power amplifier device is shown in FIG. Transistors Q1 and Q2 are input differential amplifiers, and transistors Q3 and Q4 are transistor Q.
It is a current mirror circuit which becomes an active load of the differential amplifier of Q1 and Q2. The transistor Q5 is a pre-driver transistor, the diodes Q6 and Q7 are bias voltage generating transistors, the transistors Q8 and Q9 are driver stage transistors, and the transistors Q11 and Q13 are output power transistors. The resistors R4 and R5 are resistors for overdriving, and have a function of enhancing the driving ability at the time of a large current. Also, capacitors C1 and COSC
Is a capacitor for stopping oscillation, capacitors CIN, COU
T is a coupling capacitor for DC cut.

The signal input to the IN terminal is amplified by the differential amplifier of the active load load of the transistors Q1 to Q4 and taken out in the form of current, which is the transistor Q.
5 times hFE. The upper half cycle of this current signal is further multiplied by hFE by the transistor Q8, folded back by the current mirror with overdrive of the transistors Q10 and Q11, and output at the collector of the transistor Q11.

The lower half cycle is multiplied by hFE by the transistor Q9, folded back by the current mirror with overdrive of the transistors Q12 and Q13, and output at the collector of the transistor Q13. This causes the signal applied to the input to be amplified and appear at the output.

[0005]

Usually, a load is connected to the OUT terminal of FIG. However, when the load is not connected, the waveform when the sine wave is applied to the input and the output is clipped becomes as shown in FIG. 7A.

In other words, after the upper clip, it does not return immediately and it sticks to the upper side for a while,
When returning from there, this time it becomes a waveform with a thorn on the lower side due to an operation such as overshoot (the part (A) in the figure).

Similarly, when the clip on the lower side does not return immediately, it sticks to the lower side for a while,
When returning from there, the waveform becomes like a thorn on the upper side ((B) in the figure).

These are phenomena that do not occur when a load is connected, but even if there is no load, it is a very undesirable phenomenon to have a waveform, which causes unnecessary radiation.

In order to prevent this, for example, the resistors R4 and R5 are reduced in order to reduce the overdrive capability, or the current source I is reduced in order to reduce the overall open loop gain.
If 1 is reduced, the waveform becomes dirty, but at the same time, the ability to drive the load decreases and the amount of feedback decreases, so there is a problem that the maximum output decreases and distortion increases. there were.

Therefore, an object of the present invention is to provide a power amplification device which prevents the phenomenon that the waveform becomes dirty at the time of no-load clipping without causing a decrease in output and an increase in distortion when a load is connected. .

[0011]

An amplifying means having a control terminal capable of externally controlling the ability to drive a subsequent stage, and an output means having an input terminal connected to an output terminal of the amplifying means,
A power amplification device comprising: a clip detection unit having an input terminal connected to an output terminal of the output unit and an output terminal connected to a control terminal of the amplification unit.
If a load is connected to the output terminal of the
The clip detection means does not detect it when
If a load is not connected to the output terminal of the output means,
When the output clips, the clip detection means
It is characterized in that the driving capability of the amplifying means is detected and reduced.

[0012]

FIG. 1 shows a most basic block diagram of an embodiment of a power amplifying device of the present invention. 1 is an amplifier circuit having a control terminal capable of externally controlling the ability to drive the latter stage, 3 is an output stage circuit having an input terminal connected to the output terminal of the amplifier circuit, and 5 is an input terminal to the output terminal of the output stage circuit. Is connected, and the output terminal is connected to the control terminal of the amplifier circuit 1.

The signal inputted from the IN terminal is amplified by the amplifier circuit 1.
Is amplified by the output stage circuit 3 and then appears at the OUT terminal. When the OUT terminal, that is, the output of the output stage circuit 3 is clipped when there is no load, the clip detection circuit 5 detects it and drives the amplifier circuit 1. The ability is reduced and driving is not performed more than necessary.

For this reason, when the output of the output stage circuit 3 is clipped, the driving capability is lowered, so that the output stage circuit 3 enters into saturation weakly, and thus it takes time to exit saturation. Prevents the waveform from becoming dirty when no load is applied.

2 to 5 are circuit diagrams in which the configuration of FIG. 1 is described in more detail. Similar to the case of FIG. 1, in any of FIGS. 2 to 5, 1 is an amplifier circuit having a control terminal capable of externally controlling the ability to drive the subsequent stage, and 3 is an input terminal connected to the output terminal of the amplifier circuit. An output stage circuit 5 is a clip detection circuit in which an input terminal is connected to the output terminal of the output stage circuit and an output terminal is connected to the control terminal of the amplifier circuit 1. In FIG. 2, the output stage circuit 3 is a collector output type SEPP output circuit of the PNP transistor 7 to the NPN transistor 9, and the clip detection circuit 5 is composed of only one transistor. However, in this figure, the clip detection circuit 5 detects only the lower clip and does not particularly detect the upper clip. However, when upper clip detection is also required, the transistor whose polarity is inverted from that of the transistor 11 is used. Connect to.

In FIG. 2, when the OUT terminal voltage is clipped to the lower side when the load is not connected to the OUT terminal and there is no load, the emitter potential of the transistor 11 becomes the transistor 9
Since it is equal to the base potential of VBE (ON),
On the other hand, the base potential is almost GND (VCE (sat) of the transistor 9 is several tens of mV), so that the transistor 11 is turned on and it is detected that the transistor 9 has reached saturation.

This returns to the amplifier circuit 1 to lower the driving capability of the amplifier circuit 1 to reduce the base current of the transistor 9 and weaken the entry into saturation of the transistor 9. As a result, the abnormal waveform as shown in FIGS. 7A and 7B does not occur, and the waveform as shown in FIG. 7B can be obtained.

When a load is connected, the VCE (sat) of the transistor 9 becomes large (several hundreds of mV or more), VBE enough to turn on the transistor 11 does not occur, and the transistor 11 does not turn on. Therefore, the clip detection circuit 5 operates only when there is no load, and when the load is connected, the clip detection circuit 5 does not operate even if the output is clipped, and does not affect the circuit operation.

Although FIG. 2 shows an example using a bipolar transistor, an example using a MOS FET is shown in FIG. The output stage circuit 3 is SE by Nch MOS FET.
It is a PP output circuit, and the clip detection circuit 5 is simply one MOS FET.

In FIG. 3, when the OUT terminal voltage is clipped to the lower side when the load is not connected to the OUT terminal and the load is not applied, the source potential of the MOS FET 25 becomes MOS FET.
Since it is equal to the gate potential of 23, VGS (ON) is output, while the gate potential of MOS FET 25 is almost G
Since it becomes ND (VDS (ON) is about tens of mV), M
The OS FET 25 is turned on and detects that the MOS FET 23 has entered saturation.

This returns to the amplifier circuit 1 to reduce the drive capability of the amplifier circuit 1 to reduce the gate drive voltage of the MOS FET 23 and weaken the entry into saturation of the MOS FET 23. As a result, (A) and (B) of FIG.
The abnormal waveform as shown in FIG. 7 does not occur, and the waveform as shown in FIG. 7B can be obtained.

When a load is connected, MOS F
The VDS (ON) of the ET23 becomes large (several hundreds of mV or more), VGS enough to turn on the MOS FET 25 does not occur, and the MOS FET 25 does not turn on. Therefore, the clip detection circuit 5 operates only when there is no load, and when the load is connected, the clip detection circuit 5 does not operate even if the output is clipped, and does not affect the circuit operation.

In the case of a MOS FET, VGS (ON) may differ depending on the element size.
A level shift circuit such as a diode may be used in series with the source of the S FET 25.

In FIG. 4, the polarities of the transistors forming the clip detection circuit 5 are changed. When clipped on the lower side with no load, the base potential of the transistor 13 is equal to the base potential VBE (ON) of the transistor 9, while the emitter potential of the transistor 13 is almost GND.
Since it becomes a potential (VCE (sat) of transistor 9)
Is several tens of mV), and the transistor 13 is turned on to detect that the transistor 9 has reached saturation. This returns to the amplifier circuit 1 and brings about the same effect as in the case of FIG.

If upper clip detection is also required, a transistor having the polarity of the transistor 13 inverted may be connected to the transistor 7.

When FIG. 4 is replaced with the case where a MOS FET is used, the result is as shown in FIG. If the lower side is clipped with no load, the gate potential of MOS FET 27 is MOS FE.
Although it is equal to the gate potential of T23, MOS FE
Since the source potential of T27 is almost the GND potential (VDS (ON) is about tens of mV), MOS FET2
7 turns on and detects that the MOS FET 23 has entered saturation. This returns to the amplifier circuit 1 and brings about the same effect as in the case of FIG.

FIG. 6 shows a specific circuit example of FIG. Since this corresponds to FIG. 10 shown in the conventional example, the same circuit elements are designated by the same reference numerals, and detailed description thereof will be omitted. 1 surrounded by a dotted line corresponds to the amplifier circuit 1 of FIG.
Corresponds to the output stage circuit 3, and 5 corresponds to the clip detection circuit 5.

Although only the lower clip is detected in FIGS. 2 and 4, both upper and lower clips are detected in FIG. 6, and the lower detection is the same as the clip detection of FIG. For the upper side detection, the clip detection form of FIG. 4 is adopted. That is, the transistor Q15
2 corresponds to the transistor 11, and the transistor Q14 corresponds to the transistor 13 in FIG. However, with regard to the transistor Q14, while the lower side detection is performed in FIG. 4, the transistor Q14 performs the upper side detection.
The polarity is opposite to 3.

Now, it is assumed that the outputs (collectors of the transistors Q11 and Q13) are clipped to the lower side under no load condition. At this time, the transistor Q13 is on and the transistor Q11 is off.
Since 3 is on, the emitter potential of the transistor Q15 is VBE (ON).

On the other hand, since the base of the transistor Q15 is connected to the output, the potential thereof is almost GND (VCE (sat) of the transistor Q13 is about several tens of mV). Therefore, the transistor Q15 is turned on,
Then, the collector current of the transistor Q15 flows through the resistor R3. Then, the emitter potential of the transistor Q4 rises. Then, the base potential of the transistor Q4 rises. Then, the collector current of the transistor Q3 increases. Then, the base current of transistor Q5 decreases. Then, the collector current of the transistor Q5 decreases. Then, the base current of the transistor Q9 decreases.
And the collector current of the transistor Q9 decreases,
Since the base current of the transistor Q13 is reduced by this, the way of entering the saturation of the transistor Q13 becomes weak.

On the other hand, when the upper side is clipped, the transistor Q11 is ON and the transistor Q13 is OFF, but since the transistor Q11 is ON, the base potential of the transistor Q14 is from Vcc to VBE (ON).
The potential is only lowered.

On the other hand, since the emitter of the transistor Q14 is connected to the output, its potential is almost Vcc (VCE (sat) of the transistor Q11 is several tens of mV), and therefore the transistor Q14 is turned on.
Then, the collector current of the transistor Q14 flows through the resistor R2. Then, the emitter potential of the transistor Q3 rises. Then, the collector current of the transistor Q3 decreases. Then, the base current of the transistor Q5 increases. Then, the collector current of the transistor Q5 increases. Then, the base current of the transistor Q8 decreases.
And the collector current of the transistor Q8 decreases,
As a result, the base current of the transistor Q11 is reduced, so that the saturation of the transistor Q11 is weakened.

As a result of the above operation, when the output enters the clip with no load on both the lower clip and the upper clip, the clip detection circuit operates, and it becomes weak to put the output transistor in saturation. The time to get out of saturation is shortened, and as a result, the conventional circuit shown in FIG.
Instead of the waveform as shown in FIG. 7A, the waveform as shown in FIG.

When a load is connected to the output, the VCE (sa) of the transistors Q11 and Q13 is
Since t) is generated for several hundred mV or more and the transistors Q14 and Q15 are not turned on, there is no influence on the maximum output and distortion when the load is connected.

FIG. 8 shows another specific example. A big difference from FIG. 6 is the circuit configuration of the output stage circuit 3 and the connection destination of the output of the clip detection circuit 5. The output stage circuit 3 is a very general one which has been widely used in the past, and the output transistor is an NPN-NPN SEPP output circuit.

In this case, even if the output (the connection point between the emitter of the transistor Q14 and the collector of the transistor Q15) is clipped, the transistor Q14 does not enter saturation (the transistor forming the current source of I2 enters saturation first). ), So upper clip detection is not performed. The lower clip detection adopts the shape shown in FIG. The output of the clip detection circuit 5 is connected to the inverting input (base of the transistor Q2) of the input differential amplifier (transistors Q1 and Q2). Resistor R9 is transistor Q16
This is the current limiting resistance when is turned on.

The collector of the transistor Q16 is not connected to the base of the transistor Q2, but the current is folded back by a current mirror circuit (not shown), and the non-inverting input (transistor Q1) of the input differential amplifier (transistors Q1 and Q2). Base).

When the output is clipped to the bottom without load and the transistor Q16 is turned on, a collector current flows through the transistor Q16 and the base potential of the transistor Q2 is lowered. Then, the collector current of the transistor Q2 increases. Then, the collector current of the transistor Q3 increases. Then, the base current of the transistor Q5 decreases.
Then, the emitter current of the transistor Q5 decreases. Then, the collector current of the transistor Q6 decreases. Then, the base current of the transistor Q13 decreases. Then, the operation is such that the collector current of the transistor Q13 decreases, which reduces the base current of the transistor Q15 and weakens the saturation of the transistor Q15.

The effect produced by this is similar to the above.

FIG. 9 shows another specific example. The difference is that the overall feedback of the entire amplifier device circuit is different from before, and the input differential amplifier (transistor Q
It is in the form of returning to the emitter instead of the base of (2, Q3). Regarding the clip detection circuit 5, this time, the shape of FIG. 4 is adopted for both the lower side and the upper side.

When the output is clipped to the lower side with no load and the transistor Q15 is turned on, a collector current flows through the transistor Q15 and the emitter potential of the transistor Q3 is lowered. Then, the collector current of the transistor Q3 decreases. Then, the base current of the transistor Q7 decreases. Then, the collector current of the transistor Q7 decreases. Then, the base current of the transistor Q11 decreases. Then, the collector current of the transistor Q11 decreases, which causes the transistor Q1
The base current of No. 3 decreases, and the transistor Q13 enters the saturation mode weakly. On the other hand, when the output is clipped to the upper side, the transistor Q14 is turned on, the collector current of the transistor Q14 flows, and the transistor Q3
The emitter potential of is raised. Then, the collector current of the transistor Q3 increases. And transistor Q
7 base current increases. Then, the collector current of the transistor Q7 increases. Then, the base current of the transistor Q10 decreases. Then, the operation is such that the collector current of the transistor Q10 decreases, which reduces the base current of the upper output transistor Q12 and weakens the saturation of the transistor Q12.

[0042]

As described above , according to the present invention.
For example , the clip waveform under no load can be cleaned as shown in FIG. 7B without causing a decrease in maximum output and deterioration of distortion, and problems such as unnecessary radiation can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a power amplification device of the present invention.

FIG. 2 is a circuit diagram showing the configuration of FIG. 1 in a little more detail.

FIG. 3 is a circuit diagram showing the configuration of FIG. 1 in a little more detail.

FIG. 4 is a circuit diagram showing the configuration of FIG. 1 in a little more detail.

5 is a circuit diagram showing the configuration of FIG. 1 in a little more detail.

FIG. 6 is a specific circuit diagram of FIG.

FIG. 7 is a waveform diagram for explaining the operation of the related art and the present invention.

FIG. 8 is a specific circuit diagram of FIG.

9 is a specific circuit diagram of FIG. 1. FIG.

FIG. 10 is a circuit diagram of a conventional power amplification device.

[Explanation of symbols]

1 ... Amplifier circuit, 3 ... Output stage circuit, 5 ... Clip circuit, 7, 9, 11, 13 ... Transistor, 2
1, 23, 25, 27 ... MOS FET.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ka Wada 3-3-9 Shimbashi, Minato-ku, Tokyo, Toshiba Abu E. Co., Ltd. (56) Reference JP-A-1-226205 (JP, A) ) JP-A-3-136506 (JP, A) JP-A-8-279722 (JP, A) JP-A-59-79613 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03G 3/30 H03F 1/32

Claims (10)

(57) [Claims] 1. An amplifying means having a control terminal capable of externally controlling the ability to drive a subsequent stage, an output means having an input terminal connected to an output terminal of the amplifying means, and an input terminal connected to an output terminal of the output means. In a power amplification device, which is connected and has a clip detection means in which an output terminal is connected to a control terminal of the amplification means, in the case where a load is connected to the output terminal of the output means, even if the output is clipped. The clip detecting means does not detect it, and when the output is clipped when the load is not connected to the output terminal of the output means, the clip detecting means detects it and reduces the driving capability of the amplifying means. A power amplification device characterized by: 2. The output means includes a first active element in which a first controlled terminal is connected to the output terminal of the output means, and the clip detection means reverses the first active element. With polarity, the second controlled terminal is connected to the control terminal of the first active element, the control terminal is connected to the input terminal of the clip detecting means, and the first controlled terminal is the clip detecting means of the clip detecting means. The power amplification device according to claim 1, further comprising a second active element connected to the output terminal. 3. The output means includes a third active element in which a first controlled terminal is connected to the output terminal of the output means, and the clip detection means is the same as the third active element. With polarity, the control terminal is connected to the control terminal of the third active element, the second controlled terminal is connected to the input terminal of the clip detecting means, and the first controlled terminal is the clip detecting means of the clip detecting means. The power amplification device according to claim 1, further comprising a fourth active element connected to the output terminal. 4. The amplifying means includes a first differential amplifier having an input terminal connected to the input terminal of the amplifying means, and the control terminal of the amplifying means includes an inversion of the first differential amplifier. Alternatively, the power amplification device according to claim 1, wherein the power amplification device is a non-inverting input terminal. 5. The amplifying means includes a second differential amplifier having an input terminal connected to the input terminal of the amplifying means and having a common controlled terminal resistance, and the control terminal of the amplifying means includes the second differential amplifier. power amplifier according to claim 1, characterized in that the second controlled terminal of one of the active element pairs constituting a second differential amplifier. 6. The amplifying means includes a current mirror circuit having an input terminal connected to an output of a third differential amplifier whose input terminal is connected to the input terminal of the amplifying means, the current mirror circuit having a controlled terminal resistance. The power amplifying apparatus according to claim 1, wherein the control terminal of the means is a second controlled terminal of an active element forming the current mirror circuit. 7. The output means includes a first transistor whose collector is connected to the output terminal of the output means, and the clip detection means has a polarity opposite to that of the first transistor and an emitter of the first transistor. 2. A second transistor connected to the base of the transistor, the base of which is connected to the input terminal of the clip detecting means, and the collector of which is connected to the output terminal of the clip detecting means. The power amplification device according to. 8. The output means includes a third transistor having a collector connected to the output terminal of the output means, and the clip detection means has the same polarity as the third transistor and a base of the third transistor. 4. A fourth transistor connected to the base of the transistor, the emitter of which is connected to the input terminal of the clip detecting means, and the collector of which is connected to the output terminal of the clip detecting means. The power amplification device according to. Wherein said amplifying means has an input terminal connected to said input terminal of said amplifying means includes a fourth differential amplifier having a common emitter resistor, the control terminal of said amplifying means and the fourth The power amplification device according to claim 1, wherein the power amplification device is one of the emitters of a pair of transistors forming a differential amplifier. 10. The amplifying means includes a current mirror circuit having an emitter resistor connected to an output of a fifth differential amplifier whose input terminal is connected to the input terminal of the amplifying means. The power amplification device according to claim 1, wherein the control terminal is an emitter of a transistor forming the current mirror circuit.