JP3447553B2 - Semiconductor package - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package having a plurality of semiconductor chips inside the package.

[0002]

2. Description of the Related Art Generally, semiconductor elements are manufactured as chips from a silicon wafer and then used as electronic parts by packaging each chip with epoxy resin or the like. Integration has been promoted, and attempts have been made to reduce the size of the package itself and package a plurality of chips in one package.

FIG. 6 shows a stacked package which is one of conventional package structures. In this package, an upper chip 61 and a lower chip 62 are arranged vertically. The upper chip 61 and the lower chip 62 are connected to the device pins 64 from chip pads (input / output terminals) (not shown) by wire bonding 63. The entire structure is covered with a molding compound such as epoxy resin.

In the case of a package having such a structure, it is very difficult to test individual semiconductor chips.
For example, as a configuration example of a conventional stacked package,
In some cases, the upper chip is a microcomputer chip and the lower chip is a memory chip. In the above case, as a method of testing the individual semiconductor chips, the first semiconductor chip test is enabled by outputting all the device pins of the two semiconductor chips to the device pins of the semiconductor package. There is a test method.

In some cases, for example, one output terminal of the upper microcomputer chip and one input terminal of the lower memory chip are wire-bonded to a common device pin according to the system configuration specifications. In this case, packaging is performed. In the subsequent shipping test, only the basic operation of the entire system can be tested and individual chips cannot be tested. Therefore, in order to avoid this, there is a second test method that makes it possible to test by incorporating a complicated test circuit in each chip and separating each individually.

[0006]

However, in the first test method described above, all the input / output terminals of the semiconductor chip are output to the device pins of the package, which leads to an increase in the number of device pins provided in the package. Was becoming.

Further, in the second test method, it is possible to reduce the number of device pins and prevent deterioration of quality by adding a complicated test circuit, but various problems such as an increase in chip size occur. Was there.

Further, when the combination of the upper chip and the lower chip is a stacked package of memory chips, in order to collectively make the respective buffers of the respective chips inoperative, the configurations of all the buffers are changed. Although it is possible to test a semiconductor chip, this also causes a problem of increasing the chip size.

Further, in the conventional case where a test is performed on the entire system, it is necessary to perform all the test patterns for the system, and it is necessary to newly prepare an expected value, resulting in an increase in development cost and an increase in test cost. Was becoming.

The present invention has been made in order to solve the above-mentioned problems, and is a semiconductor package including a plurality of semiconductor chips, which can be manufactured individually without increasing the number of device pins or adding a complicated test circuit. It is an object of the present invention to provide a semiconductor package that enables the testing of the semiconductor chip.

[0011]

The present invention has the following constitution in order to achieve the above object. A first invention is a semiconductor package having two or more semiconductor chips connected to a common device pin, wherein conduction and non-conduction between the device pin and an internal circuit can be controlled based on a control signal applied to the device pin. Is a semiconductor package having a buffer section.

A second aspect of the present invention, common to a semiconductor package having two or more semiconductor chips to be connected to the device pins, conduction between the input and output terminals and the internal circuit based on a control signal applied to the device pins and non A disconnection circuit having a buffer capable of controlling conduction and a control signal holding unit connected to the test switch and the reset switch is provided between the input / output terminal and the internal circuit, and the test switch is turned ON, Turn off the reset switch to make one of the buffers conductive, turn off the test switch,
This is a semiconductor package in which all the buffers are turned on by turning on the reset switch.

A third invention, the second origination, characterized in that provided by stacking semiconductor chips having a built-in decoupling circuits
It is a semiconductor package according to Akira.

[0014] The fourth aspect of the present invention, first the reset switch
The semiconductor package according to the third aspect of the invention is characterized in that a semiconductor chip formed of a conductivity type transistor is stacked on one side and a reset switch is formed on a semiconductor chip formed of the second conductivity type transistor on the other side.

According to the first aspect of the invention, the semiconductor chip connected to the common device pin can be electrically disconnected based on the control signal. If there is a semiconductor chip that does not have a buffer between it and a common device pin or a semiconductor chip that has a buffer, it is possible to test only the semiconductor chip that does not have the buffer required for the test by making the buffer non-conductive. Become. When all the buffers are provided between the common device pin and the internal circuit, the buffer provided in the semiconductor chip to be tested is made conductive, and the other buffers are made non-conductive so that one semiconductor chip or two or more semiconductor chips are provided. It becomes possible to selectively test the semiconductor chips. Further, by making all the buffers provided in the semiconductor chip connected to the common device pin conductive, the semiconductor package can be operated normally.

As a result, each semiconductor chip connected to the common device pin inside the package is completely separated without incorporating a complicated test circuit in the semiconductor package into the semiconductor chip, and the performance of each individual semiconductor chip is confirmed and the failure point is detected. Tests such as discovery can be carried out. In the present invention, the test patterns and expected values used in the wafer test can be reused only by increasing the routine for initializing the external connection state of the input / output terminals. Further, at the end of the test, all the buffers can be turned on to perform the original operation, so that the test or the like can be easily performed.

According to the second aspect of the invention, since the disconnecting circuit is provided between the input / output terminal of the semiconductor chip connected to the common device pin and the internal circuit, each semiconductor chip connected to the common device pin is electrically connected. It is now possible to disconnect from the device pin. When the disconnection circuit is provided between the common device pin and each internal circuit, the test of the semiconductor chip not provided with the disconnection circuit can be individually performed by setting the buffer of the disconnection circuit to be non-conductive. If a disconnection circuit is provided between the common device pin and each internal circuit, make the buffers of the disconnection circuits provided in the semiconductor chip to be tested conductive and the buffers of other disconnection circuits nonconductive. so,
It is possible to selectively test one semiconductor chip or two or more semiconductor chips. Further, by making all the buffers of the disconnection circuit provided in the semiconductor chip connected to the common device pin conductive, the semiconductor package can operate normally.

Thus, without incorporating a complicated test circuit in the semiconductor package, the semiconductor chips inside the package can be completely separated and a test such as performance confirmation of each semiconductor chip and detection of a failure point can be performed. In the present invention, the test patterns and expected values used in the wafer test can be reused only by increasing the routine for initializing the external connection state of the input / output terminals. Further, at the end of the test, all the buffers can be turned on to perform the original operation, so that the test or the like can be easily performed.

According to the third invention, it is possible to effectively perform a performance test or the like on the stacked semiconductor chips for the purpose of downsizing.

According to the fourth aspect of the present invention, since the switching between the test state and the actual operating state of the disconnection circuit can be performed by a simple circuit using a common reset signal, the disconnection circuit can be constructed in a small space, and the limit is limited. It is possible to effectively use the internal circuit in the provided semiconductor chip space. Further, it is possible to minimize the increase in the number of terminals for the individual chip test in the stacked package.

[0021]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. (First Embodiment) FIG. 1 is a perspective view showing a part of the inside of a stacked package which is a semiconductor package according to the present invention.

The stacked package forms a semiconductor chip 2A having an internal circuit 1A, a disconnecting circuit 3A and a pad (input / output terminal) 4A, and similarly, an internal circuit 1B and a disconnecting circuit 3B and a pad (input / output terminal) 4B. Attach the semiconductor chip 2B to the bottom surface of the semiconductor chip (the surface opposite to the element formation surface).
And the common device pin 5 and each pad 4A, 4B are connected to the wire 8 by more wire bonding. Similarly, the common reset signal pin 6 and test signal pin 7 are also connected to the disconnecting circuits 3A, 3B. It is connected by a wire 8.

2 shows a circuit diagram of the disconnecting circuit 3A, and FIG. 3 shows a circuit diagram of the disconnecting circuit 3B. Detachment circuit 3 shown in FIG.
A includes a buffer 9A, a test signal switch 10, a latch circuit 12A, and a reset switch 13A.

As shown in FIG. 4, the buffer 9A has an output buffer 16A and an input buffer 17A which are activated when the signal line 12L connected to the latch circuit 12A is at a low level.
It consists of.

The test signal switch 10 is an Nch transistor having a gate terminal connected to the test signal terminal 11, a drain terminal connected to the pad 4A, and a source terminal connected to the latch circuit 12A. The test signal switch 10 functions as a switch controlled by a test signal from the test signal pin 7 input to the test signal terminal 11.

The latch circuit 12A is a circuit composed of two inverters as shown in FIG. 4, and holds a control signal. The latch circuit 12A holds the signal level of the signal line 12L, and is connected to the test switch 10, the buffer 9A, and a reset switch 13A described later.

The reset switch 13A is an Nch transistor. The gate terminal of the Nch transistor 10 is connected to the reset signal terminal 14, the drain terminal is grounded to the latch circuit 12A, and the source terminal is grounded. The reset switch 13A functions as a switch controlled by the reset signal from the reset signal pin 6 input to the reset signal terminal 14.

The disconnecting circuit 3B includes a buffer 9B, a test signal switch 10 and a latch circuit 1 as shown in FIG.
2B, a reset switch 13B, and an inverter 15. Since the test signal switch 10 is the same as the test signal switch 10 shown in the disconnection circuit 3A, its description is omitted. As shown in FIG. 5, the buffer 9B is composed of an output buffer 16B and an input buffer 17B which are in operation when the signal line 12L is at high level.

The reset switch 13B is a Pch transistor having a gate terminal connected to the output side of the inverter 15, a drain connected to a power source (not shown), and a source terminal connected to the latch circuit 12B. The reset switch 13B functions as a switch controlled by a reset signal from the inverter 15. The inverter 15 inverts the reset signal level from the reset signal terminal 14 connected to the reset signal pin 6 by the wire 8 and inputs it to the gate of the Pch transistor 13B. Therefore, when the reset signal is at a high level, it becomes a low level reset signal via the inverter 15, and the reset switch 13B which is a Pch transistor is turned on. On the contrary, when the reset signal is at a low level, the inverter is turned on. Since a high level is applied to the gate of the Pch transistor via 15, the reset switch 13B is turned off.

In the present embodiment, the output buffer 16
Although the input / output configurations of A and 16B and the input buffers 17A and 17B are used, the present invention can be applied to configurations of only the output buffers 16A and 16B.

(When Testing Semiconductor Chip 2A) Next, the operation when testing the semiconductor chip 2A will be described. When testing the semiconductor chip 2A, first, the reset signal RS input from the reset signal pin 6 to the reset terminal 14 is set to low level, the test signal TS input to the test terminal 11 from the test signal pin 7 is set to high level, Further, the signal DS input from the device pin 5 to the chip pad 4A and the chip pad 4B is input as a low level. At this time, chip pad 4A and chip pad 4B
The buffer 9A and the buffer 9B must be in an inoperative state in order to prevent a collision between the signal DS input from the buffer 9 and the output data of the buffers 9A and 9B.

By inputting the above signals, the test switch 10 is turned on, and the low level signal DS input to the chip pads 4A and 4B is held in the latch circuits 12A and 12B.

Next, the test switch 10 is turned off by shifting the test signal TS to the low level. Each of the latch circuits 12A and 12B is held at a low level, the output buffer 16A is turned on, the output buffer 16B is turned off, the semiconductor chip 2B is separated from the common device pin, and the individual tests of the semiconductor chip 2A are performed. It will be possible.

(When Testing Semiconductor Chip 2B) Next, the operation when testing the semiconductor chip 2B will be described. When testing the semiconductor chip 2B, first, the reset signal RS is set to the low level, the test signal TS is set to the high level, and the signal DS for the device pins is input to the high level. In order to prevent the signal DS from colliding with the output data of the buffers 9A and 9B, the buffers 9A and 9B
Must be inactive.

As a result, the test switch 10 is turned on, and the high level signal DS input to the chip pads 4A and 4B receives the latch circuits 12A and 12A.
Held in B.

Next, the test switch 10 is turned off by shifting the test signal TS to the low level. The latch circuits 12A and 12B are kept at a high level, the output buffer 16A is in an off state, the output buffer 16B is in an on state, and the chip 1A is separated from the common device pin 5, so that the chips 2A can be individually tested. .

(In Case of Actual Operation State, Not in Test of Each Chip) Next, a case of actual operation state in place of a test of each chip will be described. In the case of actual operation, first, the low-level test signal TS is input to the test signal pin 7. As a result, each test switch 10 is turned off.

Next, by inputting a high level reset signal RS to the reset signal pin 6, the reset switches 13A and 13B are turned on, the latch circuit 12A is at a low level, and the latch 12B is at a high level due to the power supply voltage. Holds the output buffer 16
Both A and the output buffer 16B are turned on. That is, it functions as the buffers 9A and 9B in the actual operation state.

(Second Embodiment) FIG. 6 is a partial perspective view of the inside of the stacked package when the semiconductor chip 2C in the stacked package is a microcomputer chip and the semiconductor chip 2D is a memory chip. The same components as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

4A is a microcomputer chip 2C
4A is a pad 4A for a memory read output signal, and 4B is a pad 4B for an output enable signal of the memory chip 2D. The two terminals 4A and 4B can be wire-bonded to the common device pin 5 in terms of system configuration specifications.

A pad 4E that is wire-bonded to a device pin 5B that is not common to external peripheral control signals and a pad 4F that is wire-bonded to the device pin 5C are provided.

Also in the second embodiment, the separation circuit 3A is provided between the microcomputer internal circuit 1C and the pad 4A, and the memory internal circuit 1D and the pad 4B are also provided.
By providing the disconnection circuit 3B between them, the test signal T
Depending on the state of S and the reset signal RS, the pad 4A of the microcomputer chip 2C and the pad 4B of the memory chip 2D which are wire-bonded to the common device pin 5 are electrically separated.

Therefore, the signal DS applied to the device pin 5 is
And the state of the reset signal RS applied to the reset signal pin 6 and the test signal TS applied to the test signal pin 7,
Microcomputer chip 2C and memory chip 2D
It was possible to easily switch to the actual use mode by organically associating both chips with the mode in which the tests such as the operation confirmation are individually performed.

Further, since the pads 4E and 4F individually have the device pins 5B and 5C, if it is not necessary to electrically disconnect them internally, the chips 1C and 1D, which are internal circuits, and the pads 4E, It is possible to provide a more efficient package of a semiconductor chip without providing a disconnection circuit between the 4Fs.

Although the preferred embodiment of the present invention has been described in the above embodiment, the present invention is not limited to this.

For example, in the above-described embodiment, the case where two chips are provided in the semiconductor package has been described, but a plurality of semiconductor chips of two or more are provided for testing in the disconnection circuit. A disconnection circuit with different thresholds of the transistor switch of the switch is provided, and the function of controlling the voltage level applied to the test signal to select the switching circuit is added to selectively select only one of the plurality of semiconductor chips. It is also possible to carry out tests, etc., and is included in the technical scope of the present invention.

With such a configuration, when a plurality of semiconductor chips can be included in the package due to miniaturization of the semiconductor chip, for example, a laminated chip having two or more layers or a plurality of internal circuits or semiconductor chips on the same plane. Even when arranging the chips, it is possible to appropriately test the function of each chip, which contributes to the improvement of reliability.

Further, the transistor which is a test switch which constitutes the disconnection circuit, the buffer which controls conduction and non-conduction, the latch circuit which holds the control signal, and the like are not limited, and may have any similar effects. .

[0049]

As described above, according to the first and second aspects of the invention, in a semiconductor package in which two or more chips are connected to a common device pin, without adding a complicated circuit, The individual semiconductor chips inside the package can be functionally completely separated. This makes it possible to utilize the test program resources for each individual semiconductor chip and facilitate testing. For example, the wafer test program can be reused.

Further, since the operating / non-operating state of the buffer can be set for each device pin, it is only necessary to add the buffer and the like to the semiconductor chip that needs to be separated, so that the overhead due to the addition of the test circuit can be minimized. it can.

Further, since the input / output terminals can be individually separated, the test program resources of each chip can be reused regardless of the type of the semiconductor chip.

According to the third invention, it is possible to apply to a semiconductor package suitable for miniaturization, and according to the fourth invention, the test state and the actual operation of the semiconductor chip by a common reset signal or the like. It becomes possible to efficiently switch the states with a simple circuit, which is useful for performing essential performance confirmation and failure judgment. Also, the number of terminals for the test state setting signal can be minimized.

[Brief description of drawings]

FIG. 1 is a semiconductor package according to a first embodiment of the present invention.
FIG. 3 is a perspective view of a part of the interior.

FIG. 2 is an explanatory diagram of one disconnection circuit according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of the other disconnection circuit according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of one disconnection circuit according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of the other disconnecting circuit according to the first embodiment of the present invention.

FIG. 6 is a semiconductor package according to a second embodiment of the present invention.
FIG. 3 is a perspective view of a part of the interior.

FIG. 7 is a sectional view of a conventional semiconductor package.

[Explanation of symbols]

1A, 1B internal circuit 2A, 2B semiconductor chip 3A, 3B disconnection circuit 4A, 4B pad 5 device pins 9A, 9B buffer 10 Test switch 12A, 12B Latch circuit 13A, 13B reset switch 1C, 1D internal circuit 2C, 2D semiconductor chip

Claims (3)

(57) [Claims] 1. A semiconductor package having two or more semiconductor chips connected to a common device pin, wherein conduction and non-conduction between an input / output terminal and an internal circuit are controlled based on a control signal applied to the device pin. Buffer part that can control conduction, and control that connects to test switch and reset switch
A disconnection circuit with a signal holding
It is installed between the internal circuit and the test switch, and the reset switch is open.
When F is turned on, one of the buffers becomes conductive, the test switch is turned off, and the reset switch is turned on.
A semiconductor package in which all buffers become conductive by turning on N. 2. A semiconductor chip containing a disconnection circuit
The semiconductor package according to claim 1, wherein the semiconductor package is provided by stacking . 3. A reset switch is a first conductivity type transistor.
A semiconductor chip composed of transistors is stacked on one side and
Semiconductor switch with a second conductivity type transistor
The semiconductor package according to claim 2 , wherein the body chip is laminated on the other side .