JP3449231B2 - Serial data monitoring device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data monitoring device, and more particularly to a serial data monitoring device for monitoring an error in serial transmission data synchronized on a transmitting / receiving side.

[0002]

2. Description of the Related Art Conventionally, in digital transmission, a high-order group digital signal created by dividing a plurality of low-order group digital signals on the time axis and multiplexing is transmitted on the transmitting side, and separated on the receiving side. To obtain the original low-order group digital signal. In such digital transmission, it is necessary to synchronize the signals with each other in order to correctly multiplex (separate) low (high) order group digital signals on both the transmitting and receiving sides.
Frame synchronization is one of the synchronization techniques. In frame synchronization, time-division-multiplexed high-order group digital signals are used as a signal group called "frame", and this is used as a serial data transmission unit, while a pulse group having a specific pattern called a frame synchronization pulse pattern is inserted. The border of the frame. The receiving side can correctly separate the low-order group digital signal from the received frame by identifying the frame synchronization pulse pattern from the received frame. In such frame-synchronous digital transmission, it is desired to avoid loss of synchronism on the transmitting / receiving side or to restore it early. As one of them, a synchronization clock signal and a frame pulse (Frame Pulse:
Hereinafter, it is abbreviated as FP. ) Is used to transmit serial data to detect a failure during transmission.

FIG. 7 shows an outline of the configuration of this conventionally proposed serial data monitoring apparatus for frame synchronous transmission. In this device, a transmission block 10 and a reception block 11 are connected via a transmission line 12. The transmission line 12 includes signal lines for transmitting the serial data 13, the FP 14, the synchronous clock signal 15, and the parity signal 16, respectively. The parity signal 16 is parity information of the transmission data generated by the transmission block 10, and is intended for detecting a failure when a data error occurs during transmission between the transmission side and the reception side. An error in the received data can be detected by comparing this parity information with the parity generated from the received data in the receiving block 11. As the parity information, there is even parity or odd parity depending on whether the number of “1” s of the data bits is even or odd. When an error in the received data is detected by the parity signal 16, the receiving side requests the transmitting side to resend the data so that the synchronization is not erroneously detected.

Further, Japanese Laid-Open Patent Publication No. 5-219044 discloses that
A frame synchronization circuit that uses a 0, 1 alternating pattern as a frame synchronization pattern at the beginning of a data block stores at least one frame of serial data in a shift register, and outputs the shift data one frame before from this shift register. Then, by always logically determining the 0, 1 alternating relationship between bits at the same position in each frame of the output shift data and the received data,
A technique is disclosed in which the backward protection operation time from the out-of-synchronization state to the synchronization establishment state is shortened.

[0005]

The conventional serial data monitoring apparatus shown in FIG. 7 has a data signal line, a synchronous clock signal line, and an FP in order to send the parity generated at the transmitting side to the receiving side. It is necessary to add a parity signal line in addition to the signal line. Therefore, in the case of long-distance transmission, there is a problem that an additional signal line and a relay device for the signal line are required, resulting in a very high cost. Further, as a measure for avoiding the addition of such a parity signal line, a means for increasing the transmission rate and multiplexing the parity of the transmission side data with the transmission data can be used, but as the transmission rate of the signal increases, the voltage Controlled oscillator (Voltage Controll)
ed Oscillator (VCO) must be used, which leads to an increase in the scale of the circuit. In addition, when the signal speed increases, it is affected by the frequency characteristics of the transmission / reception device or the transmission line, and when transmitting the same distance as the original signal speed, it is inevitable that deterioration during transmission will increase, and the transmission distance will be short. turn into. As a result, a relay device or the like is still required and the cost becomes high.

Further, a frame synchronization pattern as disclosed in Japanese Patent Application Laid-Open No. 5-219044 is applied to data blocks 0, 1
If the frame boundaries are identified by the alternating pattern, the data length to be transmitted becomes long when the same information as the information transmitted by the system of FIG. 7 is transmitted. Focusing on the property of serial data, the shorter the transmission time at the same transmission rate, the higher the transmission reliability.

Therefore, an object of the present invention is to provide a serial data monitoring device for monitoring a data error without adding an extra signal line and without having to improve the signal speed of transmission data.

Another object of the present invention is a serial data monitoring apparatus capable of reproducing the FP downstream even if the receiving side detects an error in the transmission line by monitoring the data error as described above. To provide.

[0009]

The [Summary of invention of claim 1 wherein, (a) a transmission data in synchronization with the reference clock, only the other section corresponding to one clock of the reference clock for each partition of a given frame period Signal state of
Take exhaust <br/> other logical sum between the first frame pulse and the inverted signal, which the pulse transmission signal generating means for generating a pulse transmission signal by the pulse and (ii) transmit data Sending means for sending the pulse transmission signal generated by the transmission signal generating means to separate transmission paths, and (c) receiving the transmission data and the pulse transmission signal sent by the sending means via the transmission path. receiving means, for generating a (d) a second frame pulse signal and a first frame pulse the same period taking an exclusive OR of after receiving the transmission data received pulse transmission signals by the receiving means Frame pulse generation means, (e)
The same cycle determining means for determining whether or not the second frame pulse generated by the frame pulse generating means has the same cycle as the first frame pulse; and (f) the first and the first cycle by the same cycle determining means. The serial data monitoring device is equipped with a transmission line error occurrence notifying means for notifying the occurrence of an error in the transmission line when it is determined that the two frame pulses are not in the same cycle.

That is, according to the first aspect of the present invention, the transmission data synchronized with the reference clock is inverted with respect to the signal state of the other sections only for the section corresponding to one clock of the reference clock for each delimiter of a predetermined frame period. With signal
The exclusive-ORed with the first frame pulse, thereby to generate a pulse transmission signal, and adapted to deliver to the transmission line together with the transmission data. The generated when these are received through the transmission path, the second frame pulse of the first frame pulse the same period the received pulse transmission signals taking signal exclusive OR after reception of the transmitted data I am trying to do it. The same cycle judging means judges whether the cycle of the second frame pulse is the same cycle as the first frame pulse, and when it is judged that these are not the same cycle, the transmission path error occurrence notifying means. Then, it is determined that an error has occurred in the transmission path during the transmission.

According to the second aspect of the present invention, (a) the transmission data synchronized with the reference clock is treated as a signal state in a section corresponding to one clock of the reference clock at every section of a predetermined frame period and in other sections. As an inverted signal
And exclusive-ORed with the first frame pulse,
Pulse transmission signal generation means for generating a pulse transmission signal by this, (b) transmission means for transmitting the transmission data and the pulse transmission signal generated by this pulse transmission signal generation means to separate transmission lines, respectively. ) exclusive receiving means for receiving and transmitting data and pulse transmission signals sent through the transmission line by the transmitting means, and (d) signal after receiving the transmission data received pulse transmission signals by the receiving means a frame pulse generating means for generating a second frame pulse of the first frame pulse the same period taking logical sum, (e) a second frame generated by the frame pulse producing <br/> forming means Pulse is first
The same cycle determining means for determining whether or not it has the same cycle as that of the frame pulse, and (f) when the first and second frame pulses are not determined to have the same cycle by the same cycle determining means, a transmission path error A transmission path error occurrence notifying means for notifying the occurrence and stopping the output of the second frame pulse; and (g) a first based on a reference clock.
Free-running frame pulse generating means for generating free-running frame pulses having the same period as the frame pulse, and (h) this free-running frame pulse generating means according to the phase of the second frame pulse generated by the frame pulse generating means. The serial data monitoring device is provided with a frame pulse phase adjusting means for outputting the free-running frame pulse generated by.

That is, according to the second aspect of the present invention, the transmission data synchronized with the reference clock is inverted with respect to the signal states of the other sections only for a section corresponding to one clock of the reference clock for each delimiter of a predetermined frame period. With signal
The exclusive-ORed with the first frame pulse, thereby to generate a pulse transmission signal, and adapted to deliver to the transmission line together with the transmission data. The generated when these are received through the transmission path, the second frame pulse of the first frame pulse the same period the received pulse transmission signals taking signal exclusive OR after reception of the transmitted data I am trying to do it. The same cycle judging means judges whether the cycle of the second frame pulse is the same cycle as the first frame pulse, and when it is judged that these are not the same cycle, the transmission path error occurrence notifying means. Then, it is determined that an error has occurred in the transmission path during the transmission, and the output of the second frame pulse is stopped. Further, the free-running frame pulse generating means generates a free-running frame pulse having the same period as the first frame pulse based on the reference clock, and generates this free-running frame pulse in synchronization with the phase of the second frame pulse. ing. As a result, even when the transmission path error occurrence notifying unit detects the occurrence of an error during transmission, the first frame pulse and the first frame pulse are synchronized with the phase of the second frame pulse when the transmission path error does not occur. The frame pulse having the same cycle can be supplied to the downstream device.

[0013] In the third aspect of the present invention, a serial data monitoring apparatus according to claim 1 or claim 2 wherein the frame-Pas
The loose generation means generates a third frame pulse having the same cycle as the first frame pulse from the pulse transmission signal based on the transmission data, and performs synchronization protection of the third frame pulse to thereby generate the second frame pulse. Is generated.

That is, according to the third aspect of the present invention, the third frame pulse having the same period as the first frame pulse is generated from the pulse transmission signal based on the transmission data,
The frame pulse with synchronization protection is output as the second frame pulse. As a result, it is possible to perform frame synchronization protection that has been conventionally used to prevent erroneous synchronization, and it is possible to further improve reliability.

According to a fourth aspect of the invention, in the serial data monitoring apparatus according to the second aspect, the frame pulse phase adjusting means is the second one generated by the frame pulse generating means.
The output of the free-running frame pulse is stopped when the frame pulse is not input within a predetermined period.

That is, according to the invention of claim 4, when the second frame pulse generated by the frame pulse generating means is not input within a predetermined period,
In a system in which it is determined that a transmission path error frequently occurs and it is not preferable to transmit the frame pulse to the downstream device in such a case, the transmission of the free-running frame pulse can be stopped.

According to a fifth aspect of the present invention, in the serial data monitoring apparatus according to the first or second aspect, the pulse transmission signal takes an exclusive OR of the transmission data and the first frame pulse in bit units. The second frame pulse is generated by performing an exclusive OR operation on a bit-by-bit basis between the transmission data received by the receiving means and the pulse transmission signal.

That is, in the invention described in claim 5, the pulse transmission signal takes the exclusive OR of the first frame pulse and the transmission data in bit units, and the second frame pulse further receives the transmission data and the pulse transmission. The signal and the signal are respectively generated by taking the exclusive OR in the bit unit.

[0019]

DETAILED DESCRIPTION OF THE INVENTION

[0020]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows an outline of the configuration of a serial data monitoring apparatus according to an embodiment of the present invention. In this serial data monitoring device, a transmission block 20 and a reception block 21 are connected via a transmission line 22. The serial data signal 23, the transmission FP 24, and the synchronous clock signal 25 are separately transmitted on the transmission path 22. As described above, in the serial data monitoring apparatus according to the present embodiment, the clock synchronized with the transmission block 20 and the reception block 21 is supplied as the synchronization clock signal 25, and the frame synchronous transmission for transmitting the serial data is performed using the FP. ing. A feature of the serial data monitoring apparatus in this embodiment is that the transmitting side generates information for detecting a signal error in the transmission path by taking the exclusive OR of the FP and the transmitting data, and the receiving side The first feature is that the occurrence of an error in the transmission path is detected by taking the exclusive OR of the information for detecting the signal error and the received data. Furthermore, the received serial data signal 23, error detection signal 24, and synchronization clock signal 2
The second feature is to reproduce the FP from 5.

In the transmission block 20 of such a serial data monitoring apparatus, the transmission data 26 whose data to be transmitted is serial data is transmitted to the first by the signal branching device 27.
Of the branch transmission data 28 and the second branch transmission data 29. The first branch transmission data 28 is input to the flip-flop 30 and retimed by the synchronization clock 25 that is synchronized on the transmitting and receiving sides. The transmission data retimed by the flip-flop 30 is sent to the reception block 21 as a serial data signal 23. On the other hand, the second branch transmission data 29 is input to one input end of an exclusive OR (hereinafter abbreviated as EXOR) circuit 31. Further, the synchronous FP 32 is input to the other input terminal of the EXOR circuit 31, and the second branch transmission data 29 which is serial data and the synchronous FP 32 are subjected to exclusive OR operation in bit units,
It is sent as an EXOR operation signal 33. This EXOR
The operation signal 33 is input to the flip-flop 34 and retimed by the synchronous clock 25. The EXOR operation signal retimed by the flip-flop 34 is sent to the reception block 21 as the transmission FP 24.

Reception block 2 of the serial data monitoring device
At 1 , the serial data signal 23 is input to the signal splitter 35. The transmission data signal input to the signal branching device 35 is branched into a first branch receiving data 36 and a second branch receiving data 37. The first branch reception data 36 is
The timing is input to the flip-flop 38 and retimed by the synchronization clock 25 which is synchronized on the transmitting and receiving sides. The branch reception data retimed by the flip-flop 38 becomes reception data 39 which is serial data to be received by the reception block 21. On the other hand, the second branch reception data 37 is input to one input terminal of the EXOR circuit 40. Further, the transmission FP 24 is input to the other input end of the EXOR circuit 40, and the EXOR circuit 3
The transmission FP and the reception data for which the exclusive OR is calculated between the synchronous FP 32 and the transmission serial data in 1 are again subjected to the exclusive OR operation in bit units, and the EXOR calculation signal 41
Is sent as. The EXOR operation signal 41 is EXORed with the serial data signal 23 received by the signal splitter 35.
The transmission FP 24 and the synchronization clock 25 received by the circuit 40
If there is no transmission error in any of them, the same signal as the synchronous FP 32 is obtained. The EXOR operation signal 41 is input to the flip-flop 42 and retimed by the synchronous clock 25. The EXOR operation signal retimed by the flip-flop 42 is input to the frame cycle counter 44 as the reception FP 43.

The frame cycle counter 44 can detect whether or not the receiving FP 43 is input at the same predetermined frame cycle F as when transmitting. When it is detected that the reception FP 43 is input in a predetermined frame cycle F, the frame cycle coincidence signal 45 having the same cycle as this frame cycle can be output. On the other hand, when it is detected that the receiving FP 43 has not been input during the predetermined frame period , it is determined that an error has occurred during signal transmission, and the alarm signal 46 can be output as a data error alarm. It is like this. This alarm signal 46 can be used to improve the reliability of transmission data, such as requesting the transmission side to resend or discarding received data.

The frame cycle coincidence signal 45 output from the frame cycle counter 44 is input to the frame protection circuit 47 in the same cycle as the synchronous FP 32. The frame protection circuit 47 performs frame synchronization protection in n stages to prevent erroneous synchronization, and outputs a frame synchronization protection signal 48 when n stages match. The frame synchronization protection signal 48 is input to the FP generation circuit 49 as a trigger signal. The FP generation circuit 49 can output the reproduction FP 50 in synchronization with the input phase of the frame synchronization protection signal 48. Even when the frame synchronization protection signal 48 is not input due to a transmission error, the FP phase error due to a signal error during transmission is absorbed by performing free-running in the frame cycle, and the FP at the normal timing is output as the reproduction FP 50. Is able to. As a result, the synchronization F on the transmitting side is
Even if the phase of P32 changes, it is possible to output the FP at the normal timing after the n-stage synchronization protection.

Next, the main part of the reception block that enables the reproduction of such an FP will be described. First, an example of the configuration of the frame cycle counter 44 will be described.

FIG. 2 shows a main configuration of the frame cycle counter 44 shown in FIG. The frame cycle counter 44 includes a counter 55. The counter 55 has a synchronous clock 25 and a reception FP4.
3 has been entered respectively. The counter 55 counts by using the synchronous clock 25 as a reference clock, and receives F
The count value is reset by P43. Further, the counter 55 sends out the frame cycle coincidence signal 45 after finishing counting for the same frame cycle as the synchronous FP 32 of the transmission block 20, but does not start counting unless the reception FP 43 is input. There is.
Therefore, the counter 55 can output the frame cycle coincidence signal 45 for each frame cycle as long as an appropriate reception FP 43 corresponding to the same frame cycle as the synchronous FP 32 of the transmission block 20 is input in advance. Has become. In addition, this frame cycle counter 44
Is provided with an EXOR circuit 56, receives the reception FP 43 and the frame period coincidence signal 45 as an input, and outputs an exclusive OR of these as an alarm signal 46. That is, when the counter 55 receives the appropriate reception FP 43 and the frame cycle coincidence signal 45 is not output at the same timing as the reception FP 43 using the synchronous clock 25 as a reference clock, this error is output as a pulse as the alarm signal 46. It will be. At this time, a plurality of alarm signal 46 pulses are output within one frame.

FIG. 3 shows operation waveforms of respective signals when the reception FP 43 is erroneously inserted in the frame period counter 44 shown in FIG. 3A shows an outline of operation waveforms of the reception FP 43, FIG. 3B shows a synchronous clock 25, FIG. 3C shows a frame period coincidence signal 45, and FIG. .

When no error occurs during transmission like the frames 57 and 58 and the receiving FP 43 is input to the frame cycle counter 44 at the same frame cycle F as the synchronous FP 32 as shown in the waveform 59, the counter 55 Is received F
Each time P43 is input, counting is performed using the synchronous clock 25 shown in the waveform 60 as a reference clock, and the frame period coincidence signal 45 is output for each frame period that is the same as the synchronous FP 32 of the transmission block 20 (waveform 61 in FIG. 3). .
At this time, since the reception FP 43 and the frame period coincidence signal 45 are output at the same timing, the pulse of the alarm signal 46 is not output (waveform 62 in FIG. 3).

However, when an error occurs during transmission and the error pulse 64 of the frame 63 is inserted into the receiving FP 43, the counter 55 causes the counter 55 to receive the first receiving FP 43 of the frame 63.
The counting is started by inputting the pulse 65 of. However, the counter 55 has the synchronous FP 32 of the transmission block 20.
Since the error pulse 64 is input before the count for the same frame period is completed, the count value is reset again at this point. Therefore, counter 5
5 does not output the predetermined frame period coincidence signal 45 of the frame 66 (pulse 67 in FIG. 3). EXOR
Since the circuit 56 outputs the exclusive OR of the reception FP 43 and the frame period coincidence signal 45 which is the output of the counter 55, the timing of the error pulse 64 inserted in the reception FP 43 of the frame 63 and the frame period of the frame 66. Two pulses are output as the alarm signal 46 at the timing of the pulse 67 that should originally be output to the coincidence signal 45 (pulses 68 ₁ and 68 _{2 in} FIG. 3). Further, even if an error occurs during the transmission of the synchronous clock signal 25, it can be detected similarly.

FIG. 4 shows operation waveforms of respective signals when the receiving FP 43 is not inserted by mistake in the frame period counter 44 shown in FIG. Figure 4 (a)
Shows the operation waveforms of the reception FP 43, FIG. 7B shows the synchronous clock 25, FIG. 7C shows the frame period coincidence signal 45, and FIG.

When no error occurs during transmission like the frames 57 and 58 and the receiving FP 43 is input to the frame period counter 44 at the same frame period F as the synchronous FP 32 as shown by the waveform 59, the counter 55 Is received F
Every time P43 is input, the synchronization clock 25 shown in the waveform 60 is used as a reference clock for counting, and the frame period coincidence signal 45 is output at the same frame period as that of the synchronous FP 32 of the transmission block 20 (waveform 61 in FIG. 4). .
At this time, since the reception FP 43 and the frame period coincidence signal 45 are output at the same timing, the pulse of the alarm signal 46 is not output (waveform 62 in FIG. 4).

However, if an error occurs during transmission, the frame
Pal that should have been originally inserted in the receiving FP43 of
When there is no space (69 in Fig. 4)₁), Counter 55 is a frame
The count is started by the input of the reception FP43 of the system 66.
Therefore, in this frame, the count of the counter 55 is
Not started. Therefore, the frame next to the frame 66
The frame cycle match signal 45 that should be output at the beginning of
No output (69 in Fig. 4)₂). The EXOR circuit 56 is
Frame cycle output from the receiving FP 43 and the counter 55
Since the exclusive OR with the coincidence signal 45 is output, the frame
Pulse 6 that should be originally inserted in the reception FP43 of system 66
9₁Timing and the beginning of the frame following frame 66
Is output to the frame cycle match signal 45.
Ruth 69 ₂As the alarm signal 46 at the timing of
Two pulses are output (pulse 68 in FIG. 4).₁, 6
8₂). In addition, if the synchronous clock signal 25 has an error during transmission,
Even if it occurs, it can be detected similarly.

As described above, the frame cycle counter 44 is
The count value is reset by the input of the reception FP 43, and the counter 55 is provided so as not to start counting after the end of the count unless the reception FP 43 is input. Then, the count value is output as the frame cycle coincidence signal 45 based on the synchronous clock 25,
An exclusive OR of the frame period coincidence signal 45 and the reception FP 43 is used to detect an error in the transmission of the reception FP 43 or the synchronization clock 25, and this is output as the frame period coincidence signal 45 and the alarm signal 46. You can do it.

The frame protection circuit 47 is a well-known front n-stage backward one-stage frame synchronization protection circuit, and is not shown. The frame cycle coincidence signal 45 input to the frame protection circuit 47 should be input in the same cycle F as the synchronous FP 32 unless there is a transmission error. Therefore, a frame position pulse output in the cycle F is generated, and it is detected for each frame whether or not this and the frame cycle coincidence signal 45 are output at the same timing, and output n times consecutively at the same timing. If it is detected that the synchronization is established, the backward n-stage protection is performed. In this way, the frame synchronization protection signal 48 is output as a trigger signal to the FP generation circuit 49 when it is detected that the signal is output n times consecutively at the same timing. Of course, it is desirable to select the optimum number of front protection stages and rear protection stages according to the system to be applied.

Next, the FP generation circuit 49 will be described.

FIG. 5 shows an outline of the configuration of the FP generation circuit 49. The frame synchronization protection signal 48 input to the FP generation circuit 49 is input to the phase detection circuit 70. The phase detection circuit 70 can detect the phase shift of the frame synchronization protection signal 48 from the synchronization clock 25, and sends the phase shift to the free-running FP generation circuit 71. The free-running FP generation circuit 71 is free-running based on the synchronous clock 25, generates the free-running FP 75 having the same frame period F as the synchronous FP 32 of the transmission block 20, and shifts the phase notified from the phase detection circuit 70. It is possible to output this as the reproduction FP 50 in accordance with the above.

As described above, the FP generation circuit 49 outputs the reproduction FP 50 whose phase is adjusted according to the input phase of the frame synchronization protection signal 48, and even when the frame synchronization protection signal 48 is not input due to a transmission line error. By outputting the free-running FP at the frame period F, it is possible to absorb the FP phase error at the time of a bit error and output the normal FP downstream.

Next, the operation of the serial data monitoring apparatus having the main configuration described above will be described with reference to FIGS. 1 and 6.

FIG. 6 shows an outline of signal operation waveforms of respective parts of the serial data monitoring apparatus in this embodiment. Here, the frame protection circuit 47 is composed of two front stages and one rear stage.
It is assumed that it is a frame synchronization protection circuit of stages. 6A shows a synchronous clock signal 25, FIG. 6B shows transmission data 26, and FIG.
The figure (c) shows the signal operation waveforms of the synchronous FP 32, and the figure (d) shows the signal operation waveforms of the EXOR operation signal 33, respectively. In addition, as the signal operation waveform of each part in the reception block 21,
6 (e) is a synchronous clock signal 25, FIG. 6 (f) is a serial data signal 23, FIG. 6 (g) is a transmission FP 24, FIG. 6 (h) is an EXOR operation signal 41, and FIG. 6 (i) is a frame period. The coincidence signal 45, the figure (j), the frame synchronization protection signal 48, and the figure (k), the signal operation waveforms of the reproduction FP 50, respectively.

In the transmission block 20, the synchronous clock signal 25 and the transmission data 26 are transmitted as shown in FIG.
It is assumed that the input is made as shown in (b) (waveforms 80 and 81 in FIG. 6). The synchronization clock signal 25 is synchronized in the transmission block 20 and the reception block 21 (waveforms 80 and 82 in FIG. 6). The synchronous FP 32 is input in synchronization with the synchronous clock 25 every predetermined frame period F (waveform 83 in FIG. 6). The transmission data 26 is bifurcated into first and second branch transmission data 28 and 29 by a signal branching device 27, and an exclusive OR of the synchronous FP 32 and the second branch transmission data 28 is calculated in the EXOR circuit 31. . That is, "1" is set only when the transmission data 26 and the synchronous FP 32 at the same timing have bit values of 1 or 0, which are opposite to each other.
And as a result, the EXOR operation signal 33 is output (waveform 84 in FIG. 6). Then, the EXOR operation signal 33 and the first branch transmission data 28 are both retimed by the flip-flops 34 and 30 by the synchronous clock 25. In this manner, the transmission block 20 sends the synchronous clock signal 25 and the transmission FP 24 and serial data signal 23 retimed by this signal to prevent an increase in the number of signals such as supervisory signals for detecting transmission errors. There is.

In the reception block 21, the serial data signal (waveform 85 in FIG. 6) transmitted by the transmission block 20 via the transmission path 22 is converted into the first and second branch reception data 36, 37 by the signal branching device 35. There are two branches. Here, the broken line portion 8 is added to the serial data signal 23 of FIG.
It is assumed that a transmission line error as shown by 6 has occurred. As described above, the transmission FP 24 only re-timed the EXOR operation signal 33 with the flip-flop, so the waveform in each frame is transmitted with the same waveform as the EXOR operation signal 33 shown in FIG. 6D. Waveform 6
7). Therefore, in the EXOR circuit 40 of the reception block 21,
Second branch reception data obtained by bifurcating the serial data signal
When the exclusive logical operation of 37 and the transmission FP 24 is performed, it becomes “1” only when the bit values have mutually opposite bit values of 1 or 0. Therefore, if there is no transmission path error, the same waveform as the synchronous FP 32 Will be output as the EXOR operation signal 41. However, when there is a transmission line error as indicated by the broken line portion 86, the erroneous detection pulse 88 is detected at the same timing as the transmission line error position by the exclusive OR operation in the EXOR circuit 40 (FIG. 6). Waveform 8
9).

When such an EXOR operation signal 41 is retimed by the flip-flop 42 and then input to the frame cycle counter 44, the counter 55 shown in FIG.
From this, the frame cycle coincidence signal 45 counted in accordance with the input of the reception FP 43 for each frame cycle F is not output (waveform 90 in FIG. 6), and at the same time, it is judged that a transmission path data error has occurred, The alarm signal 46 will be output. However, except for the transmission path error in the broken line portion 86, the frame cycle match signal 45 is set to the frame cycle F.
For each (waveform 91 in FIG. 6).

In the frame protection circuit 47, by protecting the pulse of the frame cycle matching signal 45, the data may be erroneous in the frame cycle, and the frame cycle matching signal 45
In order to prevent erroneous frame pulses from being sent to the downstream even if the pulse of the
It is taking steps. As a result, the frame cycle protection signal 48 is output only after the frame cycle coincidence signal 45 has been input twice in a predetermined frame cycle F (waveform 92 in FIG. 6). When the frame synchronization protection signal 48 is input, the FP generation circuit 49 self-runs and generates the reproduction FP 50 in synchronization with the cycle. Even if the frame synchronization protection signal 48 shown in FIG. 6 (j) is in a missing state in the frame protection circuit 47, the reproduction FP is normally sent out at the frame period F downstream (waveform 93 in FIG. 6).

As described above, in the serial data monitoring apparatus according to the present embodiment, the transmission block 10 performs the exclusive OR of the transmission data 26 and the synchronous FP 32 to transmit F.
P24 is generated, and the reception side and the transmission FP24 are generated on the reception side.
The exclusive OR is performed to detect the coincidence with the predetermined frame period F. This makes it possible to detect a transmission path error that has occurred during transmission. Further, even when an error occurs in the transmission line and a mismatch with the frame cycle F is detected in this way, a frame synchronization signal which is a match detection signal with the frame cycle F that has been input until then is protected after n stages of protection. Reproduce the free-running FP according to the phase of the protection signal 48 F
By sending P50 downstream, the FP phase error at the time of a bit error is absorbed and a normal FP is supplied to the downstream side.

Modification

In the serial data monitoring apparatus according to this embodiment, the frame cycle counter 44, the frame protection circuit 47, and the FP generation circuit 49 allow the FP generation circuit 4 to operate even when a data error occurs in the frame cycle counter 44.
The regenerated FP was sent downstream by the self-propelled FP generated in 9. However, depending on the system, when data errors frequently occur, it may not be necessary to send the FP downstream anymore. Therefore, in the FP generation circuit of the serial data monitoring device in this embodiment, the frame protection circuit 4
The frame synchronization protection signal 48 input from 8 is monitored,
When the input of this signal is not detected due to the absence of arbitrary plural N frame inputs in a certain period of time, the sending of the reproduction FP 50 is stopped to prevent the sending of unnecessary FPs downstream. be able to.

In the serial data monitoring apparatus according to the present embodiment and this modification, the transmitting side generates an exclusive OR of the transmitting data and the FP, and the receiving side generates an exclusive OR of the receiving data and the transmitting FP. Although the FP is reproduced by the logical sum and the transmission path error is detected during the transmission, the calculation on the transmitting side and the receiving side is not limited to the exclusive logical sum calculation. The calculation method is not limited as long as the transmission data and FP on the transmission side and the transmission FP and reception data on the reception side can be calculated to detect the transmission path error and reproduce the FP on the reception side.

Further, it goes without saying that the present invention is not limited to the main configuration of the frame cycle counter 44 or the FP generation circuit 49 in this embodiment and this modification.

Further, a transmission block 20 and a reception block 21
The transmission line connecting the and is not limited to the signal form of the transmission line. For example, the signal transmitted via the transmission path may be an optical signal or an electric signal.

[0051]

As described above, according to the first aspect of the present invention, it is possible to detect the occurrence of a transmission path error that has occurred during transmission without newly adding a signal line between the transmission / reception blocks, and to the receiving side. It becomes possible to reproduce the frame pulse in. Furthermore, since it is not necessary to use a method of increasing the transmission speed and multiplexing signals, the device can be downsized. Further, since the transmission / reception blocks only need to be connected by the data signal line, FP, and clock signal line, even if the transmission / reception side needs to change, it is not necessary to change the transmission path, which is excellent in system expandability. ing.

According to the second aspect of the invention, in addition to the effect of the first aspect of the invention, a transmission line error occurs even when the transmission line error occurrence notifying means detects an error during transmission. It becomes possible to supply the frame pulse having the same period as the first frame pulse to the downstream device in accordance with the input phase of the second frame pulse when not performing.

Further, according to the third aspect of the invention, the frame synchronization protection conventionally used for preventing erroneous synchronization can be performed, and the reliability can be further improved.

Further, according to the invention of claim 4,
Even in a system in which it is not desirable to send the frame pulse to the downstream device, it can be applied only by stopping the sending of the free-running frame pulse.

Further, according to the invention of claim 5, the exclusive OR can be realized with a very simple structure, so that the cost of the device can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a configuration of a frame data monitoring device in an embodiment of the present invention.

FIG. 2 is a block diagram showing an outline of a main part configuration of a frame cycle counter in the present embodiment.

FIG. 3 is a timing chart showing operation waveforms of respective parts when a pulse is inserted due to a transmission error of the frame cycle counter in the present embodiment.

FIG. 4 is a timing chart showing operation waveforms of respective portions when there is no pulse originally inserted due to a transmission error of the frame cycle counter in the present embodiment.

FIG. 5 is a block diagram showing an outline of a main part configuration of an FP generation circuit in the present embodiment.

FIG. 6 is a timing chart showing operation waveforms of respective parts of the frame data monitoring device in the present embodiment.

FIG. 7 is a block diagram showing an outline of a configuration of a conventionally proposed frame synchronization transmission system.

[Explanation of symbols]

20 send block 21 Receive Block 22 Transmission line 23 Serial data signal 24 Transmission FP 25 Synchronous clock signal 26 Transmission data 27, 35 Signal splitter 28 First branch transmission data 29 Second branch transmission data 30, 34, 38, 42 flip-flops 31, 40 EXOR circuit 32 Synchronous FP 33, 41 EXOR operation signal 36 First branch received data 37 Second branch reception data 39 Received data 43 Reception FP 44 frame cycle counter 45 frame period match signal 46 Warning signal 47 frame protection circuit 48 frame sync protection signal 49 FP generation circuit 50 playback FP

Claims (5)

(57) [Claims] 1. Transmitted data synchronized with a reference clock ,
For each delimiter of a predetermined frame cycle, only the section corresponding to one clock of this reference clock is signaled in other sections.
On purpose between the first frame pulse and inverted signal
In an exclusive OR, thereby a pulse transmission signal generating means for generating a pulse transmission signal and sends the transmission data and a pulse transmission signal generated by the pulse transmission signal generating means to each separate transmission path Sending means, receiving means for receiving the transmission data and the pulse transmission signal sent by the sending means via the transmission path, and receiving the pulse transmission signal received by the receiving means for receiving the transmission data a frame pulse generating means for generating a second frame pulse signal and exclusive same period as the first frame pulse taking after, a second frame pulse generated by the frame pulse generating means An identical cycle determining means for determining whether or not the same cycle as the first frame pulse, Serial data monitoring apparatus characterized by comprising a transmission path error occurrence notification means for notifying the occurrence of errors in the transmission path when said first and second frame pulse is judged not to be the same cycle by means. 2. A method transmitting data synchronized with the reference clock,
For each delimiter of a predetermined frame cycle, only the section corresponding to one clock of this reference clock is signaled in other sections.
On purpose between the first frame pulse and inverted signal
In an exclusive OR, thereby a pulse transmission signal generating means for generating a pulse transmission signal and sends the transmission data and a pulse transmission signal generated by the pulse transmission signal generating means to each separate transmission path Sending means, receiving means for receiving the transmission data and the pulse transmission signal sent by the sending means via the transmission path, and receiving the pulse transmission signal received by the receiving means for receiving the transmission data a frame pulse generating means for generating a second frame pulse signal and exclusive same period as the first frame pulse taking after, a second frame pulse generated by the frame pulse generating means An identical cycle determining means for determining whether or not the same cycle as the first frame pulse, A transmission path error occurrence notifying means for notifying the occurrence of a transmission path error and stopping the output of the second frame pulse when the means determines that the first and second frame pulses are not in the same cycle; A free-running frame pulse generating unit that generates a free-running frame pulse having the same period as the first frame pulse based on a clock, and a self-running frame pulse generating unit that matches the phase of the second frame pulse generated by the frame pulse generating unit. A serial data monitoring device comprising: a frame pulse phase adjusting means for outputting the free-running frame pulse generated by the running frame pulse generating means. 3. The frame pulse generation means generates a third frame pulse having the same period as the first frame pulse from the pulse transmission signal based on the transmission data, and synchronizes the third frame pulse. The serial data monitoring apparatus according to claim 1 or 2, wherein the second frame pulse is generated by taking protection. 4. The frame pulse phase adjustment means stops the output of the free-running frame pulse when the second frame pulse generated by the frame pulse generation means is not input within a predetermined period. The serial data monitoring device according to claim 2, characterized in that 5. The pulse transmission signal is generated by taking an exclusive OR of the transmission data and the first frame pulse in bit units, and the second frame pulse is received by the receiving means. 3. The serial data monitoring device according to claim 1, wherein the transmission data and the pulse transmission signal are generated by taking an exclusive OR in bit units.