JP3450150B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device capable of flattening a semiconductor surface regardless of the layout of underlying metal wiring.

[0002]

2. Description of the Related Art In a method of manufacturing a semiconductor device having a multi-wiring structure of a VLSI, it is essential to flatten the entire surface of the LSI because the margin of the depth of focus of lithography is small. The conventional planarization method by etching has a problem that a groove is formed at each boundary of a mask. As a method for planarizing the entire surface of a wide LSI, a chemical mechanical polishing method, Chemical Mechanical method, is used.
anical Polish method (hereinafter referred to as CMP method)
Came to be used. The CMP method is a method in which a wafer is pressed against a polishing pad attached to a surface plate while pouring a polishing liquid containing polishing abrasive grains, and the surface plate is rotated while the weight is applied to the wafer to perform polishing. However, in the CMP method, the interlayer insulating layer above the dense portion of the underlying wiring is hard to be polished, and the interlayer insulating layer above the sparse portion is likely to be polished, resulting in a difference in flatness.

FIGS. 5A to 5C are sectional views showing steps of a conventional method for manufacturing a semiconductor device described in, for example, the patent of Japanese Patent No. 2555947. FIG. 6 is a plan view of FIG. 5C showing the steps of the conventional semiconductor device manufacturing method. As shown in FIG. 5A, an insulating layer 12 of a silicon oxide film is formed on a silicon substrate 11 by a CVD method, and an aluminum light alloy 13 is formed thereon by a sputtering method.
Of 0.5 μm is formed. Next, the aluminum-based alloy 13 is patterned by a normal process to form the wiring 13A and the dummy wiring 13B having a desired pattern. Dummy wiring B
When the wirings 13A are separated by a predetermined dimension, for example, 2 μm or more, the wirings are always arranged in the space between them. As shown in FIG. 6, the dummy wiring 13B is formed in an island shape so that parasitic capacitance does not occur between the dummy wiring 13B and the wiring 13A.

Next, as shown in FIG. 5 (b), CV is applied to the entire surface.
The plasma nitride film 14 was used as a stopper film by the method D.
A film is formed to a thickness of 1 μm. Further, the interlayer insulating layer 1 is formed by the CVD method.
5 is deposited to a thickness of 2 μm.

Next, as shown in FIG. 5C, the interlayer insulating layer 1 is formed by CMP until the plasma nitride film 14 is exposed.
Polish 5. At this time, the plasma nitride film 14 on the dummy wiring 13B serves as a stopper film, and the interlayer insulating layer 15 in the region where the wiring 13A does not exist is prevented from being polished, and the entire planarization is achieved.

[0006]

However, as shown in FIG.
In the conventional method of manufacturing a semiconductor device shown in FIG.
In the case of the multilayer wiring structure, the relative dielectric constant ε of the plasma nitride film 14 left after polishing is as large as 7.4 and the interlayer insulating layer 15 is large.
There is a problem that the capacitance between the electrode 13 formed on both sides of and the electrode (not shown) formed on the interlayer insulating layer 15 is large, and the operation speed of the semiconductor device is slowed down. Further, since there are two layers having different etching rates of the interlayer insulating layer 15 and the plasma nitride film 14 between the wiring 13A and the upper wiring, the wiring 13A and the wiring on the upper surface of the interlayer insulating layer formed thereon are There is a problem that it is not easy to control the etching time for forming a through hole for connecting the two.

In order to prevent a decrease in operating speed, the polishing position of the interlayer insulating layer 15 by the CMP method is set at the plasma nitride film 1.
4 When the plasma nitride film 14 remaining after reaching the surface 4 is removed by etching, a step is generated at the boundary between the place where the plasma nitride film 14 is present and the place where the plasma nitride film 14 is absent. There is a problem that a step of filling the insulating layer later or performing another flattening by the CMP method again is required. Further, in order to provide the dummy wiring 13B, it is necessary to further design the pattern of the dummy wiring after designing the wiring pattern, which causes a problem that the mask manufacturing time increases.

The present invention has been made in order to solve the above problems, and does not depend on the wiring pattern of the lower layer, LS.
I An object of the present invention is to obtain a method for manufacturing a semiconductor device capable of flattening over the entire surface with a small number of steps.

[0009]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a photosensitive insulating layer is formed on an insulating layer formed on a wiring pattern on a semiconductor substrate. Step, a second step of irradiating the photosensitive insulating layer with light over the entire surface, a third step of developing the photosensitive insulating layer to form a residual photosensitive insulating layer, and an excessive polishing of the residual photosensitive insulating layer. And a fourth step of polishing the second insulating layer as a suppressing film by a chemical mechanical polishing method.

In the method of manufacturing a semiconductor device according to the second aspect of the present invention, the photosensitive insulating layer is a positive type photosensitive insulating layer.

In the method of manufacturing a semiconductor device according to the third aspect of the present invention, the positive photosensitive insulating layer is made of a silsesquioxane-based material.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the photosensitive insulating layer is a negative type photosensitive insulating layer and the wiring pattern has an antireflection film.

The method of manufacturing a semiconductor device according to a fifth aspect of the present invention includes a heat treatment step of hardening the residual photosensitive insulating layer.

[0014]

DETAILED DESCRIPTION OF THE INVENTION

Embodiment 1. 1 (a) to 1 (c) and 2
2A and 2B are process diagrams showing a method for manufacturing a semiconductor device according to the first embodiment of the invention. In FIG. 1 (a),
21 is a silicon substrate which is a semiconductor substrate. Reference numeral 22 is a SiO 2 film which is a first insulating layer, and is formed on the silicon substrate 21. An aluminum wiring pattern 23 having a film thickness of 0.5 μm is formed on the first insulating layer 22. Reference numeral 24 is a second insulating layer of SiO 2 having a film thickness of 2 μm,
It is formed on the aluminum wiring pattern 23 and the first insulating layer 22. Reference numeral 25 denotes a positive photosensitive insulating layer corresponding to the photosensitive insulating layer, which is a SOG film made of a silsesquioxane-based material having a silicon ladder structure, in which a portion irradiated with light is easily dissolved in a developing solution. 2 insulating layers 2
It is formed on the No. 4 surface. The positive photosensitive insulating layer 25 is an organic material and has a relative dielectric constant ε of about 4 or less.
The positive photosensitive insulating material 25 is not limited to the silsesquioxane-based material, and may be a photosensitive insulating material that generates an OH group which is easily dissolved in an alkaline developing solution by exposure to light.

In FIG. 1 (b), 26a is an excimer laser beam or ultraviolet light from a mercury lamp, which is applied to the positive photosensitive insulating layer 25. 27a is the first reflected light, which is the aluminum wiring pattern 2 by the irradiation of the ultraviolet light 26a.
It is the reflected light from No. 3. 27b is the second reflected light, which is the reflected light from the first insulating layer 22 due to the irradiation of the ultraviolet light 26a. In FIG. 1C, reference numeral 25a denotes a positive photosensitive insulating layer to be irradiated, which is after the positive photosensitive insulating layer 25 is irradiated with the ultraviolet light 26a. Reference numeral 28a denotes a first irradiated positive photosensitive insulating layer, which is an irradiated positive photosensitive insulating layer on the wiring layer 23. Reference numeral 28b denotes a second irradiated positive photosensitive insulating layer, which is an irradiated positive photosensitive insulating layer in a region without the wiring layer 23. In FIG. 2A, 28c is a residual positive photosensitive insulating layer corresponding to the residual photosensitive insulating layer, which is the positive photosensitive insulating layer 2 to be irradiated after the irradiation of the ultraviolet light 26a.
It remains after the development of 5a. 30 is a heat ray in the heat treatment. In FIG. 2B, 24b is CMP.
It is the second insulating layer after polishing.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to manufacturing process diagrams shown in FIGS. Figure 1
In the first step shown in (a), the second insulating film having a thickness equal to or larger than the film thickness of the wiring pattern 23 is formed on the aluminum wiring pattern 23 formed on the first insulating layer 22 on the silicon substrate 21 by a usual method. Form layer 24. Further, the second insulating layer 2
SOG of a positive type photosensitive material is applied onto 4 and then sintered to form a positive type photosensitive insulating layer 25.

Next, in the second step shown in FIG.
The positive photosensitive insulating layer 25 is irradiated with ultraviolet light 26a of an excimer laser on the entire surface without a mask. As shown in FIG. 1C, the irradiated positive photosensitive insulating layer 28 a above the aluminum wiring pattern 23 is irradiated with ultraviolet light 26 a and reflected light 27 a of high intensity, and the aluminum wiring pattern 23 without the aluminum wiring pattern 23 is exposed. Ultraviolet light 26a and reflected light 2 having a small intensity are applied to the irradiated positive photosensitive insulating layer 28b in the upper part of the space.
7b is irradiated. As a result, the aluminum wiring pattern 23
The irradiated positive photosensitive insulating layer 28a on the upper side is more easily dissolved in the developing solution.

Next, in a third step shown in FIG. 2A, the irradiated positive photosensitive insulating layer 25a is developed with a developing solution for a predetermined time. The irradiated positive photosensitive insulating layer 28a on the aluminum wiring pattern 23 is first dissolved, and the exposed positive photosensitive insulating layer 28b between the aluminum wiring patterns 23 remains. Next, the residual positive photosensitive insulating layer 28c is heat-treated at 400 ° C. for about 20 minutes to irradiate it with the heat ray 30 to cure the residual positive photosensitive insulating layer 28c. This is to increase the hardness of the residual positive photosensitive insulating layer 28c. However, the heat treatment step is not always required as long as it has a hardness higher than a predetermined level from the beginning.

Next, in the fourth step shown in FIG. 2B, the residual positive photosensitive insulating layer 28c and the second insulating film are left for a time such that the entire thickness of the residual positive photosensitive insulating layer 28c is polished. The layer 24 is a residual positive photosensitive insulating layer 2 formed by the CMP method.
Polish for a preset time such that 8c is removed.
As a result, the planarized second insulating layer 24b is obtained.

The hardness of the residual positive photosensitive insulating layer 28c is close to that of the second insulating layer 24, and the residual positive photosensitive insulating layer 28c excessively suppresses the polishing rate of the second insulating layer 24 by the CMP method. Since it functions as a polishing suppression film, a flat second insulating layer 24 surface is obtained over the entire LSI surface. The residual positive photosensitive insulating layer 28c that has been heat-treated in the third step of FIG. 2A has increased hardness, which further increases the polishing suppression force. However, in order to act as a film for suppressing excessive polishing,
The hardness of the residual positive photosensitive insulating layer 28c is equal to that of the second insulating layer 2
It may be 4 or more, and does not necessarily have to be significantly high.

In the method of manufacturing a semiconductor device of Example 1, a positive type photosensitive insulating layer is used as the photosensitive insulating layer, and the residual photosensitive insulating layer remaining after development after the entire exposure to ultraviolet rays without a mask is excessively polished. Since the CMP polishing is performed by using it as a suppression film, it is possible to omit the mask pattern design time of the dummy wiring and the polishing stopper layer residue removing step, and planarize with a small number of steps. Further, since the positive photosensitive insulating layer 25 having a small relative permittivity ε of about 4 or less is used, the operating speed is not reduced by the residue.

Embodiment 2. 3 (a) to 3 (c) and 4 (a) to 4 (c) are process diagrams showing a method for manufacturing a semiconductor device according to a second embodiment of the invention. In FIG. 3A, reference numeral 31 is an antireflection film, which is formed on the aluminum wiring pattern 23 and emits ultraviolet light 26 from the aluminum wiring pattern 23.
This is for reducing the reflection of b (described later). 32
Is a photosensitive polyimide film which is a negative type photosensitive insulating layer corresponding to the photosensitive insulating layer, and the portion irradiated with ultraviolet light is less likely to dissolve in the developing solution.
It is formed on the No. 4 surface.

In FIG. 3 (b), the ultraviolet light 26b is the same as the ultraviolet light 26a of the first embodiment, and is applied to the negative photosensitive insulating layer 32. 37a is the third reflected light, which is the aluminum wiring pattern 23 produced by the irradiation of the ultraviolet light 26b.
It is the reflected light from the upper reflective film 31. 37b is the fourth reflected light, which is the reflected light from the first insulating layer 22 due to the irradiation of the ultraviolet light 26b. In FIG. 3C, reference numeral 32a denotes a negative photosensitive insulating layer to be irradiated, which is obtained after the negative photosensitive insulating layer 32 is irradiated with the ultraviolet light 26b. 38a is the first
The negative photosensitive insulating layer to be irradiated, which is the negative photosensitive insulating layer to be irradiated on the wiring layer 23. Reference numeral 38b denotes a second negative photosensitive insulating layer to be irradiated, which is a negative photosensitive insulating layer to be irradiated in a region where the wiring layer 23 is not provided.

In FIG. 4A, reference numeral 38c denotes a residual negative photosensitive insulating layer corresponding to the residual photosensitive insulating layer, which remains after the irradiation of the negative photosensitive photosensitive insulating layer 32a after the irradiation of the ultraviolet light 26b. It is a thing. In FIG. 4B, 2
4d is a second insulating layer after CMP polishing. Figure 3 (a)
3 (c) and FIG. 4 (a) to FIG. 4 (c), the other reference numerals are the same as those in FIG. 1 (a) to FIG. 1 (c) and FIG.
It is the same as that of (a) and FIG.2 (b).

Next, a method of manufacturing the semiconductor device according to the second embodiment will be described with reference to the manufacturing process diagrams shown in FIGS. Figure 3
In the first step shown in (a), on the aluminum wiring pattern 23 having the antireflection layer 31 formed on the first insulating layer 22 on the silicon substrate 21, the thickness of the wiring pattern is equal to or more than the thickness of the wiring pattern by a usual method. The second insulating layer 23 is formed.
Further, a negative photosensitive insulating layer 32 is formed on the second insulating layer 24. The negative photosensitive insulating layer 32 is photosensitive polyimide.

Next, in the second step shown in FIG. 3 (b),
The negative photosensitive insulating layer 32 is irradiated with ultraviolet light 26a of an excimer laser on the entire surface without using a mask. As shown in FIG. 3C, as a result of the irradiation of the ultraviolet light 26b, the aluminum wiring having a small irradiation intensity by the ultraviolet light 26b and the reflected light 37a has a small irradiation intensity by the antireflection layer 31 provided on the aluminum wiring pattern 23. The irradiated negative photosensitive insulating layer 38a on the pattern 23 is more exposed to the developing solution than the irradiated negative photosensitive insulating layer 38b on the portion without the aluminum wiring pattern 23 having a high irradiation intensity by the ultraviolet light 26b and the reflected light 37b. It becomes easy to dissolve.

Next, in the third step shown in FIG. 4 (a), when the development is performed with a developing solution for a predetermined time, the irradiated negative photosensitive insulating layer 38a on the aluminum wiring pattern 23 is first dissolved and irradiated. A portion of the negative photosensitive insulating layer 38b remains. Next, the residual negative photosensitive insulating layer 38c is heat-treated in the same manner as in Example 1 to irradiate it with the heat ray 30 to cure the residual negative photosensitive insulating layer 38c. This is to increase the mechanical strength of the residual negative photosensitive insulating layer 38c. However, the heat treatment step is not always necessary as long as it has a mechanical strength higher than a predetermined level from the beginning.

Next, in the fourth step shown in FIG. 4B, the residual negative photosensitive insulating layer 38c and the second insulating layer 2 are formed.
4 is polished by the CMP method for a predetermined time such that the residual positive photosensitive insulating layer 38c is completely polished.

The hardness of the residual negative photosensitive insulating layer 38c is close to the hardness of the second insulating layer 24, and the residual negative photosensitive insulating layer 38c acts as a film for suppressing excessive polishing. The abrasion of the insulating layer 24 is suppressed, and a flat surface is obtained. In the method for manufacturing a semiconductor device of Example 2, after the photosensitive insulating layer is formed, the overpolishing suppression film for CMP polishing is formed only by the whole surface exposure of ultraviolet rays without a mask.
Flattening can be performed with a small number of steps by omitting the mask pattern design time of the dummy wiring and the step of removing the residue of the polishing stopper layer. Further, since the antireflection film is provided on the wiring pattern 23 and the negative photosensitive insulating layer is formed on the antireflection film, a film for suppressing excessive polishing by the irradiated negative photosensitive insulating layer 38b can be formed between the wiring patterns. .

[0030]

According to the method of manufacturing a semiconductor device of the present invention, after the photosensitive insulating layer is formed on the upper portion of the wiring pattern, the entire surface is exposed to ultraviolet rays without a mask, and the residual photosensitive insulating layer remaining after development is excessively polished. Since the CMP polishing is performed as the suppressing film, the entire surface of the LSI can be planarized in a small number of steps without depending on the wiring pattern of the lower layer.

[Brief description of drawings]

FIG. 1 is a process drawing showing the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

FIG. 2 is a process chart showing the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a process drawing showing the manufacturing method of the semiconductor device according to the second embodiment of the invention.

FIG. 4 is a process drawing showing the manufacturing method of the semiconductor device according to the second embodiment of the present invention.

FIG. 5 is a cross-sectional view showing steps of a conventional method for manufacturing a semiconductor device.

FIG. 6 is a plan view showing steps of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

21 semiconductor substrate, 22 first insulating layer, 23 wiring pattern, 24 second insulating layer, 24b, 24d flattening insulating layer, 25 positive photosensitive insulating layer, 25a irradiated positive photosensitive insulating layer, 26a, 26b UV light, 27a, 27b
Reflected light, 28a, 28b Irradiated positive photosensitive insulating layer, 28c Residual positive photosensitive insulating layer, 30 Heat rays, 3
2 Negative photosensitive insulating layer, 32a Irradiated negative photosensitive insulating layer, 37a, 37b Reflected light, 38a, 38
b Irradiated negative photosensitive insulating layer, 38c Residual negative photosensitive insulating layer.

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Claims (5)

(57) [Claims] 1. A first step of forming a photosensitive insulating layer on an insulating layer formed on a wiring pattern on a semiconductor substrate,
A second step of irradiating the photosensitive insulating layer with light over the entire surface and a third step of developing the photosensitive insulating layer to form a residual photosensitive insulating layer
And a fourth step of polishing the insulating layer by a chemical mechanical polishing method using the residual photosensitive insulating layer as a suppression film that suppresses excessive polishing. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the photosensitive insulating layer is a positive photosensitive insulating layer. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the positive photosensitive insulating layer is a silsesquioxane-based material. 4. The photosensitive insulating layer is a negative type photosensitive insulating layer, and the wiring pattern has an antireflection film for reducing light reflection on the upper portion of the wiring pattern. Manufacturing method of semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 1, further comprising a heat treatment step of hardening the residual photosensitive insulating layer.