JP3450239B2 - Semiconductor memory device and word line driving method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a word line driving method, and more particularly to a large scale semiconductor integrated circuit.
The present invention relates to an (LSI) semiconductor memory device and a word line driving method.

[0002]

2. Description of the Related Art Conventionally, not only a semiconductor memory device formed into an LSI (so-called memory LSI) but also an LSI is strongly required to have a low power supply voltage, low power consumption, and high speed operation. In general, lowering the power supply voltage leads to a decrease in operating speed, but particularly in the case of a memory LSI, a decrease in the voltage amplitude of the word driver significantly reduces the operating speed.

The reason is as follows. Since the memory cell transistor forming the memory is the smallest in the chip, the threshold Vt is higher than that of other transistors. That is, the threshold Vt becomes high due to the narrow channel effect, the substrate effect, or the influence of the high-concentration channel stopper being in proximity. Further, the smaller size is more susceptible to manufacturing variations such as dimensions, and the variation in the threshold value Vt becomes larger. The word driver is required to have a high voltage equal to or higher than the maximum threshold value Vt. In other words, the voltage amplitude of the word driver greatly affects the operating speed, and the decrease in the voltage amplitude of the word driver significantly reduces the operating speed.

In order to solve this problem, therefore, a method has been proposed in which a high level output voltage of the word driver is boosted from the power supply voltage to a high voltage by utilizing a booster circuit. This method can maintain the selected word line potential high even when the power supply voltage is low, and is an effective method for speeding up. Two kinds of currents are passed through this booster circuit.
One is a minute, almost constant reverse bias leakage current flowing in the pn junction of the load. The second is a large transient current that flows when the memory is selected and the word driver operates. The former is a small and almost constant value of D
Since it is a C current, it is not a problem, but the latter is an AC current with a large current value and fluctuating, so it must be taken into consideration when designing the booster circuit.

This AC current depends on how much the selected word line transition occurs in a certain time. For example, 100
Among the changes in the address, the AC current consumption largely changes depending on whether the change accompanying the selected word line transition is 50 times or 100 times. However, since it is not possible to predict how the address will change, it is unavoidable to set the supply capability of the booster circuit to exceed the maximum load assuming a case where different word lines are continuously selected. Absent.

If the current capability is insufficient and the high level output voltage of the word driver drops, the potential of the selected word line drops. In that case, not only the reading speed is lowered, but also erroneous reading may occur. From the above, the load circuit always consumes a large amount of current regardless of the size of the load, which has been a major obstacle to reducing power consumption.

In order to solve this problem, a semiconductor memory device which monitors the level of the boosted voltage and makes the current output capability of the booster circuit variable has been conventionally proposed (RC Fosse).
t al., "Application of a High-Voltage Pumped Supply
for Low-Power DRAM "1992 Symposium on VLSI Circui
ts Digest of Technical Papers, pp.106-107).

FIG. 4 shows a circuit diagram of an example of this conventional semiconductor memory device. As shown in the figure, this conventional semiconductor memory device comprises a level monitor 1, a ring oscillator 2, and a booster unit 3. VDD is a power supply voltage, and VPP is a boosted power supply voltage. In this conventional device, VPP applied to a word line (not shown) of a dynamic random access memory (DRAM) is monitored by a level monitor 1, and when the voltage drops, the ring oscillator 2
Is operated and the booster 3 boosts VPP.

Next, the operation of this conventional device will be described in detail. The enable signal is a signal that determines the operation / non-operation of the illustrated circuit. When the enable signal changes from low level to high level, the node a goes high and the gate voltage of the transistor QM becomes VPP. The transistor QM has the same shape and size as the memory cell and is a monitoring transistor having a threshold value Vt.

Power supply voltage VPP is sufficiently high, VPP>
If (VDD + Vt), the transistor QM to which VDD is applied to the source becomes conductive, and the transistor Q1,
A current mirror circuit is formed by Q2. The current driving capability of the transistor Q2 is sufficiently larger than that of the transistors Q0 and Q0 ', and the high level voltage of the node a causes the VP until the current starts to flow in the transistor Q2.
If the P detection circuit is fast enough, the voltage of the node b at the drain of the transistor Q0 is maintained at a high level. Therefore, the output voltage OSCEN of the inverter INV is held at the low level, and the ring oscillator 2 is not activated.

However, if the power supply voltage VPP is VPP <(V
DD + Vt), the electric charge of the node b is discharged through the transistors Q0 and Q0 ′, and the inverter IN
The V output voltage OSCEN becomes high level, and the ring oscillator 2 starts oscillating operation. When the ring oscillator 2 oscillates, the output signal OS of the ring oscillator 2
The following operations are carried out by alternately repeating the low level and the high level of C.

First, the output signal OS of the ring oscillator 2
During the period when C is at the low level, since the nodes c, d, and e in the booster unit 3 have been at the low level until then, the transistors Q3 and Q4 are in the ON state, and the node f at each drain of Q3 and Q4. , G are Q3 and Q4, respectively.
Of the respective source potentials VDD and VPP. However, since the signal OSC becomes low level, the nodes c, d, and e become high level, the potential of the node f becomes 0V, and the potential of the node g becomes (VDD-Vt5) (where Vt5 is The threshold value of the transistor Q5 which is the drain).

At this time, since Q4 is in the off state, when the node f is discharged from VDD to 0 V, the voltage g also tends to fluctuate to the low level, but the transistor Q5 is turned on. (VDD-Vt
5).

Next, the output signal O of the ring oscillator 2
During the period when SC is at the high level, the nodes c, d, and e are all at the low level, and the node f is charged to VDD again. The node f is connected to the node g via the capacitor Cp.
(Q4 and Q5 drain common connection point). At this time, since the transistor Q4 is on and Q5 is off, the charge corresponding to the change of the voltage of the node f to the voltage VDD is supplied to VPP, and the potential of VPP rises. In this way, when the VPP decreases, the ring oscillator 2 starts the oscillation operation, and the output signal OSC of the ring oscillator 2 alternately repeats the low level and the high level, so that the potential of the VPP is kept constant in the booster 3. Work is done.

[0015]

However, the above-mentioned FIG.
In the conventional semiconductor memory device shown in FIG. 1, the semiconductor memory device is a high-speed operation LSI that is required to have the ability to react in a short time and increase the boosted voltage VPP because it operates after the output voltage VPP of the booster unit 3 decreases. Is extremely difficult to apply.

The present invention has been made in view of the above points,
An object of the present invention is to provide a semiconductor memory device and a word line driving method which can be easily applied to a high-speed operation LSI by detecting a word line transition and controlling a booster circuit to suppress a voltage drop in advance.

[0017]

In order to achieve the above object, the semiconductor memory device of the present invention uses a boosted voltage from a booster circuit to select a word line selected from word lines connected to a memory cell. In a semiconductor memory device supplied via a driver, a word line transition detection circuit that detects a change in the potential level of a selected word line and an output detection signal of the word line transition detection circuit are output. The counter that changes or maintains the count value and the current supply capacity that is supplied to the word driver in response to the change in the output count value are selected.
The output counter showing the continuity of the change in the potential level of the word line
And a step- up circuit that can be changed stepwise according to the input value . According to the present invention, it is possible to detect the word line transition instead of the booster circuit voltage and set the optimum current supply capability to the booster circuit without excess or deficiency according to the size of the load.

Further, according to the present invention, when the selected word line transitions are continuous, the output count value of the counter gradually changes in the first direction toward the first value in synchronization with the clock signal. When the word line selection is continued, the output count value gradually changes toward the second value in the second direction opposite to the first direction in synchronization with the clock signal, and the booster circuit changes the count value. Changes in the first direction, the supply current capacity increases in accordance with the count value, and the count value becomes the second value.
It is characterized in that the supply current capability is reduced in accordance with the count value when changing in the direction of.

Further, in order to achieve the above object, the method of the present invention is a semiconductor in which a boosted voltage from a booster circuit is supplied to a selected word line among word lines connected to a memory cell via a word driver. In a word line driving method for a memory device, a change in the potential level of a selected word line is detected, and the output count value of a counter is changed or maintained according to the continuity of the change that is the detection result . In response to the change , the current supply ability to be supplied from the booster circuit to the word driver can be changed stepwise according to the change of the output count value at least when the selected word line transition is continuous.
It is characterized by being variable so as to rise .

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a circuit system diagram of an embodiment of a semiconductor memory device according to the present invention. In the figure, of the address input signals of the memory, the X-decoded address signal A0 is latched by the address latch 11 synchronized with the clock signal CLK to become the signal A0L, and then the 2-input exclusive OR circuit (EX-OR While being supplied to one input terminal of the (Circuit) 12, the other input terminal of the EX-OR circuit 12 is directly supplied.

Although not shown in FIG. 1 for convenience of illustration, the other X decode address signals A1 to An are also latched by the corresponding address latches in the same manner as the X decode address signal A0. It is supplied to the OR circuit as well as directly to the 2-input EX-OR circuit. The output signals of a total of n + 1 address latches including the address latch 11 that latches the X decode address signals A0 to An are also supplied to the X decoder 16.

The address signals extracted from a total of n + 1 EX-OR circuits including the EX-OR circuit 12 are O
It is commonly input to the counter 14 through the R circuit 13.
The counter 14 is a synchronous counter that counts in synchronization with the clock signal CLK and outputs 0 immediately after reset. If the output signal of the OR circuit 13 is at a high level, the counter 14 performs a count-up operation up to a constant value p in synchronization with the clock signal CLK. When the output signal is at the high level, the output value p is maintained.

On the other hand, if the output signal of the OR circuit 13 is at a low level, the counter 14 performs a countdown operation in synchronization with the clock signal CLK, and after the output value becomes 0, the output signal of the OR circuit 13 becomes low. At a low level, the output value 0 is maintained.

The booster circuit 15 is a booster circuit whose supply current capability is variable, and supplies the boosted power supply voltage to the word driver 17 via the power supply line 18. That is, the potential when the word line 19 connected to the memory cell (not shown) is selected becomes the potential supplied from the booster circuit 15 to the word driver 17. The booster circuit 15 has a function of receiving the counter output value of the counter 14 and varying the current capability supplied to the word driver 17 in accordance with the counter output value.

FIG. 2 shows a circuit diagram of an embodiment of the booster circuit 15. As shown in the figure, in the booster circuit 15, two N-channel MOS type field effect transistors M1 and M2, which are diode-connected, are connected in series, and a capacitor is provided at a connection point (node N) of the transistors M1 and M2. One end of CP is connected. This capacitor C
P is the pump-up capacity. Also, the transistor M
The thresholds of 1 and M2 are Vt, respectively.

The other end of the capacitor CP is connected to the output terminal of the frequency division ratio variable circuit 21. Variable division ratio circuit 21
Is a capacitor CP that divides the input clock signal CLK.
The frequency division ratio is applied to the counter 14 shown in FIG.
It is variable according to the output count value of. Here, for example, when the counter value is the maximum value p, the above frequency division ratio is the minimum, the output signal frequency of the frequency division ratio variable circuit 21 is the highest, and when the minimum count value is 0, the frequency division ratio is the maximum. The output signal frequency of the frequency division ratio variable circuit 21 becomes the lowest. The power supply voltage VDD input to the transistor M1 is boosted by the transistor M2 and output to the VPP terminal. Here, the voltage limiter circuit for preventing excessive boosting is omitted for ease of explanation. The clock signal CLK is
It is a square wave in which a low level (GND) and a high level (VDD) are alternately repeated.

Next, the operation of the present embodiment shown in FIGS. 1 and 2 will be described with reference to the timing chart of FIG. One of X decode address signals, for example, when only the X decode address signals A0 is changed. One cycle Φ0 with the clock signal CLK shown in FIG.
In, X decode address signals A0 changes from the low level (0) to a high level (1), in the next one cycle .phi.1, that changes from the high level to the low level, shown in Figure 3 is the selected word line Thus, W <0> changes to W <1>. At this time, the EX-OR circuit 1 to which the address signal A0 and the signal A0L obtained by being latched by the address latch 11 are input
The output signal of 2 becomes a pulse.

This output signal passes through the OR circuit 13 and is shown in FIG.
Is input to the counter 14 as a pulse waveform shown in FIG. 2 and the count value is incremented from 0 to 1 in synchronization with the clock during the high level period. Although the address signal A0 has been described here, the pulse signal is ORed when one or more of the X decode address signals change.
It is taken out from the circuit 13 and inputted to the counter 14.
That is, when the selected word line changes, the counter 1
The output of 4 will be counted up as shown in FIG.

The booster circuit 15 receives the output counter value of the counter 14 and increases the current capacity supplied to the word driver 17 by one step. Here, the operation of the booster circuit 15 shown in FIG. 2 will be described. When the divided clock signal output from the variable division ratio circuit 21 is at a low level (GND), a current is supplied from VDD to the node N through the transistor M1. Flows in, and the potential of the node N becomes (VDD-V
rise to t). Then, when the divided clock signal becomes high level (VDD), coupling occurs at both ends of the capacitor CP (potential difference between both ends is (VDD-Vt)).
Since the potential of the node N exceeds VDD, the current does not flow to the VDD terminal by the action of the transistor M1 but flows toward the VPP terminal, and the VPP terminal has a maximum voltage of 2 (V
DD-Vt).

As described above, by continuously supplying the clock signal, the above-mentioned state is repeated, and the VPP terminal has a maximum of 2.
The boosted potential of (VDD-Vt) is maintained. Further, the repetition of the above state changes depending on the count value.

When the selected word line changes, the consumed AC current also increases, but if the supply current capacity is set to increase in proportion to this, the booster circuit 15 consumes an excessive current. Without doing so, the high level of the word driver 17, that is, the selected word line potential is held at a constant value.

Further, as shown in FIG. 3, when the clock is Φ1 to Φ2 and the word line transition is continuous, the word driver 17
, The supply current capacity of the booster circuit 15 increases as the output counter value of the counter 14 increases, so that the optimum consumption current and the selected word line potential are To be kept.

On the contrary, in three consecutive cycles of Φ3, Φ4, and Φ5 clocks shown in FIG. 3, the X decoder address signal A
0 is maintained at a high level and the same word line is continuously selected. In this case, the AC current consumption of the word driver 17 becomes small. In this case, the output counter value of the counter 14 is counted down as 2 → 1 → 0 as shown in FIG.
The current supply capability is lowered, and the booster circuit 15 operates so as not to consume an excessive current.

As described above, when the selected word line transition is continuous, the counter 14 performs a count-up operation. However, it is physically possible to increase the count output value infinitely and to increase the power supply capacity. It is impossible. Therefore, if the count-up is performed at a certain value or more, the count output value is kept constant after that. In FIG. 3, in the state of Φ2 → Φ3, if the count value becomes 2 or more, that is, if the change of the selected word line occurs 3 times or more consecutively, the count output value of the counter 14 remains 2.

In this case, the dimension of the booster circuit 15 may be changed so that the AC current consumption of the word line can be sufficiently supplied even if the selected word line changes three or more times in succession. Specifically, for example, the capacitor C in FIG.
It is conceivable to prepare a plurality of Ps, usually use a small capacity one, and use a large capacity one when the load becomes high.

Further, in the above-described embodiment, the same is true when the selected word line transition does not occur, that is, when the same word line is selected continuously. For example, when the counter output value becomes 0, it is maintained at 0 thereafter, and the state in which the current consumption of the booster circuit 15 is the lowest continues.

As described above, in the present embodiment, the output counter value of the counter 14 which operates to detect the word line transition and change or maintain the output value according to the magnitude of the load is supplied to the booster circuit 15. Since the optimum current capacity for supplying and supplying to the word driver 17 is set appropriately, it is possible to suppress excessive power consumption and keep the boosted voltage constant. In addition, the voltage drop is detected in advance by detecting the word line transition instead of the booster circuit voltage and controlling the booster circuit 15. Therefore, it is not necessary to react in a short time.

The booster circuit 15 in which the current capacity to be supplied changes depending on the output value of the counter can be realized by some methods other than the configuration shown in FIG. For example, a configuration is possible in which the dimensions of the transistors, resistors, and the like that form the booster circuit 15 are made variable according to the output count value of the counter 14. Both are easy to implement.

The present invention is not limited to the above-described embodiment, and for example, the transistors M1 and M2 shown in FIG. 2 are diode-connected to function as diodes, but they are functionally equivalent. Therefore, not only a diode but also a transistor having a gate to which a clock signal is input may be used and an equivalent function to that of a diode may be used, and all diode elements are included. Further, it goes without saying that the transistors M1 and M2 may be field effect transistors other than MOS transistors or bipolar transistors.

[0040]

As described above, according to the present invention,
Instead of the booster circuit voltage, the word line transition is detected and the optimum current supply capacity is set in the booster circuit according to the size of the load. Since it is necessary to determine the capacity assuming the maximum load, it is possible to prevent the phenomenon that the booster circuit operates exceeding the actual word line current consumption and consumes excessive current. The voltage can be kept constant.

Further, according to the present invention, since the voltage drop is suppressed in advance by detecting the word line transition and controlling the booster circuit, it is not necessary to react in a short time, and therefore the high speed operation is possible. It is easy to apply to a memory LSI that operates, and low voltage, low power consumption and high speed operation can both be achieved.

[Brief description of drawings]

FIG. 1 is a circuit system diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of an embodiment of the booster circuit in FIG.

FIG. 3 is a timing chart for explaining the operation of FIG.

FIG. 4 is a circuit diagram of a conventional example.

[Explanation of symbols]

11 Address latch 12 Exclusive OR circuit (EX-OR circuit) 13 OR circuit 14 counter 15 Booster circuit 16 X decoder 17 word driver 19 word lines 21 Dividing ratio variable circuit M1, M2 N-channel MOS type field effect transistor CP capacitor (pump up capacity)

Claims (5)

(57) [Claims] 1. A semiconductor memory device for supplying a boosted voltage from a booster circuit to a selected word line among word lines connected to a memory cell via a word driver, the potential level of the selected word line being changed. receiving a word line transition detection circuit for detecting a change, in response to an output detection signal of said word line transition detection circuit, a counter for changing or maintaining the output count value, a change in the output count value, supplied to the word drivers The current supply capacity of the selected word line.
In response to the output count value, which indicates the continuity of changes in
A semiconductor memory device having a step-up circuit that can be changed stepwise . 2. The word line transition detection circuit comprises a plurality of Xs.
Each decode address signals in synchronization with the separately clock signal inputs and a plurality of address latch for latching, and X de <br/> code address signal corresponding to the output signal and the output signal of said address latch The relevant X decode address
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises a plurality of logic circuits that detect a change in the output signal and a single OR circuit that performs an OR operation on the output signals of the plurality of logic circuits. 3. When the selected word line transition continues, the counter gradually changes the output count value toward the first value in the first direction in synchronization with the clock signal, and selects the same word line. , The output count value gradually changes toward the second value in the second direction opposite to the first direction in synchronization with the clock signal, and the booster circuit causes the count value to change. Changes in the first direction, the supply current capacity increases in accordance with the count value, and when the count value changes in the second direction, the supply current capacity decreases in accordance with the count value. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a configuration. 4. The boosting circuit outputs a boosted power supply voltage in response to a first diode element having one end connected to a power supply voltage and the power supply voltage from the first diode element. A second diode element connected in series to one diode element, a capacitor having one end connected to a connection point of the first and second diode elements, and an output count value of the counter at the other end of the capacitor 2. The semiconductor memory device according to claim 1, further comprising a supply unit that supplies a clock signal whose frequency changes in accordance with the above. 5. A word line driving method for a semiconductor memory device, wherein a boosted voltage from a booster circuit is supplied to a selected word line among word lines connected to a memory cell via a word driver, and the selected word is selected. detecting a change in the potential level of the line, the detection result is that depending on the continuity of change is changed or maintain the output count value of the counter, varying the output count value
Depending on the reduction, the current supply capacity supplied to the word driver from the booster circuit, at least when the selected word line transition is continuous in response to changes in the output count value stage
A method for driving a word line, which is characterized in that it is variable so as to rise.