JP3454672B2 - Real-time clock circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a real time clock circuit, and more particularly to a real time clock circuit for supplying clock data to a digital device in real time.

[0002]

2. Description of the Related Art Electronic equipment such as video equipment and video conference systems may require clock data in real time. A real-time clock (hereinafter referred to as RTC) circuit is a circuit that supplies clock data in real time.

As a conventional real-time clock circuit, there is a counter type RTC circuit using a counter and an arithmetic type RTC circuit.

FIG. 14 is a circuit diagram showing an RTC circuit of the counter type. In FIG. 14, the RTC circuit includes a second counter 11 that receives a 1 Hz clock signal and counts from 0 to 59, and a minute counter 1 that receives a carry output from the second counter 11 and counts from 0 to 59.
2. Carry output of minute counter 12 is input and 0-23
Is composed of an hour counter 13 for counting up to, and the outputs of the respective counters represent RTC data of seconds, minutes, and hours, respectively.

FIG. 15 is a circuit configuration diagram showing an RTC circuit according to a calculation method. 15, the RTC circuit includes an address counter 21 for designating an address for reading data from the RAM, a data storage RAM 22 for storing data of seconds, minutes, hours, days of the week, days, months, and years, and RTC data from the RAM 22. Determination circuit 23, selector 24 for switching the internal address and the external address from the address counter and outputting to the address of RAM 22, internal R
AM precharge signal PC and internal RAM write signal WR and external RAM precharge signal PC and external RAM
It is composed of a selector 25 which switches the write signal WR and outputs it to the RAM 22.

The determination circuit 23 outputs +1 data to the RAM 22, and the RTC data from the RAM 22 can be determined to obtain desired data.

A flag UIP indicating that the RTC operation is being performed is input to the selector 25 and the address counter 21.

The internal PC, WR and address are used for RTC calculation inside the IC, and the internal PC, WR and address are used when setting or reading data from outside the IC.

FIG. 16 is a timing chart showing the operation of the RTC circuit according to the above-mentioned calculation method.
The case where the RTC operation is performed by R and the address is shown. The external PC, WR, and address are ALL0. FIG.
As shown in, the flag U indicating that the RTC operation is in progress
If there is an IP, RAM for each time unit of seconds, minutes, and hours
The input is incremented by 1 (+1 if there is a carry-up in the previous time unit, and incremented by 0 otherwise), and written to the RAM 22 at the write timing WR.

[0010]

However, in such a conventional real-time clock circuit, RAM precharge is required for each time unit, and power consumption cannot be reduced. For example, when the operation shown in FIG. 16 is performed, 14 precharge cycles are required per second, and the power consumption becomes larger than that of the counter method.

An object of the present invention is to provide a real-time clock circuit that can reduce power consumption.

[0012]

SUMMARY OF THE INVENTION A real-time clock circuit according to the present invention has a storage means for storing real-time clock data, and a carry-out of data read from the storage means to determine at least two types of time data in time units. In the real-time clock circuit for obtaining the above, there is provided means for stopping the writing of data to the storage means when a carry does not occur during the calculation in the previous time unit.

A real-time clock circuit according to the present invention is a memory means for storing real-time clock data, and a real-time clock circuit for determining carry of data read from the memory means to obtain time data of at least two types of time units. A means is provided for stopping the supply of the precharge signal to the storage means when a carry does not occur during the calculation in the previous time unit.

The real-time clock circuit according to the present invention determines at least 2 by storing means for storing real-time clock data by address designation from the address counter and carry of data read from the storing means.
A real-time clock circuit that obtains time data of various time units includes means for stopping the operation of the address counter when no carry occurs during the calculation of the previous time unit.

The real-time clock circuit according to the present invention may be provided with means for releasing the storage means from the arithmetic processing of the time data when no carry occurs during the arithmetic operation in the previous time unit.

The real-time clock circuit according to the present invention may include a test terminal for inputting a test signal and a means for generating a carry in all time units when the test signal is input. .

In the real-time clock circuit according to the present invention, the storage means may be a dual port RAM.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION The real-time clock circuit according to the present invention can be applied to a real-time clock circuit that supplies clock data to electronic equipment.

First Embodiment FIG. 1 is a circuit diagram showing the configuration of a real-time clock circuit according to the first embodiment of the present invention.

In FIG. 1, a real-time clock circuit 100 includes an address counter 101 for designating an address for reading data from a RAM, seconds, minutes, hours, days of the week, days,
RAM1 for data storage that stores RTC data for month and year
02 (storage means), a determination circuit 103 for determining RTC data from the RAM 102, a selector 104 for switching the internal address and the external address from the address counter and outputting them to the address of the RAM 102, an internal RAM precharge signal PC and an internal RAM write signal. WR and external R
Selector 1 for switching between AM precharge signal PC and external RAM write signal WR and outputting to RAM 102
05, AND which takes AND logic of carry UP detection output from the determination circuit 103 and internal RAM write signal WR
The gate circuit 106 is composed of an AND gate circuit 107 that takes an AND logic of the internal RAM precharge signal PC and the RTC operation flag UIP.

The address counter 101 designates an address for reading data from the data storage RAM 102.

The data storage RAM 102 has an address

Every [00] to [12], seconds, minutes, hours, days of the week, days,
It stores RTC data for the month and year and outputs the addressed data. Further, the RTC data is updated and stored by the +1 (increment) data from the determination circuit 103, and the RTC data is output to the determination circuit 103.

The determination circuit 103 is a RAM 1 for data storage.
A carry determination is made based on the RTC data from No. 02 to obtain the final RTC data.

The AND gate circuit 106 is used for the decision circuit 10
AND logic of the carry UP detection output from 3 and the internal RAM write signal WR is taken, and the internal RAM write signal WR is output to the selector 105 only when there is a carry UP detection output.

As described above, in the real-time clock circuit 100 according to the present embodiment, when a carry-up detection output is newly provided in the RTC circuit section based on the arithmetic processing method including the address counter 101, the data storage RAM 102 and the determination circuit 103. Only the AND gate circuit 106 that outputs the internal RAM write signal WR is added.

The operation of the real-time clock circuit 100 configured as described above will be described below.

FIG. 2 is a timing chart for explaining the operation of the real-time clock circuit 100, which is an example when only carry UP from the second occurs. Further, the operation of UIP = "L" is omitted because it relates to the internal calculation.

As shown in FIG. 2, RTC data is obtained by arithmetic processing using a RAM, similarly to the RTC circuit according to the arithmetic processing method of the conventional example. That is, the determination circuit 103
Outputs +1 data to the data storing RAM 102, carries the carry of the RTC data from the data storing RAM 102, and obtains the final RTC data.

In the present embodiment, if carry UP (carry) does not occur during the calculation of the previous time unit (for example, seconds indicate minutes and days indicate months), the determination circuit 10 is executed.
Carry UP detection is not output from 3 and therefore internal R
The AM write signal WR is not supplied to the RAM 102 via the AND gate circuit 106 and the selector 105. Therefore, no data is written in the RAM 102,
The operation of the RAM 102 is stopped.

For example, as shown in FIG. 2, when carry UP from second occurs and carry UP from minute does not occur, RAM 10 of RAM write signal WR
2 is stopped, and the subsequent write operation is stopped. Generally, a relatively large amount of power consumption is required for the write operation of the RAM, but the write frequency is greatly reduced.

In this way, when carry-up does not occur during the calculation in the previous time unit, the data itself is not written, ie, the write operation is stopped, instead of writing the data as +0 in the RAM 102. As a result, the RAM according to the RAM write signal WR
Since the number of write operations to 102 is reduced, increase in power consumption can be suppressed.

As described above, the real-time clock circuit 100 according to the first embodiment has the address counter 101, the data storage RAM 102, and the determination circuit 10.
Since the AND gate circuit 106 that outputs the internal RAM write signal WR only when the carry UP detection output is newly provided is added to the RTC circuit section according to the arithmetic processing method of 3, the RAM write signal WR is "H". ”
The level, that is, the timing of writing data to the RAM is generated by receiving the carry of the previous time unit, and the number of times of writing to the RAM can be reduced, and the power consumption can be significantly reduced.

Second Embodiment FIG. 3 is a circuit diagram showing the configuration of a real-time clock circuit according to the second embodiment of the present invention. In the description of the real-time clock circuit according to the present embodiment, the same components as those of the real-time clock circuit shown in FIG. 1 will be assigned the same reference numerals and overlapping description will be omitted.

In FIG. 3, a real time clock circuit 200 includes an address counter 101 for designating an address for reading data from the RAM, seconds, minutes, hours, days of the week, days,
RAM1 for data storage that stores RTC data for month and year
02, a determination circuit 103 for determining RTC data from the RAM 102, a selector 104 for switching between an internal address and an external address from an address counter and outputting to an address of the RAM 102, an internal RAM precharge signal PC
And the AND logic of the carry UP detection output from the selector 105 and the determination circuit 103 which switch the internal RAM write signal WR and the external RAM precharge signal PC and the external RAM write signal WR and output to the RAM 102. AND gate circuit 1
06, A which takes an AND logic of the carry UP detection output from the determination circuit 103 and the internal RAM precharge signal PC
ND gate circuit 201, internal RAM precharge signal P
AN that takes the AND logic of C and the RTC operation flag UIP
It is composed of a D gate circuit 107.

The AND gate circuit 201 is used for the decision circuit 10
AND logic of the carry UP detection output from 3 and the internal RAM precharge signal PC is taken, and the internal precharge signal PC is output to the selector 105 only when there is a carry UP detection output.

As described above, the real-time clock circuit 200 according to the present embodiment internally operates only when the carry-up detection output is present in the RTC circuit section based on the arithmetic processing method including the address counter 101, the data storage RAM 102 and the determination circuit 103. AND gate circuit 106 for outputting RAM write signal WR and internal precharge signal P
The configuration is such that an AND gate circuit 201 that outputs C is added.

The operation of the real-time clock circuit 200 configured as described above will be described below.

FIG. 4 is a timing chart for explaining the operation of the real-time clock circuit 200, which is an example of the case where only carry UP from the second occurs. Further, the operation of UIP = "L" is omitted because it relates to the internal calculation.

As shown in FIG. 4, when carry-up is not generated during the calculation in the previous time unit, the decision circuit 103 does not output carry-up detection, and therefore the internal RAM
The write signal WR and the precharge signal PC are R via the AND gate circuits 106 and 201 and the selector 105.
Not supplied to AM 102. Therefore, the data write operation and the precharge operation are not performed on the RAM 102, and the operation of the RAM 102 is stopped.

For example, as shown in FIG. 4, when carry UP from second occurs and carry UP from minute does not occur, supply of RAM write signal WR and precharge signal PC to RAM 102 is stopped. Then, the subsequent write operation and precharge operation are stopped.

As described above, the real-time clock circuit 200 according to the second embodiment has the address counter 101, the data storage RAM 102, and the determination circuit 10.
A configuration in which an AND gate circuit 106 that outputs an internal RAM write signal WR and an AND gate circuit 201 that outputs an internal precharge signal PC are added to the RTC circuit section according to the arithmetic processing method of 3 in which a carry UP detection output is provided. Therefore, in addition to the power consumption reduction effect of the first embodiment, the power consumption can be further reduced by reducing the number of precharge operations by stopping the precharge signal PC.

Third Embodiment FIG. 5 is a circuit diagram showing the configuration of a real-time clock circuit according to the third embodiment of the present invention. In the description of the real-time clock circuit according to this embodiment, the same components as those of the real-time clock circuit shown in FIG.

In FIG. 5, the real-time clock circuit 300 includes an address counter 101 for designating an address for reading data from the RAM, seconds, minutes, hours, days of the week, days,
RAM1 for data storage that stores RTC data for month and year
02, a determination circuit 103 for determining RTC data from the RAM 102, a selector 104 for switching between an internal address and an external address from an address counter and outputting to an address of the RAM 102, an internal RAM precharge signal PC
And the AND logic of the carry UP detection output from the selector 105 and the determination circuit 103 which switch the internal RAM write signal WR and the external RAM precharge signal PC and the external RAM write signal WR and output to the RAM 102. AND gate circuit 1
06, A which takes an AND logic of the carry UP detection output from the determination circuit 103 and the internal RAM precharge signal PC
ND gate circuit 201, internal RAM precharge signal P
AN that takes the AND logic of C and the RTC operation flag UIP
It is composed of a D gate circuit 107.

The AND gate circuit 201 includes the decision circuit 10
The AND logic of the carry UP detection output from 3 and the internal RAM precharge signal PC is taken, and the internal precharge signal PC is output to the selector 105 and the AND gate circuit 107 only when the carry UP detection output is given.

Here, as the internal RAM precharge signal PC as the system clock, which is input to the address counter 101, the precharge signal PC via the AND gate circuit 201 is input.

As described above, the real-time clock circuit 300 according to the present embodiment internally operates only when the carry-up detection output is present in the RTC circuit section based on the arithmetic processing method including the address counter 101, the data storage RAM 102 and the determination circuit 103. The AND gate circuit 106 that outputs the RAM write signal WR, and the internal precharge signal PC are sent to the RAM 10 only when the carry UP detection output is generated.
2 and an AND gate circuit 201 for outputting to the address counter 101 is added.

The operation of the real-time clock circuit 300 configured as described above will be described below.

FIG. 6 is a timing chart for explaining the operation of the real-time clock circuit 300, which is an example when only carry UP from the second occurs. Further, the operation of UIP = "L" is omitted because it relates to the internal calculation.

As shown in FIG. 6, when carry-up is not generated in the calculation in the previous time unit, carry-up detection is not output from the determination circuit 103, and accordingly, the internal RAM is not detected.
The write signal WR and the precharge signal PC are R via the AND gate circuits 106 and 201 and the selector 105.
Not supplied to AM 102. Therefore, the data write operation and the precharge operation are not performed on the RAM 102, and the operation of the RAM 102 is stopped. In addition to this,
When the carry-up is not generated during the calculation in the previous time unit, the input of the precharge signal PC to the address counter 101 is also stopped.

For example, as shown in FIG. 6, when carry UP from second occurs and carry UP from minute does not occur, supply of the RAM write signal WR and the precharge signal PC to the RAM 102 is stopped. Then, the subsequent write operation and precharge operation are stopped, and the precharge signal PC to the address counter 101 is sent.
The change of the address signal disappears when the input of is stopped.

As described above, in the real-time clock circuit 300 according to the third embodiment, the AND gate circuit 106 which outputs the internal RAM write signal WR only when the carry UP detection output and the carry UP detection output are provided. RA only when there is an internal precharge signal PC
AND output to M102 and address counter 101
Since the configuration is such that the gate circuit 201 is added, in addition to the power consumption reduction effect of the first and second embodiments, it is possible to further reduce power consumption by reducing address access in the address counter 101.

Fourth Embodiment FIG. 7 is a circuit diagram showing the configuration of a real-time clock circuit according to the fourth embodiment of the present invention. In the description of the real-time clock circuit according to the present embodiment, the same components as those of the real-time clock circuit shown in FIG. 5 will be assigned the same reference numerals and overlapping description will be omitted.

In FIG. 7, a real-time clock circuit 400 includes an address counter 101 for designating an address for reading data from the RAM, seconds, minutes, hours, days of the week, days,
RAM1 for data storage that stores RTC data for month and year
02, a determination circuit 103 for determining RTC data from the RAM 102, a selector 104 for switching between an internal address and an external address from an address counter and outputting to an address of the RAM 102, an internal RAM precharge signal PC
And the AND logic of the carry UP detection output from the selector 105 and the determination circuit 103 which switch the internal RAM write signal WR and the external RAM precharge signal PC and the external RAM write signal WR and output to the RAM 102. AND gate circuit 1
06, A which takes an AND logic of the carry UP detection output from the determination circuit 103 and the internal RAM precharge signal PC
ND gate circuit 201, RTC_START from the outside
Latch 4 that latches the signal and outputs the operation flag UIP
01, AND gate circuit 10 which takes the AND logic of the internal RAM precharge signal PC and the RTC operation flag UIP
It consists of 7.

The latch 401 is composed of a NOR gate and an inverter, and latches the RTC_START signal from the outside until the carry UP detection output from the determination circuit 103 is input, and as a calculation flag UIP, the selector 105 and the AND gate circuit 107. Is output to.

As described above, the real-time clock circuit 300 according to the present embodiment is provided with RTC_START from the outside.
Latch 4 that latches the signal until the carry UP detection output is input and creates the flag UIP for the RTC operation
01 is added to the configuration.

The operation of the real-time clock circuit 400 configured as above will be described below.

FIG. 8 is a timing chart for explaining the operation of the real-time clock circuit 400, which is an example of the case where only carry UP from the second occurs.

The RTC operation when the carry-up does not occur during the time unit calculation is the same as that of the third embodiment.

In this embodiment, when carry-up is not generated during the time unit calculation, the latch 401 is reset by receiving the carry-up detection output from the determination circuit 103, and as shown in FIG. Set to "L".
Therefore, the RAM 102 is released from the RTC operation,
The time during which the RAM 102 can be accessed from the outside can be increased.

As described above, the real-time clock circuit 400 according to the fourth embodiment is provided with an RT from the outside.
Since the configuration is such that the latch 401 that latches the C_START signal until the carry UP detection output is input and creates the flag UIP for the RTC operation is added, in addition to the power consumption reduction effect of each of the above-described embodiments, externally It is possible to increase the accessible time to the RAM.

Fifth Embodiment FIG. 9 is a circuit diagram showing the configuration of a real-time clock circuit according to the fifth embodiment of the present invention. In the description of the real-time clock circuit according to the present embodiment, the same components as those of the real-time clock circuit shown in FIGS. 1 and 7 are designated by the same reference numerals, and duplicated description will be omitted.

In FIG. 9, the real-time clock circuit 500 includes an address counter 101 for designating an address for reading data from the RAM, second, minute, hour, day, day,
Dual port RAM to store RTC data of month and year
501, a determination circuit 103 for determining RTC data from the dual port RAM 501, an AND gate circuit 106 for ANDing the carry UP detection output from the determination circuit 103 and the internal RAM write signal WR, and the determination circuit 1
AND gate circuit 2 which takes AND logic of carry UP detection output from 03 and internal RAM precharge signal PC
01, a latch 401 that latches an RTC_START signal from the outside and outputs a calculation flag UIP, an internal RAM
A of precharge signal PC and RTC operation flag UIP
It is composed of an AND gate circuit 107 taking ND logic.

The dual port RAM 501 is a memory that has two input / output terminals and can be accessed independently from both ports. One port is provided with an internal RAM precharge signal PC, a RAM write signal WR and an internal address. The external RAM precharge signal PC, the RAM write signal WR and the internal address are connected to the other port.

Output of AND gate circuit 106 and AND
The output of the gate circuit 201 is the dual port RAM 50.
1 is directly connected to one port.

The operation of the real-time clock circuit 500 configured as above will be described below.

FIG. 8 is a timing chart for explaining the operation of the real time clock circuit 400.
This is an example of setting the month while P = “H”.

The basic operation of the RTC operation is similar to that of the seventh embodiment.

In the example shown in FIG. 8, a dual port RAM
One port of 501 is used for internal access, and the other port is used for external access. In this case, the month can be set by external access independently of the RTC operation by internal access, but since the minutes are being calculated internally at the timing shown in FIG.
Data other than minutes can be written normally.

As described above, since the real-time clock circuit 500 according to the fifth embodiment is constructed by using the dual port RAM 501, the circuit scale can be further reduced in addition to the effect of each of the above embodiments. Further, it becomes possible to access the RAM from the outside at an arbitrary timing.

Sixth Embodiment FIG. 11 is a circuit diagram showing the configuration of a real-time clock circuit according to the sixth embodiment of the present invention. Note that, in describing the real-time clock circuit according to the present embodiment, FIG.
Also, the same components as those of the real-time clock circuit shown in FIG.

In FIG. 9, a real-time clock circuit 500 includes an address counter 101 for designating an address for reading data from RAM, second, minute, hour, day, day,
Dual port RAM to store RTC data of month and year
601, a single port RAM 602 for storing data not related to RTC calculation, a dual port RAM 601
Circuit 103 for determining RTC data from the AND circuit, AND gate circuit 1 for ANDing the carry UP detection output from the determination circuit 103 and the internal RAM write signal WR
06, A which takes an AND logic of the carry UP detection output from the determination circuit 103 and the internal RAM precharge signal PC
ND gate circuit 201, RTC_START from the outside
Latch 4 that latches the signal and outputs the operation flag UIP
01, AND gate circuit 10 which takes the AND logic of the internal RAM precharge signal PC and the RTC operation flag UIP
It consists of 7.

The dual port RAM 601 is a memory that has two input / output terminals and can be accessed independently from both ports. One port is provided with an internal RAM precharge signal PC, a RAM write signal WR and an internal address. The external RAM precharge signal PC, the RAM write signal WR and the internal address are connected to the other port.

The single port RAM 602 is a normal RAM for storing data not related to RTC calculation,
For example, it is a RAM used in an IC.

In this embodiment, the external PC, the external WR, the external address, the output to the external, and the input from the external are configured such that one port of the dual port RAM 601 and the port of the single port RAM 602 are common. Connect to.

As described above, in the real-time clock circuit 600 according to the sixth embodiment, the input / output ports of the dual port RAM 601 for storing the RTC data and the single port RAM 602 for storing the data not related to the RTC calculation are configured in common. Therefore, it becomes possible to realize the RAM, which should originally be divided into two blocks, in one block. In this case, the input / output units of the two types of RAM share a port, and the RAM 601 for RTC calculation is further used.
Other than the above, since it is configured with a single-port RAM, in addition to the effect of the fifth embodiment, a small-scale dual-port RAM can be used, and the overall circuit scale can be further reduced. .

Seventh Embodiment FIG. 12 is a circuit diagram showing the configuration of a real-time clock circuit according to the seventh embodiment of the present invention. Note that, in describing the real-time clock circuit according to the present embodiment, FIG.
Also, the same components as those of the real-time clock circuit shown in FIG.

In the fifth embodiment, when the count UP test (evaluation) is performed, January 1, 0 to 12, 1999.
It takes about 3 billion cycles until 59 minutes 59 seconds on the 31st of the month.
Therefore, in this embodiment, by providing a TEST terminal, the number of operation cycles for testing is greatly reduced.

In FIG. 12, the real-time clock circuit 700 includes an address counter 101 for designating an address for reading data from the RAM, second, minute, hour, day, day,
Dual port RAM to store RTC data of month and year
501, determination circuit 103 for determining RTC data from dual port RAM 501, TEST terminal input and TE
AND gate circuit 70 taking AND logic with the ST signal
1, an OR gate circuit 702 that takes an OR logic between the output of the AND gate circuit 701 and the carry UP detection output from the determination circuit 103, the TEST signal or the OR gate circuit 702
AND gate circuit 106 for ANDing the carry UP detection output and the internal RAM write signal WR output from the determination circuit 103 via the TEST signal or the carry UP detection output and the internal RAM precharge signal P.
An AND gate circuit 201 that takes an AND logic with C, a latch 401 that latches an RTC_START signal from the outside and outputs an operation flag UIP, an AND gate circuit that takes an AND logic with the internal RAM precharge signal PC and the RTC operation flag UIP It is composed of 107.

The latch 401 is an external RTC_ST.
The ART signal is latched and output to the selector 105 and the AND gate circuit 107 as the operation flag UIP until the carry UP detection output from the determination circuit 103 is input, but the TEST terminal becomes "H" at the time of testing. Therefore, UIP is output until the TEST signal becomes "L".

The operation of the real-time clock circuit 700 configured as described above will be described below.

FIG. 13 shows a real time clock circuit 400.
3 is a timing chart for explaining the operation of FIG.

As shown in FIG. 13, the TEST
The time width of the TEST signal input to the terminal is fixed.

When the TEST terminal is "H", all the time units are incremented by 1 regardless of the carry-up of the previous time unit.
It is possible to test the count UP in a maximum of 99 operation cycles from January 1, 0 to December 31, 1999, 59 minutes 59 seconds.

Therefore, in addition to the effects of the fifth embodiment, the test time can be significantly reduced.

Although the present embodiment is applied to the circuit of the fifth embodiment, it goes without saying that the same method may be applied to other embodiments.

As described above, the real-time clock circuit according to each of the above embodiments has a simple circuit configuration,
It has an excellent feature that it can reduce power consumption and can be mounted inside various electronic devices.

It should be noted that in each of the above-described embodiments, R is stored in the storage means.
Although the AM is used, of course, the present invention is not limited to this, and another memory that performs the same operation may be used. Further, although the operation is performed at the rising edge of various signals, it goes without saying that the operation may be performed at the falling edge.

Further, the real-time clock circuit is
The present invention can be applied to a real-time clock circuit that supplies clock data to various electronic devices, but it goes without saying that it can also be applied to any real-time clock circuit that outputs clock data. Also,
The real-time clock circuit according to the present embodiment may be incorporated and installed inside the integrated circuit, or may be applied to an independent device.

Further, the types and number of flip-flops and gate circuits constituting the real-time clock circuit, the connection state, etc. are not limited to those in the above embodiments.

[0090]

Since the real-time clock circuit according to the present invention is provided with a means for stopping the writing of data to the storage means when a carry does not occur during the calculation in the previous time unit, the number of writing times can be reduced. Power consumption can be significantly reduced by reducing the power consumption.

Since the real-time clock circuit according to the present invention is provided with means for stopping the supply of the precharge signal to the storage means when the carry does not occur during the calculation in the previous time unit, the precharge operation is performed. By reducing the number of times, power consumption can be reduced.

Since the real-time clock circuit according to the present invention is provided with means for stopping the operation of the address counter when no carry occurs during the calculation in the previous time unit, the power consumption is reduced due to the decrease in address access. It can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a real-time clock circuit according to a first embodiment to which the present invention is applied.

FIG. 2 is a timing chart for explaining the operation of the real-time clock circuit.

FIG. 3 is a circuit diagram showing a configuration of a real-time clock circuit according to a second embodiment to which the present invention is applied.

FIG. 4 is a timing chart for explaining the operation of the real-time clock circuit.

FIG. 5 is a circuit diagram showing a configuration of a real-time clock circuit according to a third embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the real-time clock circuit.

FIG. 7 is a circuit diagram showing a configuration of a real-time clock circuit according to a fourth embodiment of the present invention.

FIG. 8 is a timing chart for explaining the operation of the real-time clock circuit.

FIG. 9 is a circuit diagram showing a configuration of a real-time clock circuit according to a fifth embodiment of the present invention.

FIG. 10 is a timing chart for explaining the operation of the real-time clock circuit.

FIG. 11 is a circuit diagram showing a configuration of a real-time clock circuit according to a sixth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a configuration of a real-time clock circuit according to a seventh embodiment of the present invention.

FIG. 13 is a timing chart for explaining the operation of the real-time clock circuit.

FIG. 14 is a circuit diagram showing a configuration of a conventional real-time clock circuit using a counter method.

FIG. 15 is a circuit diagram showing a configuration of a real-time clock circuit according to a conventional arithmetic method.

FIG. 16 is a timing chart for explaining the operation of the conventional real-time clock circuit.

[Explanation of symbols]

100, 200, 300, 400, 500, 600, 7
00 real-time clock circuit, 101 address counter, 102 data storage RAM, 103 determination circuit, 104, 105 selector, 106, 107, 20
1,701 AND gate circuit, 401 latch, 50
1,601 Dual port RAM, 602 Single port RAM, 702 OR gate circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G04G 1/00-3/00 G04F 10/00

Claims (6)

(57) [Claims] 1. A storage unit for storing real-time clock data, and a real-time clock circuit for determining carry of data read from the storage unit to obtain time data of at least two kinds of time units A real-time clock circuit comprising means for stopping writing of data to the storage means when the carry does not occur at times. 2. A storage unit for storing real-time clock data, and a real-time clock circuit for determining carry of data read from the storage unit to obtain time data of at least two kinds of time units A real-time clock circuit comprising means for stopping the supply of the precharge signal to the storage means when the carry is not generated. 3. A storage unit for storing real-time clock data by address designation from an address counter, and a real-time clock circuit for determining carry of data read from the storage unit to obtain time data of at least two types of time units. 2. A real-time clock circuit, comprising means for stopping the operation of the address counter when the carry does not occur during the calculation in the previous time unit. 4. The real-time clock circuit according to claim 1, 2 or 3, wherein when the carry does not occur during the operation of the previous time unit, the storage means is operated to process the time data. A real-time clock circuit comprising means for releasing the clock from the real-time clock circuit. 5. The real-time clock circuit according to claim 1, 2, 3 or 4, wherein a test terminal for inputting a test signal, and the digit in all time units when the test signal is being input. A real-time clock circuit comprising: means for generating a rise. 6. The real time clock circuit according to claim 1, wherein the storage means is a dual port RAM.