JP3458750B2 - Bus control device and information processing system having the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus controller suitable for use in a bus bridge connecting at least two system buses and an information processing system having the same.

[0002]

2. Description of the Related Art An example of an information processing system in which a plurality of system buses to which a plurality of store-in caches are connected is connected by a bus bridge is disclosed in Japanese Patent Laid-Open No. 11-15734, "Cache System". An outline of this information processing system will be described with reference to FIG. In the figure,
The processors (EPUs) 101 to 104 are connected to store-in caches (SICs) 111 to 114, respectively, and the SICs 101 to 104 are connected to a local bus 120. Where SIC 111-114 is E
Although it is a private cache of the PUs 101 to 104, it may generally take the form of a shared cache in which multiple EPUs are connected to one SIC. The local bus 120 is
Further, it is connected to the global bus 5 via the bus bridge (BB) 130. Physically EPU 101-104, SIC 111-11
4. The local bus 120 and the bus bridge 130 are mounted on one package and form one structural unit (central processing unit: CPU1). A plurality of packages (CPU 2) having the same configuration as the CPU 1 are connected to the global bus 5 and share the main memories (MMU) 3 to 4.

The operation of the system bus used in this information processing system will be briefly described. The local bus 120 and the global bus 5 are split transaction type buses that operate according to the same bus protocol, and are further configured so that the address bus and the data bus are separated and can be operated independently. . Among these, the operation of the command using the address bus will be described with reference to Table 2 shown in FIG. <
In Table 2>, states 1 to 5 are timing signals which are always counted in synchronization with the clock. A stage is defined in synchronization with each state, and commands can be operated by overlapping each bus cycle. For example, in the CAN stage of the preceding command, the REQ stage of the immediately following command is started. The period of states 1 to 5 is called a bus cycle. However, in an information processing system having a complicated configuration in which store-in caches are connected via a large number of buses like a conventional system, in particular, cache coherency is maintained or exclusive control such as locking is performed. The problem is that the implementation becomes very complicated. Although the above-mentioned Japanese Patent Laid-Open No. 11-15734 makes no mention of this point, the more complicated the system, the more likely it is to cause problems such as data corruption, command loss, and stalls due to logical defects (bugs).

Here, especially regarding the stall of the bus, FIG.
Will be briefly explained. FIG. 8 is an operation conceptual diagram cited for explaining the simplest example of a situation where a bus stall occurs in the information processing system having the configuration shown in FIG. In the figure, SIC 111 and 211, bus bridges 130 and 230,
The components such as the local buses 120 and 220 and the global bus 5 correspond to those in FIG. Also, in FIG. 6, elements unnecessary for the description here are omitted. Further, the command buffers 133 and 233 are buffer buffers for sending commands received from the global bus to the local bus,
The command buffers 134 and 234 are buffer buffers for sending a command received from the local bus to the global bus.

Referring to FIG. 8, first, the command buffer 23
Assuming that 3 is in a buffer full state for some reason, the command transmission from the command buffer 134 to the global bus 5 must be suppressed at this time.
(A in the figure). This is because, for example, if the command to be sent from the command buffer 134 is a memory read, the SIC211 may have the necessary data, and this command should be sent to the command buffer 233 in order to obtain that data. This is because it needs to be stored in. Command suppression is performed by CA in the conventional information processing system.
Bus bridge 230 becomes bus bridge 130 at N stage
This is done by canceling the command sent from. Eventually, the command buffer 134 will become buffer full due to subsequent commands from, for example, the SIC 111.
(B in the figure). At this time, if a command is sent from the command buffer 233 to the local bus 220, the command buffer
Since the buffer full state of 233 is released, the command transmission inhibition from the command buffer 134 is also released, and thus the buffer full state of the command buffer 134 will be released soon.

[0006]

However, here, for example, there is a problem in the logic of the bus bridge 130, and the implementation is such that all commands are sent to the local bus 120 due to the buffer full state of the command buffer 134. Assuming a case, it is possible that the buffer full state of the command buffer 134 may inhibit command transmission from the command buffer 133 to the local bus (E in the figure). As a result, the command buffer 133 becomes a buffer full state and the command buffer 234
The command transmission from SIC211 is suppressed (C in the figure), and the command buffer 234 becomes a buffer full state by the command from the SIC211 (D in the figure). By this time the command buffer 233
If the buffer full condition of the
Due to the same trouble as 130, the command transmission from the command buffer 233 is suppressed by the buffer full of the command buffer 234. In this way, all four command buffers become buffer full, and no command can be sent from any command buffer. This is the stall of the bus.

Of course, the above-mentioned example is the simplest example of the stalls that can occur in the system having such a configuration, and in fact, many occurrence patterns are considered including the case where the stalls occur in a more complicated sequence. To be However, as a situation in which a stall occurs, suppression of subsequent commands due to the buffer full state is often triggered as in the above-mentioned example. Originally, such a defect has the property that it must be solved by correcting the logic, but in the actual development work, the problem was corrected even if the logic was corrected after the problem was found on the prototype. It takes several months or more to get the LSI,
For some types of failures that can be predicted in advance, LS
It is desirable to incorporate some kind of workaround at the design stage of I. The present invention has been made in view of the above circumstances, and in a bus bridge connecting two system buses, the stall of the bus is mainly caused by a logical defect.
When a (deadlock) occurs, it is configured to detect it and avoid it, which is useful in the development and evaluation of a bus bridge. An object is to provide an information processing system having a device.

[0008]

Means for Solving the Problems] bus control apparatus according to claim 1, wherein in order to solve the above problems, an information processing system having a bus bridge for connecting at least two system bus between the bus bridge has Coman
Monitor the difference in the number of commands sent and received to the buffer
However, for the fixed cycle previously defined by the threshold,
By detecting a condition where the difference no longer changes, the bus
When a stall of the bus is detected, the buffer busy is temporarily suppressed when the stall of the bus is detected, and the reception of the command arriving via the system bus is permitted. It is characterized in that the reception of the subsequent command is suppressed by the buffer busy when the preset threshold value is exceeded so that the number of entries is smaller than the number of entries held by.

According to another aspect of the bus control device of the present invention, a buffer for storing a command received via the bus, a read pointer generation circuit for generating a read pointer of the buffer, and a write pointer generation circuit for generating a write pointer. And the read pointer and write pointer outputs are supplied, the number of commands stored in the buffer is calculated by calculating the difference between the pointer values, and a buffer busy signal that detects buffer full and suppresses subsequent command reception And a buffer busy detection circuit that detects this and the difference between the read pointer and the write pointer.
The buffer by comparing it with a first threshold defined for
The busy pointer is detected, and the read pointer and
The value of the write pointer is previously defined by the second threshold
To detect a state that does not change during a certain cycle
Stall detection circuit for suppressing the buffer busy signal
And a logical sum circuit for performing a logical sum operation of the outputs of the busy detection circuit and the stall detection circuit and outputting the result as a busy signal to the outside. Further, in the bus control device according to claim 3, the stall detection circuit includes a subtracter for calculating the difference between the pointer values supplied by the read pointer generation circuit and the write pointer generation circuit, and the stall in advance with the subtracter output. comparing the threshold set for the detection, a first comparator for outputting a signal which becomes significant when it exceeds the threshold value the difference is set, before
A second and a third comparator for detecting changes in respective values set in the read pointer and the write pointer ,
A first AND circuit for performing a logical AND operation of the outputs of the second and third comparators and setting and resetting a counter for counting a predetermined value necessary for monitoring the stall, and the counter output A fourth comparator for detecting a stall of the bus by comparing it with a predefined threshold; and a second AND operation circuit for ANDing the outputs of the first and fourth comparators. It is characterized by including. Also,
5. The bus control device according to claim 4, further comprising a flip-flop in which a mode flag that enables the stall detection is set, and which is supplied as one input of the second AND operation circuit and has a function for stall detection. It is characterized by controlling.

An information processing system according to a fifth aspect of the present invention receives a first system bus, a second system bus, and a command which arrives via the first system bus via a first bus interface. A first command buffer transmitting to the second system bus via a second bus interface under the control of a bus bridge control circuit, and a command arriving via the second system bus to the second command buffer; received via the bus interface, and a second command buffer for transmitting said through said first bus interface under the control of the bus bridge control circuit to the first system bus, said first and second That of
Number of commands sent and received for each command buffer
The constant cycle that monitors the difference between
By detecting a condition where the difference remains unchanged during
The stall of the first and second system buses is detected,
When the stall of the system bus is detected, the buffer busy is temporarily suppressed to allow the reception of the command from either one of the system buses, and the difference in the number of transmission / reception of the command is the first / second. And a bus bridge control circuit that inhibits reception of a subsequent command due to the buffer busy when the number of entries exceeds a preset threshold value so as to be smaller than the number of entries of the command buffer.

In the above-mentioned structure, the present invention is a bus bridge connecting two system buses, and the bus is stalled (deadlock) mainly due to a logical defect.
When an error occurs, it is detected, and a means for avoiding it is added, and the evaluation mode useful for development / evaluation is provided. The stall detection circuit detects the stall of the bus by monitoring the registration and reading in the command buffer, and in this case, temporarily suppresses the buffer busy signal so that the command can be accepted from the bus. In order to allow this additional command to be accepted, the stall detection circuit monitors the number of commands stored in the command buffer, and when this exceeds a preset threshold value that is less than the number of entries in the command buffer. The buffer busy signal suppresses the reception of subsequent commands from the bus. In this way, the subsequent command is forcibly accepted when it is not registered or read in the command buffer for a certain period of time, so it may occur when the subsequent command cannot be received due to buffer busy. You can avoid bus stalls. This makes it possible to continue evaluation without interruption until a new LSI is acquired, for example, when a problem occurs in the evaluation of a device prototype. Further, since the function realized by the present invention can be disabled by using the mode flag, the function of the present invention is realized only when a logical defect occurs in the trial evaluation of the device, and the normal operation is not performed. It has no effect.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention, in which only the periphery of a bus bridge is extracted and shown in the information processing system of the present invention. In the figure, a local bus 120, a global bus 5, and a bus bridge 130 correspond to the elements of FIG. 6 described in the section of the prior art. Further, the local bus interface 131 is an interface circuit with the local bus 120, the global bus interface 132 is an interface circuit with the global bus 5, and the command buffer 133 is a command received from the global bus 5 and sent to the local bus 120. Buffer buffer, as well as the command buffer 13
Reference numeral 4 is a buffer buffer for storing commands received from the local bus 120 and sent to the global bus 5. The bus bridge control circuit 135 is a control circuit that controls the overall operation of the bus bridge 130 described below. Further, in order to maintain the cache coherency of the store-in cache connected to the local bus 120, the bus bridge 130 holds a copy of the tag of the store-in cache in the CTAG memory 136. In the figure,
The flow of commands and data is illustrated by arrows.

FIG. 2 is a block diagram showing a more detailed structure around the command buffer 134. In the figure, a buffer 301 is a buffer that stores a command received from a local bus. This buffer is a ring buffer having a capacity of 8 words, and its read / write pointer is supplied by the read pointer generation circuit 302 and the write pointer generation circuit 303. The update operation of the read pointer and the write pointer is controlled by a control signal (not shown) from the bus bridge control circuit 135. In addition, the read pointer generation circuit 302 and the write pointer generation circuit 303
Is output from the busy detection circuit 304 and the stall detection circuit 305.
Entered in. The busy detection circuit 304 obtains the number of commands stored in the buffer 301 by calculating the difference between the write pointer and the read pointer, and if the buffer is full, the subsequent command reception is suppressed.
Output a busy signal (B_Busy). Stall detection circuit 305
Monitors the operation of the buffer 301 and outputs a busy signal (S_Busy) as necessary. Details of this circuit will be described later using FIG. The OR circuit 306 is a stall detection circuit for the busy signal (B_Busy) from the busy detection circuit 304.
The logical sum of (S_Busy) is sent to the bus bridge control circuit as a busy signal (Busy).

Next, referring to the block diagram shown in FIG.
Details of the stall detection circuit 305 will be described. Referring to the figure, first, the values of the read pointer and the write pointer input from the read pointer generation circuit 302 and the write pointer generation circuit 303 are input to the subtractor 319, and the difference between the write pointer and the read pointer is obtained. This value matches the number of commands stored in the buffer 301. On the other hand, the flip-flop (F / F) 321 has a 3-bit capacity, and the threshold value for transmitting the S_Busy signal is stored therein. This value can be set by an operation from outside the LSI when the LSI is initialized. This difference value and F /
The value stored in F 321 is compared by the comparator 320, and if the difference value is greater than or equal to the threshold value, the comparator 320 outputs a “true” value. Needless to say again, the reason why such a threshold check is necessary is to make a space in the entry of the buffer 301 in order to forcefully accept the subsequent command when detecting the stall. This is because it is necessary. Therefore, it should be noted that when the stall detection circuit 305 is functioning, the apparent number of entries in the buffer 301 appears smaller than the actual number of entries, and the system performance is slightly reduced. This function should be used only for the purpose of not interrupting evaluation by the prototype until the logic modified LSI is obtained when a logic problem that causes a stall occurs.

On the other hand, the inputs from the read pointer generation circuit 302 and the write pointer generation circuit 303 are F / F 3 respectively.
11 and F / F 312 are once stored and compared with the original value by the comparators 313 and 314. This circuit is a differentiating circuit that outputs "true" when the input value changes. This output is
It is input as a set / reset signal to the counter 316 through the AND circuit 315. Counter 316 is a 32-bit wide counter, the size of which is chosen to be large enough to monitor bus stalls. The stall of the bus is detected by the comparator 318 outputting "true" when the value of the F / F 317 storing the threshold value becomes equal to the value of the counter 316. FIG. 4 shows the operation of the counter 316 as <Table 1>. As shown in <Table 1>, the counter 316 starts the cant when the input from the AND circuit 315 is “true” and the input from the comparator 318 is “false”.
When the input from the circuit 315 is "false" or when the AND circuit 31
Both the input from 5 and the input from comparator 318 are “true”
Reset if. The outputs of the comparator 320 and the comparator 318 are output as a busy signal (S_Busy) via the AND circuit 322. Stored in the F / F 323 is a mode flag that determines whether to enable the function of the stall detection circuit 305. When this value is “true”, the output of the AND circuit 322 is valid, When it is "false", it is always "false" (the stall detection circuit does not operate).

The configurations of the local bus interface 131, the bus bridge control circuit 135, the global bus interface 132, and the CTAG memory 136 are well known and have no direct relation to the gist of the present invention, and therefore detailed description thereof will be omitted.
Further, in the embodiment of the present invention, the buffer 301 has been described as a ring buffer, but a shifter may be used instead. In this case, it is necessary to change the configurations of the read pointer generation circuit, the write pointer generation circuit, etc., but it is easy to realize the same functions as the busy detection circuit 304 and the stall detection circuit 305. Also, in the direction of sending the command received from the global bus 5 to the local bus 120, the command buffer 1
It is possible to monitor the buffer full state by making 33 the same circuit configuration as the command buffer 134.

FIG. 5 is a timing chart cited for explaining the operation of the embodiment of the present invention. From top to bottom,
(a) Bus cycle, (b) Bus command, (c) Difference between write pointer and read pointer, (d) B_Busy signal, (e) Counter 316 output, (f) S_Busy signal, (g) Busy signal Show. Hereinafter, the operation of the bus bridge shown in FIGS. 1 to 3 will be described in detail with reference to the timing chart shown in FIG. In the figure, each bus cycle is represented by states 1 to 5 in Table 1 described in the section of the description of the prior art.
Refers to the period. When the bus command (Bus_CMD) is transmitted in synchronization with the bus cycle, the bus bridge receives it and stores it in the command buffer 301. This operation is performed by the write instruction signal (not shown) from the bus bridge control circuit 135 to the command buffer 301 and the read pointer generation circuit 30.
2 and a control signal to the write pointer generation circuit 303. The number of commands stored in the command buffer 301 is represented by "WP-RP" in the figure.

According to the timing chart shown in FIG. 5,
Command Bus_CMD from bus cycle l to l + 2
When ("5" to "7") is sent, the command is stored in the buffer 301 with a delay of one bus cycle, and the write pointer is updated. Before and after this, unless a command is sent from the buffer 301 to the global bus 5, only the write pointer is incremented by 1, and the value of WP-RP is incremented by 1 (WP in the figure).
-RP 5, 6, 7). The output (S_Busy) of the stall detection circuit is
In the bus cycle l + 3, the value of WP-RP exceeds the threshold value (7 is assumed here) stored in the F / F 321, so that the value is “true (H)”. The value of the counter 316 (Count in the figure) has been reset up to this time and is “0”, but at the bus cycle l + 4, the values of the read pointer and the write pointer do not change from those of the immediately preceding bus cycle. Is updated to +1. When this value reaches the threshold of F / F317 (assuming that "n" is stored here) in bus cycle m + 1, the value of S_Busy is suppressed by the output of comparator 318 for only one bus cycle.
("False" is output). B_Busy is a busy detection circuit 304
This is a busy (buffer full) signal of the buffer 301 output by WP-RP. It is "true (H)" when WP-RP is "8", and "false" otherwise.
(L) ”. Bus_CMD“ 8 ”is sent out by S_Busy being suppressed for only one cycle in bus cycle m + 1 and stored in buffer 301. As a result, WP-RP = in bus cycle m + 2. 8 and B_Busy becomes “true”.

As described above, the present invention is a means for detecting and avoiding a bus stall (deadlock) caused mainly by a logical defect in a bus bridge connecting two system buses. Is added, and it is equipped with it as a useful evaluation mode during development and evaluation. The stall detection circuit detects the stall of the bus by monitoring the registration and reading in the command buffer, and in this case, temporarily suppresses the buffer busy signal so that the command can be accepted from the bus.
In order to allow this additional command to be accepted, the stall detection circuit monitors the number of commands stored in the command buffer, and when this exceeds a preset threshold value that is less than the number of entries in the command buffer. The buffer busy signal suppresses the reception of subsequent commands from the bus. In this way, the subsequent command is forcibly accepted when it is not registered or read in the command buffer for a certain period of time, so it may occur when the subsequent command cannot be received due to buffer busy. You can avoid bus stalls. This makes it possible to continue evaluation without interruption until a new LSI is acquired, for example, when a problem occurs in the evaluation of a device prototype.

[0020]

As described above, according to the present invention, by providing means for tentatively avoiding a logical defect, when a defect occurs in the trial evaluation of the device,
The evaluation can be continued without interruption until a new LSI is obtained. Further, by detecting the operation of the read pointer and the write pointer of the command buffer, it is detected that a stall has occurred, and when such a stall occurs, further subsequent commands are accepted, so that the command buffer full state is temporarily The stall can be canceled. Further, since the function realized by the present invention can be disabled by the mode flag, the evaluation work can be performed by using the function of the present invention only when a logical defect occurs in the trial evaluation of the device. Does not affect the operation of.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing details around a command buffer in FIG.

3 is a block diagram showing an internal configuration of a stall detection circuit in FIG.

FIG. 4 is a table format showing the operation of the counter in FIG.
It is the figure shown with>.

FIG. 5 is a timing chart quoted for explaining the operation of the embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional information processing system.

FIG. 7 is a diagram showing an operation of a bus command in a conventional information processing system in a table format <Table 2>.

FIG. 8 is a system operation conceptual diagram cited for explaining a schematic operation of a bus stall in a conventional information processing system.

[Explanation of symbols]

5 ... Global bus, 120 ... Local bus, 131 ... Local bus interface, 132 ... Global bus interface, 133 ... Command buffer, 134 ... Command buffer, 135 ... Bus bridge control circuit, 301 ... Buffer, 302
... Read pointer generation circuit (RP), 303 ... Write pointer generation circuit (WP), 304 ... Busy detection circuit, 305 ... Stall detection circuit, 306 ... OR circuit, 311 (312) ... Flip-flop (F / F), 313 ... Second comparator, 314 ... Third comparator, 3
15 ... First AND circuit (AND), 316 ... Counter, 317 (32
1)… Flip-flop (F / F), 318… Fourth comparator, 3
20 ... First comparator, 322 ... Second AND circuit (AND), 32
3 ... Mode flip-flop

Continuation of front page (56) Reference JP-A-1-241660 (JP, A) JP-A-4-150436 (JP, A) JP-A-5-314061 (JP, A) JP-A-6-332867 (JP , A) JP-A-6-236329 (JP, A) JP-A-10-312359 (JP, A) JP-A-10-79744 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB) Name) G06F 13/36 310

Claims (5)

(57) [Claims] 1. An information processing system having a bus bridge for connecting system buses to each other, a command buffer for the command buffer of the bus bridge.
Monitor the difference between the number of incoming and outgoing
The above condition will not change during a certain cycle
By detecting the stall of the bus by detecting it, the buffer busy is temporarily suppressed when the stall of the bus is detected, and the reception of the command arriving via the system bus is permitted, and the number of the transmission and reception of the command. The bus controller suppresses the reception of a subsequent command due to the buffer busy when a threshold value set in advance so that the difference is smaller than the number of entries in the command buffer is exceeded. 2. A buffer for storing a command received via a bus, a read pointer generation circuit for generating a read pointer of the buffer, a write pointer generation circuit for generating a write pointer, and a read pointer and a write pointer output. The number of commands stored in the buffer is calculated by calculating the difference between the two pointer values supplied, and a buffer busy signal that detects the buffer full and suppresses subsequent command reception is generated. Predefine the detection circuit and the difference between the read pointer and the write pointer
Buffer busy by comparing with a first threshold
Is detected, the read pointer and the write are further detected.
The pointer value is a constant value that is defined in advance by the second threshold.
By detecting a state that does not change during the cycle,
A bus control device comprising: a stall detection circuit for suppressing a buffer busy signal; and a logical sum circuit for performing a logical sum operation of the outputs of the busy detection circuit and the stall detection circuit and outputting the result as a busy signal to the outside. 3. The stall detection circuit is set in advance for stall detection with a subtracter that calculates the difference between the pointer values supplied by the read pointer generation circuit and the write pointer generation circuit, and the subtracter output. that threshold are compared, and a first comparator for outputting a signal which becomes significant when it exceeds the threshold value the difference is set, the Li
To monitor the stall by performing a logical product operation of the outputs of the second and third comparators and the second and third comparators that detect changes in the respective values set in the write pointer and the write pointer . A first AND circuit that sets and resets a counter that counts a predetermined value necessary for the above, and a fourth comparator that detects the stall of the bus by comparing the counter output with the predefined threshold value. 3. The bus control device according to claim 2, further comprising: a second AND operation circuit for ANDing the outputs of the first comparator and the fourth comparator. 4. A flip-flop having a mode flag set to enable the stall detection is further provided, and the flip-flop is supplied as one input of the second AND operation circuit to control the function for stall detection. The bus control device according to claim 3. 5. A first system bus, a second system bus, and a command arriving via the first system bus are received via a first bus interface and controlled by a bus bridge control circuit. A first command buffer which is transmitted below to the second system bus via a second bus interface, and a command which arrives via the second system bus is received via the second bus interface. A second command buffer for transmitting to the first system bus via the first bus interface under the control of the bus bridge control circuit, and the first and second command buffers.
Monitor the difference in the number of command transmissions and receptions and set the threshold in advance.
The difference does not change during a certain fixed cycle.
The first and second system buses by detecting the status
Of the system bus is detected, the buffer busy is temporarily suppressed when the stall of the system bus is detected, and the reception of the command from either one of the system buses is permitted. And a bus bridge control circuit for suppressing reception of a subsequent command due to the buffer busy when a threshold value set in advance so as to be smaller than the number of entries held by the first and second command buffers is exceeded. Information processing system.