JP3459130B2 - Current switch circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current switch circuit used in a device for converting digital data into an analog signal at high speed, which is represented by a video digital-analog converter.

[0002]

2. Description of the Related Art In a conventional current switch circuit, PMOS transistors are connected between a power supply and ground and between a power supply and an output terminal, and gates of these two PMOS transistors receive a first digital signal and a digital signal, respectively. , A second digital signal obtained by inverting the first digital signal via an inverter is input and driven.

[0003]

However, in the circuit having the above configuration, since the first digital signal and the second digital signal which is the inverted signal of this signal are used, the delay due to the two signals causes the delay. There was a problem that kyu noise was generated. Further, due to this noise, a conversion error becomes large, which makes it difficult to operate at high speed.

[0004]

According to a first aspect of the present invention, there is provided a current switch circuit comprising: a first potential node to which a first potential is applied; a second potential node to which a ground potential is applied; an output terminal; A first transistor of the first conductivity type, one end of which is connected to the first potential node and whose gate is biased to a constant potential, and one end of which is connected to the first transistor and whose gate is connected to the ground potential Second of the first conductivity type
Transistor, the second transistor and the second transistor
A third transistor of a second conductivity type complementary to the first conductivity type connected to a potential node; a first conductivity type connected to the first transistor and the output terminal; And a fourth transistor, wherein a single control signal is applied to the gates of the third and fourth transistors.

According to a second aspect of the present invention, a current switch circuit has a first potential node to which a first potential is applied, a second potential node to which a ground potential is applied, an output terminal, and one end of the first potential node. And a first transistor of a first conductivity type whose gate is biased to a constant potential;
Second transistor of the first conductivity type, one end of which is connected to the second transistor and the gate of which is connected to the ground potential, and the first conductivity type which is connected between the second transistor and the second potential node. Current switch circuit having a third transistor of a second conductivity type complementary to the second type, a first transistor, and a fourth transistor of a first conductivity type connected between the first transistor and the output terminal. Therefore, the first control signal is applied to the gate of the third transistor, and the second control signal of the intermediate potential level of the amplitude of the first control signal is applied to the gate of the fourth transistor. It is characterized by

A current switch circuit according to a third aspect of the present invention is the same as the circuit according to the first aspect of the present invention, which is a charge storage means having one end connected to the output terminal, and the inverted signal of the control signal applied to the other end. The present invention is characterized in that a charge accumulating means is installed.

Here, the first potential is, for example, a power supply potential. Further, the first conductivity type transistor is, for example, a P-channel type transistor, and the second conductivity type transistor is, for example, an N-channel type transistor. Furthermore, the electrification storage means is, for example, a capacitor.

[0008]

In the circuit structure, since the single control signal is applied to the gates of the third and fourth transistors, the signal is not delayed and the skew noise can be prevented from occurring.

If the fourth transistor is driven by the second control signal having the same phase as the control signal and a smaller amplitude, the output overshoot can be reduced.

Further, since a capacitor having the same capacitance as the gate-drain capacitance of this transistor and having the inverted signal of the control signal applied thereto is attached to one end of the fourth transistor, output overshoot can be reduced.

[0011]

First Embodiment FIG. 1 shows a current switch circuit according to the first embodiment of the present invention. The configuration of this current switch circuit will be described below. The source electrode of the P-type MOS transistor (hereinafter referred to as PMOS) P10 is connected to the power supply potential node VDD, and the gate electrode is biased to a constant potential level. The source electrode of PMOSP11 is PMOSP10
, And the gate electrode is connected to the ground potential node GND. The drain electrode of the N-type MOS transistor (hereinafter referred to as NMOS) N11 is PM
The source electrode is connected to the drain electrode of OSP11.
It is connected to the ground potential node GND. PMOSP1
The source electrode of 2 is connected to the drain electrode of the PMOS 10, and the drain electrode is connected to the output terminal OUT. The digital signal vin is input to the gate electrodes of the NMOS N11 and the PMOS P12. A resistor R is connected between the output terminal OUT and the ground potential node GND.

Next, the operation of this current switch circuit will be described. Since the gate electrode of the PMOS P10 is biased to a constant potential, the weighted current io from the drain electrode of the PMOS P10 and the PMOS P11 is generated.
Is supplied to the node n which is the connection point of the. PMOSP1
The gate electrode of No. 1 is connected to the ground potential node GND and is therefore in a conductive state. This PMOS P11
Has a function of preventing the fluctuation of the current io at the node n. Here, the digital signal is at a high level (hereinafter, H
Level), NMOSN11 is conductive, PMOS
P12 becomes non-conductive. Therefore, the current io is PM
It flows into the ground potential node GND through OSP11 and NMOSN11. Further, when the digital signal is low level (hereinafter, referred to as L level), the NMOS N11 is non-conductive and the PMOS P12 is conductive. Therefore, the current i
o is supplied to the output terminal OUT via the PMOS P12. At this time, a voltage corresponding to the current io is generated across the resistor R, and this voltage becomes an analog signal.

As described above, according to the current switch circuit of the first embodiment of the present invention, there are two options for selecting whether to pass the current io to the ground potential node or to obtain it as the output current at the output terminal OUT. Switching element (NMOSN1
1 and PMOSP12) to a single digital signal vin
Can be controlled with. Therefore, it is possible to reduce the skew noise that occurs when controlling with two signals. Furthermore, the reduction of noise enables high-speed operation.

[0014]

Second Embodiment FIG. 2 shows a current switch circuit according to the second embodiment of the present invention. The configuration of this current switch circuit will be described below. The same components as those in FIG. 1 are designated by the same reference numerals,
The description is omitted. The source electrode of the PMOSP22 is
It is connected to the drain electrode of the PMOS P10, and the drain electrode is connected to the output terminal OUT. This PMOS
The reference potential Vref is input to the gate electrode of N22. Here, the reference potential Vref is the digital signal v
It is a constant potential that takes an intermediate potential level of the amplitude of in (potential difference between H level and L level). Next, the operation of this current switch circuit will be described. Also here, in order to avoid a duplicate description with the circuit operation of FIG. 1, an operation different from that of the first embodiment will be described.

When the digital signal vin is at the H level, that is, when the digital signal vin has a higher potential than the reference voltage Vref, a constant potential is supplied to the node n (the node n is kept at a constant potential). Is conduction, P
MOSP22 is almost non-conductive. Therefore, the current i
o flows into the ground potential node GND via the PMOS P11 and the NMOS N11. Also, the digital signal v
When in is at L level, that is, when the digital signal vin has a lower potential than the reference voltage Vref, conversely, the NMOS N11
Is almost non-conductive, and the PMOS P22 is in a conductive state. Therefore, the current io is output to the output terminal OU via the PMOS P22.
Supplied to T. At this time, a voltage corresponding to the current io is generated across the resistor R, and this voltage becomes an analog signal.

As described above, in the current switch circuit according to the second embodiment of the present invention, the two switching elements for selecting whether to pass the current io to the ground potential node GND or obtain it as the output current at the output terminal OUT. (NMOSN
11 and the PMOSP22) are digital signals v
It was driven by the reference potential Vref which takes an intermediate potential level between in and the amplitude of the digital signal. Therefore, the gate-source capacitance of the PMOS P22 is less likely to change, and output overshoot can be reduced.

The reference potential Vref may be a signal having the same phase as the digital signal and a smaller amplitude than the digital signal, instead of the constant potential, but the constant potential is more effective.

[0018]

[Third Embodiment] FIG. 3 shows a current switch circuit according to a third embodiment of the present invention. The configuration of this current switch circuit will be described below. The same components as those in FIG. 1 are designated by the same reference numerals,
The description is omitted. One end a of a capacitor (charge storage means) C is connected to the drain electrode of the PMOS P12. This capacitor has a capacitance equal to the gate-drain capacitance of the PMOS P12, and the inverted signal (-vin) of the digital signal vin is applied to the terminal b which is not connected to the PMOS P12.

Next, the operation of this current switch circuit will be described. Also here, in order to avoid a duplicate description with the circuit operation of FIG. 1, an operation different from that of the first embodiment will be described.

When the digital signal vin is at H level, NM
The OSN 11 becomes conductive and the PMOS P12 becomes non-conductive. Therefore, the current io becomes equal to the PMOSP11 and NMO.
It flows into the ground potential node GND through SN11. Further, when the digital signal vin is at L level, the NMOSN1
1 becomes non-conductive, PMOS P12 becomes conductive, and the current i
o is supplied to the output terminal OUT via the PMOS P12. At this time, the inverted signal (-vin) of the digital signal vin is applied to one end b of the capacitor C.

Next, the function of the capacitor C will be described with reference to FIGS. 4 and 5. As shown in FIG.
In the PMOS, a gate-drain capacitance cgs and a gate-source capacitance cgs are generated due to the potential difference between the gate g and the drain d and the potential difference between the gate g and the source s. Here, the signal input to the gate is
When changing the rising / falling speed at 50MHz or more and at a high speed, gate-gate as shown in Fig. 5 (i).
A cgd (csg) influence dash voltage is generated through the drain capacitance (or the gate-source capacitance).
In this case, an abnormal potential change may occur in the drain (source) of the PMOS.

However, as shown in FIG.
If a capacitor C having a capacitance equal to the gate-drain capacitance of the PMOS P12 and receiving the inverted signal (-vin) of the digital signal vin is connected to the drain electrode of S12, as shown in FIG. cg by vin
When the s-effect dash voltage occurs, a dummy dash voltage occurs. Therefore, a dummy dash current in the opposite direction to the cgd-affected dash current caused by vin is generated,
These currents cancel each other out.

As described above, in the current switch circuit according to the third embodiment of the present invention, PM is connected to the drain electrode of the PMOS 12.
Since the capacitor C having a capacitance equal to the gate-drain capacitance of the OSP 12 and having the inverted signal (-vin) of the digital signal vin applied thereto is connected, a dummy dash current in the opposite direction to the cgd influence dash current is generated. ,
These currents can be canceled by each other, and output overshoot can be reduced.

[0024]

[Fourth Embodiment] FIG. 6 is a block diagram of a digital-analog converter (hereinafter referred to as a DAC) showing a fourth embodiment of the present invention. The DAC 1 is composed of a register 2, a decoder 3, and a current switch unit 4. The current switch 4 is composed of a plurality of current switch circuits 5.

The operation of this DAC will be described. nb
The digital signal of it is input to the register 2, and the signal is decoded into mbit. Further, the mbit decode signal is input to the current switch unit 4 composed of x current switch circuits, the current switch circuit 5 corresponding to the nbit data is selected, and the current corresponding to the digital signal is applied to the current switch unit 4. It is output from 4.

A high conversion speed of 200 M to 300 MHz is required for such a DAC, especially for a large CRT monitor such as WS or PC.

Therefore, if the current switch circuit described in the first to third embodiments is used for the DAC shown in FIG.
It is possible to reduce the error of C and enable high speed operation.

[0028]

As described above in detail, according to the current switch circuit of the first embodiment of the present invention, whether the current io is passed to the ground potential node or is obtained as the output current at the output terminal OUT. , And the switching elements (NMOS N11 and PMOS P12) can be controlled by a single digital signal vin. Therefore, it is possible to reduce the skew noise that occurs when controlling with two signals. Furthermore, the reduction of noise enables high-speed operation.

Further, in the current switch circuit of the second embodiment of the present invention, two switching elements (NMOSN1) for selecting whether to pass the current io to the ground potential node GND or obtain it as the output current at the output terminal OUT are selected.
1 and the PMOSP22) are digital signals vi
It was driven by a reference potential Vref that takes an intermediate potential level between n and the amplitude of the digital signal. Therefore, the gate-source capacitance of the PMOS P22 is less likely to change, and output overshoot can be reduced.

Furthermore, in the current switch circuit according to the third embodiment of the present invention, the drain electrode of the PMOS 12 is connected to the PMOS.
Has a capacitance equal to the gate-drain capacitance of P12,
Since the capacitor C to which the inverted signal (-vin) of the digital signal vin is applied is connected, a dummy dash current in the opposite direction to the cgd influence dash current is generated, and these currents can be canceled by each other, and the output Overshoot can be reduced.

[Brief description of drawings]

FIG. 1 is a current switch circuit according to a first embodiment of the present invention.

FIG. 2 is a current switch circuit according to a second embodiment of the present invention.

FIG. 3 is a current switch circuit according to a third embodiment of the present invention.

FIG. 4 is an explanatory diagram of MOS gate-source and gate-drain capacitances.

[FIG. 5] Dash voltage explanatory diagram

FIG. 6 is a block diagram of a DAC showing a fourth embodiment of the present invention.

[Explanation of symbols]

PMOS 10, 11, 12, 22 ... P-type MOS transistor NMOS 11 ... N-type MOS transistor VDD ... Power supply potential GND ... Ground potential OUT ... Output terminal R ... Resistor C ... Capacitor 1 ... Digital / analog converter 2 ... Register 3 ... Decoder 4 ... Current switch unit 5 ... Current switch circuit

─────────────────────────────────────────────────── ─── Continued Front Page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 17/00 H03M 1/74

Claims (3)

(57) [Claims] 1. A first potential node to which a first potential is applied, a second potential node to which a ground potential is applied, an output terminal, and one end of which is connected to the first potential node and whose gate has a constant potential. A first transistor of a first conductivity type biased to the first transistor, a second transistor of a first conductivity type having one end connected to the first transistor and a gate connected to a ground potential, and the second transistor A third conductivity type third complementary to the first conductivity type connected between the transistor and the second potential node.
Of the third transistor and the first transistor, and a fourth transistor of the first conductivity type connected between the first transistor and the output terminal. A current switch circuit, wherein a single control signal is applied to the gate. 2. A first potential node to which a first potential is applied, a second potential node to which a ground potential is applied, an output terminal, one end of which is connected to the first potential node, and a gate of which has a constant potential. A first transistor of a first conductivity type biased to the first transistor, a second transistor of a first conductivity type having one end connected to the first transistor and a gate connected to a ground potential, and the second transistor A third conductivity type third complementary to the first conductivity type connected between the transistor and the second potential node.
A current switch circuit comprising: a first transistor and a fourth transistor of a first conductivity type connected between the first transistor and the output terminal; 1. The current switch circuit, wherein the first control signal is applied, and the second control signal having an intermediate potential level of the amplitude of the first control signal is applied to the gate of the fourth transistor. 3. The current switch circuit further includes a charge storage unit having one end connected to the output terminal, and the other end having a charge storage unit to which an inverted signal of the control signal is applied. The current switch circuit according to claim 1, wherein: