JP3460798B2 - Elliptic product-sum calculation method, elliptic-product-sum calculation device, and recording medium storing elliptic-product-sum calculation program - Google Patents
Elliptic product-sum calculation method, elliptic-product-sum calculation device, and recording medium storing elliptic-product-sum calculation programInfo
- Publication number
- JP3460798B2 JP3460798B2 JP34659198A JP34659198A JP3460798B2 JP 3460798 B2 JP3460798 B2 JP 3460798B2 JP 34659198 A JP34659198 A JP 34659198A JP 34659198 A JP34659198 A JP 34659198A JP 3460798 B2 JP3460798 B2 JP 3460798B2
- Authority
- JP
- Japan
- Prior art keywords
- order
- executed
- case
- calculation
- ruiha
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Complex Calculations (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は、暗号技術などに用
いられる、素体Fp上の3次関数の複数の点の楕円積和
演算を高速に実現する方法及び装置、並びに、そのプロ
グラムを記録した記録媒体に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for realizing a high-speed elliptic product sum operation of a plurality of points of a cubic function on a field F p , which is used in cryptography, and a program therefor. The present invention relates to a recorded recording medium.
【0002】[0002]
【従来の技術】楕円暗号では、素体(有限体)上の楕円
曲線EP 2. Description of the Related Art In elliptic cryptography, an elliptic curve E P on a prime field (finite field)
【0003】[0003]
【数7】 [Equation 7]
【0004】上の整数点(x,y)の解集合をメッセー
ジ空間とみなす。つまり、楕円曲線上の点を有限の整数
値(0以上p未満)に限定し、演算はこの上限値pで割
った余りとする(mod演算)。A solution set of the above integer points (x, y) is regarded as a message space. That is, the points on the elliptic curve are limited to a finite integer value (0 or more and less than p), and the calculation is the remainder divided by this upper limit value p (mod calculation).
【0005】いま、素体FP上の楕円曲線EP上の2点を
P(x1,y1),Q(x2,y2)とし、T=cP+dQ
を求める値とする。T(x3,y3)も楕円曲線EP上の
点である。図6に、従来の算出手順のフローチャートを
示す。ただし、cとdはNow, let P (x 1 , y 1 ), Q (x 2 , y 2 ) be two points on the elliptic curve E P on the prime field F P , and T = cP + dQ.
Is the value to be calculated. T (x 3 , y 3 ) is also a point on the elliptic curve E P. FIG. 6 shows a flowchart of a conventional calculation procedure. However, c and d are
【0006】[0006]
【数8】 [Equation 8]
【0007】のように2進表現し、c、dの第iビット
目の係数を各々c i ,d i (∈{0,1})とする。kはck
≠0、またはdk≠0となる最大の整数である。また、
楕円曲線上の各種演算の定義を以下の通りとする。Binary representation is performed as in the above, and the coefficient of the i-th bit of c and d is respectively defined as c i , d i (ε {0,1}). k is ck
It is a maximum integer such that ≠ 0 or d k ≠ 0. Also,
The definitions of various operations on the elliptic curve are as follows.
【0008】楕円2倍演算T=2Pは、 1.P=(0,0)の場合は、x3=0,y3=0 2.P≠(0,0)の場合は、The ellipse doubling operation T = 2P is 1. If P = a (0,0), x 3 = 0 , y 3 = 0 2. If P ≠ (0,0),
【0009】[0009]
【数9】 とする。[Equation 9] And
【0010】また、楕円加算演算T=P+Qは、
3.P=(0,0)の場合は、x3=x2,y3=y2
4.P≠(0,0)、かつQ=(0,0)の場合は、x
3=x1,y3=y1
5.P≠(0,0)、かつQ=(0,0)、かつP+Q
=(0,0)の場合は、x3=0,y3=0
6.P≠(0,0)、かつQ≠(0,0)かつP+Q≠
(0,0)の場合は、Further, the elliptic curve addition operation T = P + Q is 3. When P = (0,0), x 3 = x 2 , y 3 = y 2 4. If P ≠ (0,0) and Q = (0,0), then x
3 = x 1 , y 3 = y 1 5. P ≠ (0,0), Q = (0,0), and P + Q
= (0,0), x 3 = 0, y 3 = 0 6. P ≠ (0,0), Q ≠ (0,0) and P + Q ≠
If (0,0),
【0011】[0011]
【数10】 とする。[Equation 10] And
【0012】図6のフローチャートは、次の処理を実行
するものである。
T←0
for(i=k;i≧0;i−−){
if((ci==0)&&(di==0))then{T←2T}
if((ci==1)&&(di==0))then{T←2T;T
←T+P}
if((ci==0)&&(di==1))then{T←2T;T
←T+Q}
if((ci==1)&&(di==1))then{T←2T;T
←T+(P+Q)}}
Return T
初期値としてTに0を設定し、i=k,k−1,…,
2,1,0の順番に、(ci,di)の値(00)、(0
1)、(10)、(11)にしたがって所定の演算を繰
り返し実行し、最終結果のTを求める。The flowchart of FIG. 6 executes the following processing. T ← 0 for (i = k; i ≧ 0; i−−) {if ((c i == 0) && (d i == 0)) then {T ← 2T} if ((c i == 1) ) && (d i == 0)) then {T ← 2T; T
← T + P} if ((c i == 0) && (d i == 1)) then {T ← 2T; T
← T + Q} if ((c i == 1) && (d i == 1)) then {T ← 2T; T
← T + (P + Q)}} Return T 0 is set to T as an initial value, and i = k, k−1, ...,
The values (00) and (0) of (c i , d i ) in the order of 2, 1, 0
Predetermined operations are repeatedly executed according to 1), 10), and 11 to obtain the final result T.
【0013】図6に示した処理手順にしたがって、上記
で定義したkを用いて、従来の算出手順に必要な楕円加
減算と楕円2倍算の必要回数を示すと、図7のようにな
る。According to the processing procedure shown in FIG. 6, the required number of elliptic curve addition / subtraction and elliptic curve doubling required for the conventional calculation procedure is shown in FIG. 7 using k defined above.
【0014】[0014]
【発明が解決しようとする課題】本発明の目的は、素体
(有限体)上の楕円曲線上の相異なる複数の点を各々整
数倍し、かつ、該整数倍した結果を加算する楕円積和演
算を、従来技術に比べて高速に行うことを可能とする方
法及び装置、並びに、そのプログラムを記録した記録媒
体を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is an elliptic product that multiplies a plurality of different points on an elliptic curve on a prime field (finite field) by an integer and adds the results of the integer multiplication. Method and apparatus capable of performing sum operation at higher speed than in the prior art, and recording medium recording the program
To provide the body .
【0015】[0015]
【課題を解決するための手段】本発明では、pを素数と
する素体Fpとし、In the present invention, a prime field F p having p as a prime number is defined as
【数11】
で定義される素体Fp上の楕円曲線Ep上の相異なる2
点をP,Qとし、互いに独立な2組の整数c,dを、 [Equation 11] 2 on the elliptic curve Ep on the field Fp defined by
Let P and Q be points, and set two independent integers c and d,
【数12】
のように2進数表現して、c,dの第iビット目の係数
をc i ,d i (∈{0,1})とし、c−1=d−1=
0、c2k+1+c2k+c2k−1≠0,d2k+1
+d2k+d2k−1≠0となるような最大のkを定義
して、
楕円積和演算計算
T=cP+dQを、制御回路、記憶回路及び演算回路を含むコンピュー
タ等により以下のように、自動的に計算する
。制御回路
は、パラメータP,Q、及び、演算結果Tの初期値とし
てT=0を記憶回路に格納し、以後、2組の整数c,d
から、i=k,k−1,…,2,1,0の順番に、順
次、2ビットずつシフトして、 (c 2i+1 c 2i c 2i-1 d 2i+1 d 2i d 2i-1 ) を選択し、この選択した(c 2i+1 c 2i c 2i-1 d 2i+1 d 2i
d 2i-1 )の値にもとづいて、 (1)(000000)、あるいは(111000)、あ
るいは(000111) 、あるいは(111111)の
場合、T←2T、T←2Tの順に実行される演算 (2)(001000)、あるいは(010000)、あ
るいは(001111)、あるいは(010111)の
場合、T←2T、T←2T、T←T+Pの順に実行され
る演算、 (3)(000001)、あるいは(111001)、あ
るいは(000010)、あるいは(111010)の
場合、T←2T、T←2T、T←T+Qの順に実行され
る演算、 (4)(101000)、あるいは(110000)、あ
るいは(101111)、あるいは(110111)の
場合、T←2T、T←2T、T←T−Pの順に実行され
る演算、 (5)(000101)、あるいは(111101)、あ
るいは(000110)、あるいは(111110)の
場合、T←2T、T←2T、T←T−Qの順に実行され
る演算、 (6)(001001)、あるいは(010001)、あ
るいは(001010)、あるいは(010010)の
場合、T←2T、T←2T、T←T+(P+Q)の順に
実行される演算、 (7)(001101)、あるいは(010101)、あ
るいは(001110)、あるいは(010110)の
場合、T←2T、T←2T、T←T+(P−Q)の順に
実行される演算、 (8)(101001)、あるいは(110001)、あ
るいは(101010)、あるいは(110010)の
場合、T←2T、T←2T、T←T−(P−Q)の順に
実行される演算、 (9)(101101)、あるいは(110101)、あ
るいは(101110)、あるいは(110110)の
場合はT←2T、T←2T、T←T−(P+Q)の順に
実行される演算、 (10)(011000)、あるいは(011111)の
場合、T←2T、T←T+P、T←2Tの順に実行され
る演算、 (11)(000011)、あるいは(111011)の
場合、T←2T、T←T+Q、T←2Tの順に実行され
る演算、 (12)(100000)、あるいは(100111)の
場合、T←2T、T←T−P、T←2Tの順に実行され
る演算、 (13)(000100)、あるいは(111100)の
場合、T←2T、T←T−Q、T←2Tの順に実行され
る演算、 (14)(011011)の場合、T←2T、T←T+
(P+Q)、T←2Tの順に実行される演算、 (15)(011100)の場合、T←2T、T←T+
(P−Q)、T←2Tの順に実行される演算、 (16)(100011)の場合、T←2T、T←T−
(P−Q)、T←2Tの順に実行される演算、 (17)(100100)の場合、T←2T、T←T−
(P+Q)、T←2Tの順に実行される演算、 (18)(011001)、あるいは(011010)の
場合、T←2T、T←T+P、T←2T、T←T+Qの
順に実行される演算
、(19)(011101)、あるいは(011110)の
場合、T←2T、T←T+P、T←2T、T←T−Qの
順に実行される演算、 (20)(100001)、あるいは(100010)の
場合、T←2T、T←T−P、T←2T、T←T+Qの
順に実行される演算、 (21)(100101)、あるいは(100110)の
場合、T←2T、T←T−P、T←2T、T←T−Qの
順に実行される演算、 (22)(001011)、あるいは(010011)の
場合、T←2T、T←T+Q、T←2T、T←T+Pの
順に実行される演算、 (23)(101011)あるいは(110011)の場
合、T←2T、T←T+Q、T←2T、T←T−Pの順
に実行される演算、 (24)(001100)、あるいは(010100)の
場合、T←2T、T←T−Q、T←2T、T←T+Pの
順に実行される演算、 (25)(101100)、あるいは(110100)の
場合、T←2T、T←T−Q、T←2T、T←T−Pの
順に実行される演算、のいずれかの演算を演算回路に指
示する。 演算回路は、制御回路からの指示にもとづき、
記憶回路からP,Q,Tを入力して、指示された演算を
実行し、演算結果のTを記憶回路に戻すようにする。 [Equation 12] Expressed in binary as follows, and the coefficient of the i-th bit of c and d
Be c i , d i (ε {0, 1}), and c −1 = d −1 =
0, c 2k + 1 + c 2k + c 2k-1 ≠ 0, d 2k + 1
By defining the maximum k such that + d 2k + d 2k−1 ≠ 0, the elliptic product sum calculation T = cP + dQ is calculated by a computer including a control circuit, a storage circuit and a calculation circuit.
It is automatically calculated by the following method . Control circuit
Is the initial value of the parameters P and Q and the calculation result T.
And stores T = 0 in the memory circuit, and thereafter two sets of integers c and d are set.
From i = k, k−1, ..., 2, 1, 0
Next, by shifting by 2 bits, (c 2i + 1 c 2i c 2i-1 d 2i + 1 d 2i d 2i-1 ) is selected, and this selected (c 2i + 1 c 2i c 2i-1 d ) is selected. 2i + 1 d 2i
Based on the value of d 2i-1 ), (1) (000000) or (111000),
Ruiha (000111) or (111111)
In this case, the operation (2) (001000) or (010000), which is executed in the order of T ← 2T, T ← 2T ,
Ruiha (001111) or (010111)
In this case, T ← 2T, T ← 2T, T ← T + P are executed in this order.
Calculation (3) (000001) or (111001)
Ruiha (000010) or (11110)
In this case, T ← 2T, T ← 2T, T ← T + Q are executed in this order.
Calculation (4) (101000) or (110000)
Ruiha (101111) or (110111)
In this case, T ← 2T, T ← 2T, T ← TP are executed in this order.
Calculation (5) (000101), or (111101),
Ruiha (000110) or (111110)
In this case, T ← 2T, T ← 2T, T ← T-Q are executed in this order.
That operation, (6) (001001), or (010001), Oh
Ruiha (001010) or (010010)
In this case, T ← 2T, T ← 2T, T ← T + (P + Q) in that order.
Operation to be executed, (7) (001101), or (010101)
Ruiha (001110) or (010110)
In this case, T ← 2T, T ← 2T, T ← T + (P−Q) in that order.
The operation to be executed, (8) (101001), or (110001),
Ruiha (101010) or (110010)
In this case, T ← 2T, T ← 2T, T ← T- (PQ) in that order.
Operation to be executed, (9) (101101), or (110101)
Ruiha (101110) or (110110)
In the case of T ← 2T, T ← 2T, T ← T- (P + Q)
The operation to be executed, (10) (011000), or (011111)
In this case, T ← 2T, T ← T + P, T ← 2T are executed in this order.
Calculation of (11) (000011) or (111011)
In this case, T ← 2T, T ← T + Q, T ← 2T are executed in this order.
Calculation of (12) (100000) or (100111)
In this case, T ← 2T, T ← TP, T ← 2T are executed in this order.
Calculation of (13) (000100) or (111100)
In this case, T ← 2T, T ← TQ, T ← 2T are executed in this order.
In the case of (14) (011011), T ← 2T, T ← T +
(P + Q), operation performed in the order of T ← 2T, (15) (011100), T ← 2T, T ← T +
(P-Q), operation performed in the order of T ← 2T, (16) (100011), T ← 2T, T ← T-
(P-Q), operation performed in the order of T ← 2T, (17) (100100), T ← 2T, T ← T-
(P + Q), operation performed in the order of T ← 2T, (18) (011001), or (011010)
In case of T ← 2T, T ← T + P, T ← 2T, T ← T + Q
Operation executed in order , (19) (011101), or (011110)
In case of T ← 2T, T ← T + P, T ← 2T, T ← T-Q
Operations that are executed in sequence, (20) (100001), or (100010)
In case of T ← 2T, T ← T-P, T ← 2T, T ← T + Q
Calculations executed in sequence, (21) (100101), or (100110)
In case of T ← 2T, T ← T-P, T ← 2T, T ← T-Q
Calculations that are executed in sequence, (22) (001011), or (010011)
In case of T ← 2T, T ← T + Q, T ← 2T, T ← T + P
Calculations executed in sequence, in the case of (23) (101011) or (110011)
, T ← 2T, T ← T + Q, T ← 2T, T ← TP
The operation executed in (24) (001100) or (010100)
In case of T ← 2T, T ← T−Q, T ← 2T, T ← T + P
The operation to be executed in order, (25) (101100), or (110100)
In case of T ← 2T, T ← T-Q, T ← 2T, T ← TP
The operation circuit is instructed to perform one of the operations executed in order.
To show. The arithmetic circuit is based on the instruction from the control circuit,
Input P, Q, T from the memory circuit and perform the specified operation
The calculation result T is returned to the memory circuit.
【0016】[0016]
【発明の実施の形態】以下、本発明の一実施の形態につ
いて説明する。ここでは、pを素数とする素体(有限
体)上の楕円曲線EP BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. Here, an elliptic curve E P on a prime field (finite field) with p as a prime number
【0017】[0017]
【数13】 [Equation 13]
【0018】上の2点をP(x1,y1)、Q(x2,
y2)とし、楕円積和演算
T=cP+dQ
を求める値とする。T(x3,y3)も楕円曲線EP上の
点である。ただし、cとdはThe two points above are P (x 1 , y 1 ), Q (x 2 ,
y 2 ), and the sum of elliptic products T = cP + dQ is obtained. T (x 3 , y 3 ) is also a point on the elliptic curve E P. However, c and d are
【0019】[0019]
【数14】 [Equation 14]
【0020】のように2進表現し、c,dの第iビット
目の係数を各々ci,di(∈{0,1})とする。また、
c-1=d-1=0とする。kはc2k+1+c2k+c2k-1≠
0、またはd2k+1+d2k+d2k-1≠0となるような最大
の整数とする。Binary representation is performed as described above, and coefficients of the i-th bit of c and d are respectively defined as c i and d i (ε {0,1}). Also,
Let c −1 = d −1 = 0. k is c 2k + 1 + c 2k + c 2k-1 ≠
0 or a maximum integer such that d 2k + 1 + d 2k + d 2k-1 ≠ 0.
【0021】図1に本楕円積和演算計算装置の構成例を
示す。図1において、制御回路100は全体の動作の制
御を司る。この制御回路100は、cとdを保持するレ
ジスタ、変数iをカウントするカウンタなどを内蔵し、
i=k,k−1,…,2,1,0の順番に、順次、(c
2i+1c2ic2i-1d2i+1d2id2i-1)を選択し、その値に
応じて、記憶回路110に対して所定データの読出しを
指示し、演算回路120に対して演算の種類と実行順序
を指示する。記憶回路110は、P、Q、P+Q、P−
Q、T(初期値は0)のデータなどを格納しており、制
御回路100の指示されたデータを読み出して演算回路
120に与える。演算回路120は2倍演算、加算、減
算などの演算を行う機能を有し、記憶回路110から与
えられたデータを入力として、制御回路100の指示さ
れた演算を、指示された順序で実行し、演算結果のTを
記憶回路110に戻す。FIG. 1 shows an example of the configuration of the present elliptic product sum operation computing device. In FIG. 1, a control circuit 100 controls the entire operation. The control circuit 100 has a register for holding c and d, a counter for counting the variable i, and the like,
i = k, k-1, ..., 2, 1, 0, in order, (c
2i + 1 c 2i c 2i-1 d 2i + 1 d 2i d 2i-1 ) is selected, and according to the value, the memory circuit 110 is instructed to read the predetermined data, and the arithmetic circuit 120 is instructed. Specify the type of operation and execution order. The memory circuit 110 includes P, Q, P + Q, and P-.
Data such as Q and T (initial value is 0) is stored, and the data instructed by the control circuit 100 is read and given to the arithmetic circuit 120. The arithmetic circuit 120 has a function of performing operations such as double operation, addition, and subtraction, and receives the data given from the memory circuit 110 as input, and executes the instructed operations of the control circuit 100 in the instructed order. , T of the calculation result is returned to the memory circuit 110.
【0022】図2に、楕円積和演算計算装置の概略処理
フローチャートを示す。制御回路100の制御下で、パ
ラメータP、Q、c、dなどを入力し、P、Qは記憶回
路110に格納し、c、dは制御回路100の内部レジ
スタに設定する(ステップ210)。次に、制御回路1
00により記憶回路110、演算回路120の動作を制
御してT=cP+dQの計算を実行し(ステップ22
0)、その計算結果Tを出力する(ステップ230)。FIG. 2 shows a schematic processing flowchart of the elliptic product sum operation computing device. Under the control of the control circuit 100, parameters P, Q, c, d, etc. are input, P, Q are stored in the memory circuit 110, and c, d are set in the internal register of the control circuit 100 (step 210). Next, the control circuit 1
00 to control the operations of the memory circuit 110 and the arithmetic circuit 120 to execute the calculation of T = cP + dQ (step 22
0), and the calculation result T is output (step 230).
【0023】図3は、図2のT=cP+dQの計算部分
(ステップ220)の詳細処理フローチャートである。
また、図4は、図3中のケース(Case)1〜25の
内容を示している。FIG. 3 is a detailed processing flowchart of the calculation part (step 220) of T = cP + dQ in FIG.
Further, FIG. 4 shows the contents of cases (Case) 1 to 25 in FIG.
【0024】楕円曲線上の各種演算の定義は以下の通り
である。
(1)楕円2倍演算T=2P
1.P=(0,0)の場合は、x3=0,y3=0
2.P≠(0,0)の場合は、The definitions of various operations on the elliptic curve are as follows. (1) Elliptic double operation T = 2P 1. If P = a (0,0), x 3 = 0 , y 3 = 0 2. If P ≠ (0,0),
【0025】[0025]
【数15】 [Equation 15]
【0026】(2)楕円加算演算T=P+Q
1.P=(0,0)の場合は、x3=x2,y3=y2
2.P≠(0,0)、かつQ=(0,0)の場合は、x3
=x1,y3=y1
3.P≠(0,0)、かつQ=(0,0)、かつP+Q=
(0,0)の場合は、x3=0,y3=0
4.P≠(0,0)、かつQ≠(0,0)、かつP+Q≠
(0,0)の場合は、(2) Elliptic curve addition operation T = P + Q 1. When P = (0,0), x 3 = x 2 , y 3 = y 2 2. If P ≠ (0,0) and Q = (0,0), then x 3
= X 1 , y 3 = y 1 . P ≠ (0,0), Q = (0,0), and P + Q =
In the case of (0,0), x 3 = 0, y 3 = 0 4. P ≠ (0,0), Q ≠ (0,0), and P + Q ≠
If (0,0),
【0027】[0027]
【数16】 [Equation 16]
【0028】(3)楕円減算演算T=P−Q
1.P=(0,0)の場合は、x3=x2,y3=p−y3
2.P≠(0,0)、かつQ=(0,0)の場合は、x
3=x1,y3=y1
3.P≠(0,0)、かつQ=(0,0)、かつP=Q
の場合は、x3=0,y3=0
4.P≠(0,0)、かつQ≠(0,0)、かつP≠Q
の場合は、(3) Elliptic subtraction operation T = P-Q 1. When P = (0,0), x 3 = x 2 , y 3 = p−y 3 2. If P ≠ (0,0) and Q = (0,0), then x
3 = x 1 , y 3 = y 1 3. P ≠ (0,0), Q = (0,0), and P = Q
In the case of, x 3 = 0, y 3 = 0 4. P ≠ (0,0), Q ≠ (0,0), and P ≠ Q
In the case of,
【0029】[0029]
【数17】 [Equation 17]
【0030】図3のフローチャートは、次の処理を実行
するものである。
T←0
for(i=k;i≧0;i−−){
if(Case1)then{T←2T;T←2T}
else if(Case2)then{T←2T;T←2T;T←T
+P}
else if(Case3)then{T←2T;T←2T;T←T
+Q}
else if(Case4)then{T←2T;T←2T;T←T
−P}
else if(Case5)then{T←2T;T←2T;T←T
−Q}
else if(Case6)then{T←2T;T←2T;T←T
+(P+Q)}
else if(Case7)then{T←2T;T←2T;T←T
+(P−Q)}
else if(Case8)then{T←2T;T←2T;T←T
−(P−Q)}
else if(Case9)then{T←2T;T←2T;T←T
−(P+Q)}
else if(Case10)then{T←2T;T+P;T←2
T}
else if(Case11)then{T←2T;T+Q;T←2
T}
else if(Case12)then{T←2T;T−P;T←2
T}
else if(Case13)then{T←2T;T−Q;T←2
T}
else if(Case14)then{T←2T;T+(P+Q);T
←2T}
else if(Case15)then{T←2T;T+(P−Q);T
←2T}
else if(Case16)then{T←2T;T−(P−Q);T
←2T}
else if(Case17)then{T←2T;T−(P+Q);T
←2T}
else if(Case18)then{T←2T;T+P;T←2
T;T←T+Q}
else if(Case19)then{T←2T;T+P;T←2
T;T←T−Q}
else if(Case20)then{T←2T;T−P;T←2
T;T←T+Q}
else if(Case21)then{T←2T;T−P;T←2
T;T←T−Q}
else if(Case22)then{T←2T;T+Q;T←2
T;T←T+P}
else if(Case23)then{T←2T;T+Q;T←2
T;T←T−P}
else if(Case24)then{T←2T;T−Q;T←2
T;T←T+P}
else if(Case25)then{T←2T;T−Q;T←2
T;T←T−P}}The flowchart of FIG. 3 executes the following processing. T ← 0 for (i = k; i ≧ 0; i−−) {if (Case1) then {T ← 2T; T ← 2T} else if (Case2) then {T ← 2T; T ← 2T; T ← T
+ P} else if (Case3) then {T ← 2T; T ← 2T; T ← T
+ Q} else if (Case 4) then {T ← 2T; T ← 2T; T ← T
-P} else if (Case 5) then {T ← 2T; T ← 2T; T ← T
-Q} else if (Case 6) then {T ← 2T; T ← 2T; T ← T
+ (P + Q)} else if (Case 7) then {T ← 2T; T ← 2T; T ← T
+ (P−Q)} else if (Case8) then {T ← 2T; T ← 2T; T ← T
-(P-Q)} else if (Case 9) then {T ← 2T; T ← 2T; T ← T
− (P + Q)} else if (Case10) then {T ← 2T; T + P; T ← 2
T} else if (Case11) then {T ← 2T; T + Q; T ← 2
T} else if (Case12) then {T ← 2T; TP-T; T ← 2
T} else if (Case13) then {T ← 2T; T−Q; T ← 2
T} else if (Case14) then {T ← 2T; T + (P + Q); T
← 2T} else if (Case15) then {T ← 2T; T + (P−Q); T
← 2T} else if (Case16) then {T ← 2T; T- (P-Q); T
← 2T} else if (Case17) then {T ← 2T; T- (P + Q); T
← 2T} else if (Case18) then {T ← 2T; T + P; T ← 2
T; T ← T + Q} else if (Case19) then {T ← 2T; T + P; T ← 2
T; T ← T−Q} else if (Case20) then {T ← 2T; T−P; T ← 2
T; T ← T + Q} else if (Case21) then {T ← 2T; TP-T; T ← 2
T; T ← T−Q} else if (Case22) then {T ← 2T; T + Q; T ← 2
T; T ← T + P} else if (Case23) then {T ← 2T; T + Q; T ← 2
T; T ← T−P} else if (Case24) then {T ← 2T; T−Q; T ← 2
T; T ← T + P} else if (Case25) then {T ← 2T; T−Q; T ← 2
T; T ← T-P}}
【0031】上記処理手順のプログラム(これを楕円積
和演算計算プログラムと称す)は、コンピュータが読み
取り可能な記録媒体、例えばフロッピーディスクやメモ
リカード、コンパクトディスク(CD−ROM)などに
記録して提供することが可能である。制御回路100
が、この記録媒体の楕円積和演算計算プログラムを読み
込み実行することで、図3の処理フローが実現する。な
お、制御回路100は、この楕円積和演算計算プログラ
ムを記録したROMをあらかじめ保持しておくことでも
よい。The program of the above processing procedure (this program is called an elliptic product sum calculation program) is provided by being recorded in a computer-readable recording medium such as a floppy disk, a memory card, a compact disk (CD-ROM) or the like. It is possible to Control circuit 100
However, the processing flow of FIG. 3 is realized by reading and executing the elliptic product sum calculation program of this recording medium. The control circuit 100 may hold a ROM in which the elliptic product sum calculation program is recorded in advance.
【0032】図3に示した処理手順では、P+QとP−
Qを予め算出して記憶回路110に記憶しておく必要が
ある。図3に示した処理手順にしたがって、先に定義し
たkを用いて、本実施形態で必要な楕円加減算と楕円2
倍演算の必要回数を示すと、図8のようになる。図7の
従来手法に比べて、平均に約20%楕円加減算演算の回
数を減少できる。In the processing procedure shown in FIG. 3, P + Q and P-
It is necessary to calculate Q in advance and store it in the storage circuit 110. According to the processing procedure shown in FIG. 3, ellipse addition / subtraction and ellipse 2 required in the present embodiment are performed using k defined above.
The required number of times of double operation is shown in FIG. Compared with the conventional method of FIG. 7, the number of elliptic addition / subtraction operations can be reduced by about 20% on average.
【0033】図5は、制御回路100の別の実施形態で
あり、図3の処理をハードウェアロックで実現した構成
例を示したものである。図5において、101はcとd
を格納したシフトレジスタであり、シフトロックにより
2ビットずつシフトし、i=k、k−1,…,2,1,
0の順番に、順次、データ(c2i+1c2ic2i-1d2i+1d
2id2i-1)を読み出すことを実現する。デコーダ102
−1〜102−25は図4のケース1〜25に対応し、
シフトレジスタ101の出力データ(c2i+1c2ic2i-1
d2i+1d2id2i-1)を並列にデコードし、いずれかで一
致した場合、該当デコーダが一致信号を出力する。演算
制御テーブル103は、ケース1−25に対応した演算
コマンド群を保持しており、デコーダ102−1〜10
2−25のデコード出力にもとづいて、対応する演算コ
マンド群の制御下で、記憶回路110に対して所望デー
タの読出しを指示し、演算回路120に対しては演算の
種類とその実行順序を指示する。FIG. 5 shows another embodiment of the control circuit 100, and shows a configuration example in which the processing of FIG. 3 is realized by a hardware lock. In FIG. 5, 101 is c and d
Is a shift register that stores 2 bits, shifts by 2 bits by shift lock, and i = k, k−1, ..., 2, 1,
The data (c 2i + 1 c 2i c 2i-1 d 2i + 1 d
2i d 2i-1 ) is realized. Decoder 102
-1 to 102-25 correspond to cases 1 to 25 in FIG.
Output data of the shift register 101 (c 2i + 1 c 2i c 2i-1
(d 2i + 1 d 2i d 2i-1 ) is decoded in parallel, and if there is a match in any of them, the corresponding decoder outputs a match signal. The arithmetic control table 103 holds an arithmetic command group corresponding to case 1-25, and the decoders 102-1 to 10-2
Based on the decoded output of 2-25, the storage circuit 110 is instructed to read desired data under the control of the corresponding operation command group, and the operation circuit 120 is instructed about the type of operation and its execution order. To do.
【0034】図5の構成によれば、図3のケース1〜2
5の場合分けが並列に処理でき、さらに高速化が実現す
る。また、ハードロジックとすることにより、制御回路
100と記憶回路110と演算回路120とを一体構成
にした半導体集積回路が実現可能である。According to the configuration of FIG. 5, the cases 1 and 2 of FIG.
The case classification of 5 can be processed in parallel, further speeding up is realized. Further, by using hard logic, it is possible to realize a semiconductor integrated circuit in which the control circuit 100, the memory circuit 110, and the arithmetic circuit 120 are integrally configured.
【0035】[0035]
【発明の効果】以上説明したように、本発明によれば、
素体FP上の楕円曲線EP上の相異なる2つの点を各々整
数倍し、かつ整数倍した結果を加算する演算を、符合付
き繰り返し2倍法を特徴とする算出方法により、従来手
法より高速に算出できる利点がある。As described above, according to the present invention,
An operation of multiplying two different points on the elliptic curve E P on the prime field F P by an integer and adding the results of the integer multiplication is performed by a conventional method using a signed iterative doubling method. There is an advantage that it can be calculated faster.
【図1】本発明の一実施形態の楕円積和演算装置の構成
例を示すブロック図である。FIG. 1 is a block diagram showing a configuration example of an elliptic product sum computing device according to an embodiment of the present invention.
【図2】図1の楕円積和演算装置の全体的処理フローチ
ャートである。FIG. 2 is an overall processing flowchart of the elliptic product sum computing device of FIG.
【図3】図2の積和演算計算部分の詳細処理フローチャ
ートである。FIG. 3 is a detailed processing flowchart of a product-sum operation calculation part in FIG.
【図4】図3の演算種別、実行順序の場合分けを示す図
である。FIG. 4 is a diagram showing the classification of operations and execution order in FIG.
【図5】図1の制御回路の機能をハードロジックで実現
した構成例を示す図である。5 is a diagram showing a configuration example in which the function of the control circuit of FIG. 1 is realized by hard logic.
【図6】従来手法による楕円積和演の処理フローチャー
トである。FIG. 6 is a processing flowchart of an elliptic product sum performance according to a conventional method.
【図7】図6の従来手法の算出処理に必要な楕円加算演
算と楕円2倍演算の回数を示す図である。FIG. 7 is a diagram showing the number of elliptic curve addition operations and elliptic curve doubling operations required for the calculation process of the conventional method of FIG.
【図8】図3の本発明の実施形態の算出処理に必要な楕
円加減算演算と楕円2倍演算の回数を示す図である。FIG. 8 is a diagram showing the number of elliptic curve addition / subtraction calculations and elliptic curve doubling calculations required for the calculation process of the embodiment of the present invention in FIG. 3;
100 制御回路 110 記憶回路 120 演算回路 100 control circuit 110 memory circuit 120 arithmetic circuits
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平5−150722(JP,A) 特開 平6−118873(JP,A) The Fast Cascade Exponentiation Alg orithm and its App lication on Crypto graphy,Lecture Not es in Computer Sci ence,Lecture Notes in Computer Scien ce,p.447−456 3次曲線に基づく公開鍵暗号,NTT R&D,1995年10月10日,Vol. 44, No.10,p.91−98 More Flexible Exp onentiation with P recomputataion,Lec ture Notes in Comp uter Science,Vol. 839,p.95−107 (58)調査した分野(Int.Cl.7,DB名) G09C 1/00 650 G06F 17/10 JICSTファイル(JOIS)─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-150722 (JP, A) JP-A-6-118873 (JP, A) The Fast Cascade Expenditure Alg origin and it's application on Cryptography, Lectur. es in Computer Science, Lecture Notes in Computer Science, p. 447-456 Public Key Cryptography Based on Cubic Curve, NTT R & D, October 10, 1995, Vol. 44, No. 10, p. 91-98 More Flexible Expiration with Precomputation, Lecture Notes in Computer Science, Vol. 839, p. 95-107 (58) Fields surveyed (Int.Cl. 7 , DB name) G09C 1/00 650 G06F 17/10 JISC file (JOIS)
Claims (3)
点をP,Qとし、互いに独立な2組の整数c,dを、 【数2】 のように2進数表現して、c,dの第iビット目の係数
をc i ,d i (∈{0,1})とし、c −1 =d −1 =
0、 c 2k+1 +c 2k +c 2k−1 ≠0,d 2k+1 +d
2k +d 2k−1 ≠0 となるような最大のkを定義し
て、楕円積和演算計算 T=cP+dQ を、制御回路、記憶回路及び演算回路を含むコンピュー
タにより自動的に計算する方法であって、制御回路は、パラメータP,Q、及び、演算結果Tの初
期値としてT=0を記憶回路に格納し、2組の整数c,
dから、i=k,k−1,…,2,1,0の順番に、順
次、2ビットずつシフトして、 (c 2i+1 c 2i c 2i-1 d 2i+1 d 2i d 2i-1 ) を選択し、前記選択した(c 2i+1 c 2i c 2i-1 d 2i+1 d 2i
d 2i-1 )の値にもとづいて、 (1)(000000)、あるいは(111000)、あ
るいは(000111)、あるいは(111111)の
場合、T←2T、T←2Tの順に実行される演算 (2)(001000)、あるいは(010000)、あ
るいは(001111)、あるいは(010111)の
場合、T←2T、T←2T、T←T+Pの順に実行され
る演算、 (3)(000001)、あるいは(111001)、あ
るいは(000010)、あるいは(111010)の
場合、T←2T、T←2T、T←T+Qの順に実行され
る演算、 (4)(101000)、あるいは(110000)、あ
るいは(101111)、あるいは(110111)の
場合、T←2T、T←2T、T←T−Pの順に実行され
る演算、 (5)(000101)、あるいは(111101)、あ
るいは(000110)、あるいは(111110)の
場合、T←2T、T←2T、T←T−Qの順に実行され
る演算、 (6)(001001)、あるいは(010001)、あ
るいは(001010)、あるいは(010010)の
場合、T←2T、T←2T、T←T+(P+Q)の順に
実行される演算、 (7)(001101)、あるいは(010101)、あ
るいは(001110)、あるいは(010110)の
場合、T←2T、T←2T、T←T+(P−Q)の順に
実行される演算、 (8)(101001)、あるいは(110001)、あ
るいは(101010)、あるいは(110010)の
場合、T←2T、T←2T、T←T−(P−Q)の順に
実行される演算、 (9)(101101)、あるいは(110101)、あ
るいは(101110)、あるいは(110110)の
場合はT←2T、T←2T、T←T−(P+Q)の順に
実行される演算、 (10)(011000)、あるいは(011111)の
場合、T←2T、T←T+P、T←2Tの順に実行され
る演算、 (11)(000011)、あるいは(111011)の
場合、T←2T、T←T +Q、T←2Tの順に実行され
る演算、 (12)(100000)、あるいは(100111)の
場合、T←2T、T←T−P、T←2Tの順に実行され
る演算、 (13)(000100)、あるいは(111100)の
場合、T←2T、T←T−Q、T←2Tの順に実行され
る演算、 (14)(011011)の場合、T←2T、T←T+
(P+Q)、T←2Tの順に実行される演算、 (15)(011100)の場合、T←2T、T←T+
(P−Q)、T←2Tの順に実行される演算、 (16)(100011)の場合、T←2T、T←T−
(P−Q)、T←2Tの順に実行される演算、 (17)(100100)の場合、T←2T、T←T−
(P+Q)、T←2Tの順に実行される演算、 (18)(011001)、あるいは(011010)の
場合、T←2T、T←T+P、T←2T、T←T+Qの
順に実行される演算、 (19)(011101)、あるいは(011110)の
場合、T←2T、T←T+P、T←2T、T←T−Qの
順に実行される演算、 (20)(100001)、あるいは(100010)の
場合、T←2T、T←T−P、T←2T、T←T+Qの
順に実行される演算、 (21)(100101)、あるいは(100110)の
場合、T←2T、T←T−P、T←2T、T←T−Qの
順に実行される演算、 (22)(001011)、あるいは(010011)の
場合、T←2T、T←T+Q、T←2T、T←T+Pの
順に実行される演算、 (23)(101011)あるいは(110011)の場
合、T←2T、T←T+Q、T←2T、T←T−Pの順
に実行される演算、 (24)(001100)、あるいは(010100)の
場合、T←2T、T←T−Q、T←2T、T←T+Pの
順に実行される演算、 (25)(101100)、あるいは(110100)の
場合、T←2T、T←T−Q、T←2T、T←T−Pの
順に実行される演算、 のいずれかの演算を演算回路に指示し、 演算回路は、前記制御回路からの指示にもとづき、記憶
回路からP,Q,Tを入力して、前記指示された演算を
実行し、演算結果のTを記憶回路に戻す、 ことを特徴と
する楕円積和演算計算方法。1. A prime field F p having p as a prime number is defined as follows: 2 on the elliptic curve Ep on the field Fp defined by
Let P and Q be points, and set two mutually independent integers c and d as follows : Expressed in binary as follows, and the coefficient of the i-th bit of c and d
Be c i , d i (ε {0,1}), and c −1 = d −1 =
0, c 2k + 1 + c 2k + c 2k−1 ≠ 0, d 2k + 1 + d
By defining the maximum k such that 2k + d2k-1 ≠ 0 , the elliptic product sum calculation T = cP + dQ is automatically calculated by the computer including the control circuit, the storage circuit and the calculation circuit. The control circuit uses the parameters P, Q and the calculation result T as the first parameter.
T = 0 is stored in the memory circuit as the period value, and two sets of integers c,
From d, i = k, k−1, ..., 2, 1, 0
Then, by shifting by 2 bits, (c 2i + 1 c 2i c 2i-1 d 2i + 1 d 2i d 2i-1 ) is selected, and the selected (c 2i + 1 c 2i c 2i-1 d ) is selected. 2i + 1 d 2i
Based on the value of d 2i-1 ), (1) (000000) or (111000),
Ruiha (000111) or (111111)
In this case, the operation (2) (001000) or (010000), which is executed in the order of T ← 2T, T ← 2T ,
Ruiha (001111) or (010111)
In this case, T ← 2T, T ← 2T, T ← T + P are executed in this order.
Calculation (3) (000001) or (111001)
Ruiha (000010) or (11110)
In this case, T ← 2T, T ← 2T, T ← T + Q are executed in this order.
Calculation (4) (101000) or (110000)
Ruiha (101111) or (110111)
In this case, T ← 2T, T ← 2T, T ← TP are executed in this order.
Calculation (5) (000101), or (111101),
Ruiha (000110) or (111110)
In this case, T ← 2T, T ← 2T, T ← T-Q are executed in this order.
That operation, (6) (001001), or (010001), Oh
Ruiha (001010) or (010010)
In this case, T ← 2T, T ← 2T, T ← T + (P + Q) in that order.
Operation to be executed, (7) (001101), or (010101)
Ruiha (001110) or (010110)
In this case, T ← 2T, T ← 2T, T ← T + (P−Q) in that order.
The operation to be executed, (8) (101001), or (110001),
Ruiha (101010) or (110010)
In this case, T ← 2T, T ← 2T, T ← T- (PQ) in that order.
Operation to be executed, (9) (101101), or (110101)
Ruiha (101110) or (110110)
In the case of T ← 2T, T ← 2T, T ← T- (P + Q)
The operation to be executed, (10) (011000), or (011111)
In this case, T ← 2T, T ← T + P, T ← 2T are executed in this order.
Calculation of (11) (000011) or (111011)
In this case, T ← 2T, T ← T + Q, T ← 2T are executed in this order.
Calculation of (12) (100000) or (100111)
In this case, T ← 2T, T ← TP, T ← 2T are executed in this order.
Calculation of (13) (000100) or (111100)
In this case, T ← 2T, T ← TQ, T ← 2T are executed in this order.
In the case of (14) (011011), T ← 2T, T ← T +
(P + Q), operation performed in the order of T ← 2T, (15) (011100), T ← 2T, T ← T +
(P-Q), operation performed in the order of T ← 2T, (16) (100011), T ← 2T, T ← T-
(P-Q), operation performed in the order of T ← 2T, (17) (100100), T ← 2T, T ← T-
(P + Q), operation performed in the order of T ← 2T, (18) (011001), or (011010)
In case of T ← 2T, T ← T + P, T ← 2T, T ← T + Q
Operation executed in order, (19) (011101), or (011110)
In case of T ← 2T, T ← T + P, T ← 2T, T ← T-Q
Operations that are executed in sequence, (20) (100001), or (100010)
In case of T ← 2T, T ← T-P, T ← 2T, T ← T + Q
Calculations executed in sequence, (21) (100101), or (100110)
In case of T ← 2T, T ← T-P, T ← 2T, T ← T-Q
Calculations that are executed in sequence, (22) (001011), or (010011)
In case of T ← 2T, T ← T + Q, T ← 2T, T ← T + P
Calculations executed in sequence, in the case of (23) (101011) or (110011)
, T ← 2T, T ← T + Q, T ← 2T, T ← TP
The operation executed in (24) (001100) or (010100)
In case of T ← 2T, T ← T−Q, T ← 2T, T ← T + P
The operation to be executed in order, (25) (101100), or (110100)
In case of T ← 2T, T ← T-Q, T ← 2T, T ← TP
One of the operations to be executed in order is instructed to the arithmetic circuit , and the arithmetic circuit stores the memory based on the instruction from the control circuit.
Input P, Q, and T from the circuit to perform the instructed operation
An elliptic product sum calculation method , which is executed and returns T as a calculation result to a storage circuit .
点をP,Qとし、互いに独立な2組の整数c,dを、 【数4】 のように2進数表現して、c,dの第iビット目の係数
をc i ,d i (∈{0,1})とし、c−1=d−1=
0、c 2k+1 +c 2k +c 2k−1 ≠0,d 2k+1 +d
2k +d 2k−1 ≠0となるような最大のkを定義し
て、楕円積和演算計算 T=cP+dQを計算する楕円積和演算装置において、 パラメータP,Q、演算結果Tを格納する記憶手段と、 2組の整数c,dを格納する記憶手段と、 前記2組の整数c,dの (c 2i+1 c 2i c 2i-1 d 2i+1 d 2i d 2i-1 ) の値に応じて、 (1)(000000)、あるいは(111000)、あ
るいは(000111)、あるいは(111111)の
場合、T←2T、T←2Tの順に実行される演算 (2)(001000)、あるいは(010000)、あ
るいは(001111)、あるいは(010111)の
場合、T←2T、T←2T、T←T+Pの順に実行され
る演算、 (3)(000001)、あるいは(111001)、あ
るいは(000010)、あるいは(111010)の
場合、T←2T、T←2T、T←T+Qの順に実行され
る演算、 (4)(101000)、あるいは(110000)、あ
るいは(101111)、あるいは(110111)の
場合、T←2T、T←2T、T←T−Pの順に実行され
る演算、 (5)(000101)、あるいは(111101)、あ
るいは(000110)、あるいは(111110)の
場合、T←2T、T←2T、T←T−Qの順に実行され
る演算、 (6)(001001)、あるいは(010001)、あ
るいは(001010)、あるいは(010010)の
場合、T←2T、T←2T、T←T+(P+Q)の順に
実行される演算、 (7)(001101)、あるいは(010101)、あ
るいは(001110)、あるいは(010110)の
場合、T←2T、T←2T、T←T+(P−Q)の順に
実行される演算、 (8)(101001)、あるいは(110001)、あ
るいは(101010)、あるいは(110010)の
場合、T←2T、T←2T、T←T−(P−Q)の順に
実行される演算、 (9)(101101)、あるいは(110101)、あ
るいは(101110)、あるいは(110110)の
場合はT←2T、T←2T、T←T−(P+Q)の順に
実行される演算、 (10)(011000)、あるいは(011111)の
場合、T←2T、T←T+P、T←2Tの順に実行され
る演算、 (11)(000011)、あるいは(111011)の
場合、T←2T、T←T+Q、T←2Tの順に実行され
る演算、 (12)(100000)、あるいは(100111)の
場合、T←2T、T←T−P、T←2Tの順に実行され
る演算、 (13)(000100)、あるいは(111100)の
場合、T←2T、T←T−Q、T←2Tの順に実行され
る演算、 (14)(011011)の場合、T←2T、T←T+
(P+Q)、T←2Tの順に実行される演算、 (15)(011100)の場合、T←2T、T←T+
(P−Q)、T←2Tの順に実行される演算、 (16)(100011)の場合、T←2T、T←T−
(P−Q)、T←2Tの順に実行される演算、 (17)(100100)の場合、T←2T、T←T−
(P+Q)、T←2Tの順に実行される演算、 (18)(011001)、あるいは(011010)の
場合、T←2T、T←T+P、T←2T、T←T+Qの
順に実行される演算、 (19)(011101)、あるいは(011110)の
場合、T←2T、T←T+P、T←2T、T←T−Qの
順に実行される演算、 (20)(100001)、あるいは(100010)の
場合、T←2T、T←T−P、T←2T、T←T+Qの
順に実行される演算、 (21)(100101)、あるいは(100110)の
場合、T←2T、T←T−P、T←2T、T←T−Qの
順に実行される演算、 (22)(001011)、あるいは(010011)の
場合、T←2T、T←T+Q、T←2T、T←T+Pの
順に実行される演算、 (23)(101011)あるいは(110011)の場
合、T←2T、T←T+Q、T←2T、T←T−Pの順
に実行される演算、 (24)(001100)、あるいは(010100)の
場合、T←2T、T←T−Q、T←2T、T←T+Pの
順に実行される演算、 (25)(101100)、あるいは(110100)の
場合、T←2T、T←T−Q、T←2T、T←T−Pの
順に実行される演算、を定義した手段と、 最初、T=0を記憶手段に初期設定し、以後、前記2組
の整数c,dから、i =k,k−1,…,2,1,0の
順番に、順次、2ビットずつシフトして、 (c 2i+1 c 2i c 2i-1 d 2i+1 d 2i d 2i-1 ) を選択し、その値に応じて、上記定義された(1)〜(25)
の演算の該当する演算を演算手段に指示する制御手段
と、 前記制御手段からの指示にもとづき、記憶手段からP,
Q,Tを入力して、前記指示された演算を実行し、演算
結果のTを記憶手段に戻す演算手段と、を有することを
特徴とする楕円積和演算計算装置 。2. A prime field F p having p as a prime number, and 2 on the elliptic curve Ep on the field Fp defined by
Let P and Q be points, and set two mutually independent integers c and d as follows : Expressed as a binary number, and the coefficient of the i-th bit of c and d
Be c i , d i (ε {0, 1}), and c −1 = d −1 =
0, c 2k + 1 + c 2k + c 2k−1 ≠ 0, d 2k + 1 + d
We define the maximum k such that 2k + d 2k-1 ≠ 0.
Te, In oval product-sum operation unit for calculating the elliptical sum operation calculates T = cP + dQ, storage means for storing the parameters P, Q, the operation result T, 2 sets of integers c, a storage unit for storing d, the Depending on the value of (c 2i + 1 c 2i c 2i-1 d 2i + 1 d 2i d 2i-1 ) of two sets of integers c and d , (1) (000000) or (111000), or ( In the case of (000111) or (111111), the operation (2) (001000) or (010000), or (001111) or (010111), which is executed in the order of T ← 2T and T ← 2T, T ← 2T , T ← 2T, T ← T + P, (3) (000001), (111001), (000010), or (111010), T ← 2T, T ← 2T, T ← T + Q In the case of (4) (101000), (110000), (101111), or (110111), T ← 2T, T ← 2T, T ← TP (5) In the case of (000101), (111101), (000110), or (111110), an operation executed in the order of T ← 2T, T ← 2T, T ← TQ, (6) (001001) , Or (010001), or (001010), or (010010), the operations executed in the order of T ← 2T, T ← 2T, T ← T + (P + Q), (7) (001101), or (010101) , Or (001110) or (010110), the operations executed in the order of T ← 2T, T ← 2T, T ← T + (P−Q), ) In the case of (101001), (110001), (101010), or (110010), the operations executed in the order of T ← 2T, T ← 2T, T ← T- (PQ), (9) ( 101101), or (110101), or (101110), or (110110), the operations executed in the order of T ← 2T, T ← 2T, T ← T− (P + Q), (10) (011000), or In the case of (011111), the operation executed in the order of T ← 2T, T ← T + P, T ← 2T, (11) (000011), or in the case of (111011), T ← 2T, T ← T + Q, T ← 2T Operation to be executed in order, (12) (100000), or in the case of (100111), operation to be executed in the order of T ← 2T, T ← TP, T ← 2T, (13) (000100) , Or (111100), T ← 2T, T ← T−Q, T ← 2T, and (14) (011011), T ← 2T, T ← T +
(P + Q), operation performed in the order of T ← 2T, (15) (011100), T ← 2T, T ← T +
(P-Q), operation performed in the order of T ← 2T, (16) (100011), T ← 2T, T ← T-
(P-Q), operation performed in the order of T ← 2T, (17) (100100), T ← 2T, T ← T-
(P + Q), operation performed in the order of T ← 2T, (18) In the case of (011001) or (011010), operation performed in the order of T ← 2T, T ← T + P, T ← 2T, T ← T + Q, (19) In the case of (011101) or (011110), the operation executed in the order of T ← 2T, T ← T + P, T ← 2T, T ← TQ, (20) (100001), or (100010) In the case of T ← 2T, T ← T−P, T ← 2T, T ← T + Q, in the order of (21) (100101) or (100110), T ← 2T, T ← T−P, Operation executed in order of T ← 2T, T ← T−Q, (22) (001011), or (010011), executed in order of T ← 2T, T ← T + Q, T ← 2T, T ← T + P Calculation, (23) (101011) or ( In the case of 10011), T ← 2T, T ← T + Q, T ← 2T, T ← T-P are executed in this order, (24) (001100), or (010100), T ← 2T, T ← T -Q, T ← 2T, T ← T + P, (25) (101100) or (110100), T ← 2T, T ← T-Q, T ← 2T, T ← T-P Means for defining operations to be executed in the order of, and first, T = 0 is initially set in the storage means.
From integers c and d of i = k, k-1, ..., 2,1,0
Sequentially, by sequentially shifting by 2 bits and selecting (c 2i + 1 c 2i c 2i-1 d 2i + 1 d 2i d 2i-1 ) , depending on the value, the above defined (1 )~(twenty five)
Control means for instructing the calculation means of the corresponding calculation
If, based on the instruction from the control unit, P from the storage means,
Input Q and T to execute the specified operation and
And a calculation means for returning the result T to the storage means.
A characteristic elliptic product sum calculation device .
点をP,Qとし、互いに独立な2組の整数c,dを、 【数6】 のように2進数表現して、c,dの第iビット目の係数
をc i ,d i (∈{0,1})とし、c−1=d−1=
0、c 2k+1 +c 2k +c 2k−1 ≠0,d 2k+1 +d
2k +d 2k−1 ≠0 となるような最大のkを定義し
て、楕円積和演算計算 T=cP+dQを、制御回路、記憶回路及び演算回路を含むコンピュー
タにより自動的に計算するための楕円積和演算プログラ
ムを記録したコンピュータ読み取り可能な記録媒体であ
って、 制御回路が、最初、パラメータP,Q、及び、演算結果
Tの初期値としてT=0を記憶回路に格納し、以後、2
組の整数c,dから、i=k,k−1,…,2 ,1,0
の順番に、順次、2ビットずつシフトして、 (c 2i+1 c 2i c 2i-1 d 2i+1 d 2i d 2i-1 ) を選択し、前記選択した(c 2i+1 c 2i c 2i-1 d 2i+1 d 2i
d 2i-1 )の値にもとづいて、 (1)(000000)、あるいは(111000)、あ
るいは(000111)、あるいは(111111)の
場合、T←2T、T←2Tの順に実行される演算 (2)(001000)、あるいは(010000)、あ
るいは(001111)、あるいは(010111)の
場合、T←2T、T←2T、T←T+Pの順に実行され
る演算、 (3)(000001)、あるいは(111001)、あ
るいは(000010)、あるいは(111010)の
場合、T←2T、T←2T、T←T+Qの順に実行され
る演算、 (4)(101000)、あるいは(110000)、あ
るいは(101111)、あるいは(110111)の
場合、T←2T、T←2T、T←T−Pの順に実行され
る演算、 (5)(000101)、あるいは(111101)、あ
るいは(000110)、あるいは(111110)の
場合、T←2T、T←2T、T←T−Qの順に実行され
る演算、 (6)(001001)、あるいは(010001)、あ
るいは(001010)、あるいは(010010)の
場合、T←2T、T←2T、T←T+(P+Q)の順に
実行される演算 、(7)(001101)、あるいは(010101)、あ
るいは(001110)、あるいは(010110)の
場合、T←2T、T←2T、T←T+(P−Q)の順に
実行される演算、 (8)(101001)、あるいは(110001)、あ
るいは(101010)、あるいは(110010)の
場合、T←2T、T←2T、T←T−(P−Q)の順に
実行される演算、 (9)(101101)、あるいは(110101)、あ
るいは(101110)、あるいは(110110)の
場合はT←2T、T←2T、T←T−(P+Q) の順に
実行される演算、 (10)(011000)、あるいは(011111)の
場合、T←2T、T←T+P、T←2Tの順に実行され
る演算、 (11)(000011)、あるいは(111011)の
場合、T←2T、T←T+Q、T←2Tの順に実行され
る演算、 (12)(100000)、あるいは(100111)の
場合、T←2T、T←T−P、T←2Tの順に実行され
る演算、 (13)(000100)、あるいは(111100)の
場合、T←2T、T←T−Q、T←2Tの順に実行され
る演算、 (14)(011011)の場合、T←2T、T←T+
(P+Q)、T←2Tの順に実行される演算、 (15)(011100)の場合、T←2T、T←T+
(P−Q)、T←2Tの順に実行される演算、 (16)(100011)の場合、T←2T、T←T−
(P−Q)、T←2Tの順に実行される演算、 (17)(100100)の場合、T←2T、T←T−
(P+Q)、T←2Tの順に実行される演算、 (18)(011001)、あるいは(011010)の
場合、T←2T、T←T+P、T←2T、T←T+Qの
順に実行される演算、 (19)(011101)、あるいは(011110)の
場合、T←2T、T←T+P、T←2T、T←T−Qの
順に実行される演算、 (20)(100001)、あるいは(100010)の
場合、T←2T、T←T−P、T←2T、T←T+Qの
順に実行される演算、 (21)(100101)、あるいは(100110)の
場合、T←2T、T←T−P、T←2T、T←T−Qの
順に実行される演算、 (22)(001011)、あるいは(010011)の
場合、T←2T、T←T+Q、T←2T、T←T+Pの
順に実行される演算、 (23)(101011)あるいは(110011)の場
合、T←2T、T←T+Q、T←2T、T←T−Pの順
に実行される演算、 (24)(001100)、あるいは(010100)の
場合、T←2T、T←T−Q、T←2T、T←T+Pの
順に実行される演算、 (25)(101100)、あるいは(110100)の
場合、T←2T、T←T−Q、T←2T、T←T−Pの
順に実行される演算、のいずれかの演算を演算回路に指
示する処理プロセス、 演算回路が、前記制御回路からの指示にもとづき、順
次、記憶回路からP,Q,Tを入力して、前記指示され
た演算を実行し、演算結果のTを記憶回路に戻す処理プ
ロセス、をコンピュータで実行するためのプログラムが
記録されていることを特徴とする記録媒体。 Wherein the element F p to prime p, Equation 5] 2 on the elliptic curve Ep on the field Fp defined by
Let P and Q be points, and set two mutually independent integers c and d as follows : Expressed in binary as follows, and the coefficient of the i-th bit of c and d
Be c i , d i (ε {0, 1}), and c −1 = d −1 =
0, c 2k + 1 + c 2k + c 2k−1 ≠ 0, d 2k + 1 + d
By defining the maximum k such that 2k + d2k-1 ≠ 0 , the elliptic product sum calculation T = cP + dQ is calculated by a computer including a control circuit, a storage circuit, and a calculation circuit.
Elliptic product sum calculation program for automatic calculation by computer
A computer-readable recording medium in which
Then, the control circuit first sets the parameters P and Q and the calculation result.
T = 0 is stored in the memory circuit as the initial value of T, and then 2
From the set of integers c and d, i = k, k−1, ..., 2 , 1, 0
In this order, by sequentially shifting by 2 bits each, (c 2i + 1 c 2i c 2i-1 d 2i + 1 d 2i d 2i-1 ) is selected, and the selected (c 2i + 1 c 2i c 2i-1 d 2i + 1 d 2i
Based on the value of d 2i-1 ), (1) (000000) or (111000),
Ruiha (000111) or (111111)
In this case, the operation (2) (001000) or (010000), which is executed in the order of T ← 2T, T ← 2T ,
Ruiha (001111) or (010111)
In this case, T ← 2T, T ← 2T, T ← T + P are executed in this order.
Calculation (3) (000001) or (111001)
Ruiha (000010) or (11110)
In this case, T ← 2T, T ← 2T, T ← T + Q are executed in this order.
Calculation (4) (101000) or (110000)
Ruiha (101111) or (110111)
In this case, T ← 2T, T ← 2T, T ← TP are executed in this order.
Calculation (5) (000101), or (111101),
Ruiha (000110) or (111110)
In this case, T ← 2T, T ← 2T, T ← T-Q are executed in this order.
That operation, (6) (001001), or (010001), Oh
Ruiha (001010) or (010010)
In this case, T ← 2T, T ← 2T, T ← T + (P + Q) in that order.
Operation to be executed , (7) (001101), or (010101)
Ruiha (001110) or (010110)
In this case, T ← 2T, T ← 2T, T ← T + (P−Q) in that order.
The operation to be executed, (8) (101001), or (110001),
Ruiha (101010) or (110010)
In this case, T ← 2T, T ← 2T, T ← T- (PQ) in that order.
Operation to be executed, (9) (101101), or (110101)
Ruiha (101110) or (110110)
If T ← 2T, T ← 2T, T ← in the order of T- (P + Q)
The operation to be executed, (10) (011000), or (011111)
In this case, T ← 2T, T ← T + P, T ← 2T are executed in this order.
Calculation of (11) (000011) or (111011)
In this case, T ← 2T, T ← T + Q, T ← 2T are executed in this order.
Calculation of (12) (100000) or (100111)
In this case, T ← 2T, T ← TP, T ← 2T are executed in this order.
Calculation of (13) (000100) or (111100)
In this case, T ← 2T, T ← TQ, T ← 2T are executed in this order.
In the case of (14) (011011), T ← 2T, T ← T +
(P + Q), operation performed in the order of T ← 2T, (15) (011100), T ← 2T, T ← T +
(P-Q), operation performed in the order of T ← 2T, (16) (100011), T ← 2T, T ← T-
(P-Q), operation performed in the order of T ← 2T, (17) (100100), T ← 2T, T ← T-
(P + Q), operation performed in the order of T ← 2T, (18) (011001), or (011010)
In case of T ← 2T, T ← T + P, T ← 2T, T ← T + Q
Operation executed in order, (19) (011101), or (011110)
In case of T ← 2T, T ← T + P, T ← 2T, T ← T-Q
Operations that are executed in sequence, (20) (100001), or (100010)
In case of T ← 2T, T ← T-P, T ← 2T, T ← T + Q
Calculations executed in sequence, (21) (100101), or (100110)
In case of T ← 2T, T ← T-P, T ← 2T, T ← T-Q
Calculations that are executed in sequence, (22) (001011), or (010011)
In case of T ← 2T, T ← T + Q, T ← 2T, T ← T + P
Calculations executed in sequence, in the case of (23) (101011) or (110011)
, T ← 2T, T ← T + Q, T ← 2T, T ← TP
The operation executed in (24) (001100) or (010100)
In case of T ← 2T, T ← T−Q, T ← 2T, T ← T + P
The operation to be executed in order, (25) (101100), or (110100)
In case of T ← 2T, T ← T-Q, T ← 2T, T ← TP
The operation circuit is instructed to perform one of the operations executed in order.
Shimesuru treatment process, the arithmetic circuit, based on an instruction from the control circuit, the order
Next, input P, Q, T from the memory circuit
The processing process for executing the calculated calculation and returning the calculation result T to the memory circuit.
Process for running computer
A recording medium characterized by being recorded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34659198A JP3460798B2 (en) | 1998-11-19 | 1998-11-19 | Elliptic product-sum calculation method, elliptic-product-sum calculation device, and recording medium storing elliptic-product-sum calculation program |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34659198A JP3460798B2 (en) | 1998-11-19 | 1998-11-19 | Elliptic product-sum calculation method, elliptic-product-sum calculation device, and recording medium storing elliptic-product-sum calculation program |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000155526A JP2000155526A (en) | 2000-06-06 |
| JP3460798B2 true JP3460798B2 (en) | 2003-10-27 |
Family
ID=18384472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34659198A Expired - Lifetime JP3460798B2 (en) | 1998-11-19 | 1998-11-19 | Elliptic product-sum calculation method, elliptic-product-sum calculation device, and recording medium storing elliptic-product-sum calculation program |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3460798B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4644039B2 (en) * | 2005-05-27 | 2011-03-02 | 日本電信電話株式会社 | Pairing calculation method, apparatus and program using the method |
-
1998
- 1998-11-19 JP JP34659198A patent/JP3460798B2/en not_active Expired - Lifetime
Non-Patent Citations (3)
| Title |
|---|
| 3次曲線に基づく公開鍵暗号,NTT R&D,1995年10月10日,Vol.44, No.10,p.91−98 |
| More Flexible Exponentiation with Precomputataion,Lecture Notes in Computer Science,Vol.839,p.95−107 |
| The Fast Cascade Exponentiation Algorithm and its Application on Cryptography,Lecture Notes in Computer Science,Lecture Notes in Computer Science,p.447−456 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000155526A (en) | 2000-06-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6466668B1 (en) | IC card equipped with elliptical curve encryption processing facility | |
| Öztürk et al. | Low-power elliptic curve cryptography using scaled modular arithmetic | |
| US7486789B2 (en) | Device and method for calculation on elliptic curve | |
| US20110161390A1 (en) | Modular multiplication processing apparatus | |
| US7046800B1 (en) | Scalable methods and apparatus for Montgomery multiplication | |
| KR101154845B1 (en) | Scalar multiplier and scalar multiplication program | |
| JP2006145852A (en) | Montgomery conversion device, arithmetic device, IC card, encryption device, decryption device, and program | |
| CN101971138B (en) | An apparatus and a method for calculating a multiple of a point on an elliptic curve | |
| Wollinger | Computer architectures for cryptosystems based on hyperelliptic curves. | |
| JP3460798B2 (en) | Elliptic product-sum calculation method, elliptic-product-sum calculation device, and recording medium storing elliptic-product-sum calculation program | |
| US8417760B2 (en) | Device and method for calculating a multiplication addition operation and for calculating a result of a modular multiplication | |
| US7016927B2 (en) | Method and apparatus for modular multiplication | |
| US8364737B2 (en) | Device and method for calculating a result of a sum with a calculating unit with limited word length | |
| JP4341889B2 (en) | Elliptical product-sum operation calculation method, elliptic product-sum operation calculation device, program, and recording medium | |
| Anagreh et al. | Accelerate Performance for Elliptic Curve Scalar Multiplication based on NAF by Parallel Computing. | |
| JP4202701B2 (en) | Polynomial residue arithmetic unit, method and program | |
| JP3390966B2 (en) | Remainder arithmetic device modulo square number and program recording medium therefor | |
| KR100564764B1 (en) | Finite Field Polynomial Multiplication Apparatus and Method | |
| JP2001265218A (en) | Calculation method and device on elliptic curve, and recording medium storing calculation program | |
| JP3638493B2 (en) | Elliptic curve square computing device and program recording medium | |
| JP2006507516A (en) | Inverse calculation of values | |
| Baktır | Efficient algorithms for finite fields, with applications in elliptic curve cryptography | |
| JP3604126B2 (en) | Cyclic window addition apparatus, method therefor and program recording medium therefor | |
| JP2007526513A (en) | Method of element power or scalar multiplication | |
| US7337203B2 (en) | Exponent calculation apparatus and method, and program |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080815 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080815 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090815 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090815 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100815 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100815 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110815 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120815 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130815 Year of fee payment: 10 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| EXPY | Cancellation because of completion of term |