JP3462829B2 - Gaming machine - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine such as a pachinko gaming machine, a coin gaming machine, or a slot machine, in which a game is played according to a player's operation. A gaming machine in which a game is played according to

[0002]

2. Description of the Related Art As a game machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium is won in a prize area such as a winning opening provided in the game area, a predetermined number of prize balls are provided. There are things that are paid out to the player.
Furthermore, a variable display unit whose display state can be changed is provided,
There is one configured to give a predetermined game value to the player when the display result of the variable display section becomes a predetermined specific display mode.

The game value means that the state of the variable winning ball device provided in the game area of the gaming machine is advantageous for a player who easily wins a hit ball, or is advantageous for the player. That is, the right is generated, or the condition for paying out the prize game medium is easily established. Further, when a predetermined amount of game balls or coins are awarded or points are added in accordance with the establishment of a predetermined condition such as winning, they are called valuable value.

In a pachinko gaming machine, it is usually called "big hit" that the display result of the variable display section for displaying a special symbol is a combination of predetermined specific display modes. When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and a big hit game state in which a hit ball is easy to win is entered. Then, in each opening period, a predetermined number (for example, 10
If there is a prize in the prize hole, the prize hole will close.
The number of times the special winning opening is opened is a predetermined number (for example, 16
Round) has been fixed. An opening time (for example, 29.5 seconds) is determined for each opening, and the special winning opening is closed when the opening time elapses even if the number of winnings does not reach a predetermined number. In addition, when the special winning opening is closed, a predetermined condition (for example, winning in a V zone provided in the special winning opening)
When is not established, the jackpot gaming state ends.

Of the combinations of display modes other than the "big hit" combination, some of the display results of the plurality of variable display portions have not yet been derivatized and displayed, and are already definite or temporary. A state in which the display mode of the variable display section in which such a display result is derived and displayed satisfies the display condition of a combination of specific display modes is referred to as “reach”. Then, when the display result of the identification information variably displayed on the variably display portion does not satisfy the condition of "big hit", the result is "disappear" and the variably display state ends. A player plays a game while enjoying how to generate a big hit.

When the game balls are won in the winning opening provided on the game board, a predetermined number of prize balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of prize balls based on the winning is determined by the game control means,
It is transmitted to the payout control board on which the payout control means is mounted. In the following, the control means other than the game control means may be referred to as electric component control means. Further, the payout control means is an example of a value giving control means.

Further, in such a gaming machine, a speaker is provided, and in order to enhance the game effect, various sound effects are emitted from the speaker as the game progresses. Further, light emitting bodies such as lamps and LEDs are provided in the game area and frame of the gaming machine, and these light emitting bodies are turned on or off as the game progresses in order to enhance the game effect. Since the sound from the speaker and the turning on / off of each light emitter are controlled according to the progress of the game, those controls are generally performed as follows.
It is performed by the game control means for controlling the progress of the game.
In that case, if a voice control means which is provided separately from the game control means and performs a specific control on the speaker and a light emitter control means that performs a specific control on the light emitter are provided, the control load on the game control means is lightened. be able to.

[0008]

When various electric component control means are provided separately from the game control means,
A control command must be transmitted from the game control means to each electric component control means. If the control commands are not reliably received by the electric component control control means, the control of the gaming machine is hindered. For example, if the payout control means erroneously receives the control command, the prize balls may not be paid out, or the wrong number of prize balls may be paid out. If the voice control means or the lamp control means erroneously receives the control command, it is possible that the player cannot feel the effect according to the progress of the game and give a suspicious feeling to the player.

Further, when the type of microcomputer used as each electric component control means is different,
The time required for each electric component control means to fetch a command may vary. Then, even if the command transmission control of the game control means for a certain electric component control control means is appropriate, if the command transmission control is applied to the command transmission processing for another electric component control control means, the electric component control control means There is a possibility that the command cannot be imported correctly.

Therefore, according to the present invention, in a gaming machine having a structure in which a command is sent from the game control means to a plurality of other electric component control means, the game control means reliably sends a command to each electric component control means. It is an object of the present invention to provide a gaming machine capable of transmitting the game data and further saving the program capacity of the game control means.

[0011]

A gaming machine according to the present invention comprises:
A game machine that allows a player to play a predetermined game, and a plurality of types of game control means for controlling the progress of the game, and an electric part control process for controlling electric parts provided in the game machine. Command output means including electric component control means, and game control means executing command output processing for outputting command data and a capture signal designating capture of command data to a plurality of types of electrical component control means. The command output process is commonly used to output command data and a capture signal to a plurality of types of electrical component control means, and the command output process outputs the command data and capture signal in the command output process. Is output, the next command data is output after a lapse of a predetermined time, and each of the plurality of types of electric component control means receives the command data for a predetermined period. Characterized in that it is a maximum constant value over the period of time required in order.

One command information sent to the electric component control means is composed of, for example, two command data.

The command output means may be configured to be able to output one command data and the next command data in a distinguishable manner.

The command output means is configured to maintain the output of the command data until the predetermined period has elapsed.

The game control means may be configured to have an area capable of simultaneously storing a plurality of commands to be output.

The command output process may be configured to include a process of determining to which of the plural kinds of electric component control means the electric component control means is to output the command data.

The predetermined period until the next command data is output is preferably longer than the period from the output of the command data to the output of the capture signal.

The electric component control means includes, for example, a value giving control means for giving a valuable value to a player when a predetermined condition is satisfied, and the value giving control means can store a plurality of inputted command data at the same time. May be configured as follows.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 seen from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the mechanism board of the pachinko gaming machine 1 seen from the back. In the following embodiments, a pachinko gaming machine will be described as an example, but the gaming machine according to the present invention is not limited to a pachinko gaming machine.
For example, it may be a coin game machine or the like. Further, it can be applied to an image-type game machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1 is
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing the reserved balls overflowing from the hitting ball supply tray 3 and a hitting ball operation handle (operation knob) 5 for firing the hit ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. Further, a game area 7 is provided on the front surface of the game board 6.

In the vicinity of the center of the game area 7, a variable display section 9 for variably displaying a plurality of types of symbols and a 7 segment L
A variable display device 8 including a variable display 10 by an ED is provided. Further, a passage memory indicator (normal symbol memory indicator) 41 composed of four LEDs is provided below the variable indicator 10. In this embodiment, the variable display section 9 has three symbol display areas of "left", "middle", and "right". On the side of the variable display device 8, a pass gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passage gate 11 is guided to the starting winning opening 14 through the ball outlet 13. In the passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 that detects a hit ball that has passed through the passage gate 11. In addition, the winning ball that has entered the starting winning opening 14 is guided to the back of the game board 6 and the starting opening switch 17
Detected by. A variable winning ball device 15 that opens and closes is provided below the starting winning opening 14.
The variable winning ball device 15 is opened by the solenoid 16.

At the lower part of the variable winning ball device 15, an opening / closing plate 20 is provided which is opened by a solenoid 21 in a specific game state (big hit state). In this embodiment, the opening / closing plate 20 serves as a means for opening / closing the special winning opening. The winning ball that enters one (V zone) of the winning balls guided from the opening / closing plate 20 to the back surface of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
In the lower part of the, there is provided a start winning prize memory display 18 having four display parts for displaying the number of winning balls that have entered the starting winning opening 14. In this example, with the upper limit of four, each time there is a start prize, the start prize memory display device 18 increases the number of lit display portions by one. Then, each time the variable display of the variable display unit 9 is started, the number of the display units that are turned on is reduced by one.

The game board 6 is provided with a plurality of winning openings 19 and 24, and the winning of the gaming balls to the respective winning openings 19 and 24 is provided with corresponding winning opening switches 19a and 19a.
24a. Decorative lamps 25 that are displayed blinking during the game are provided around the left and right sides of the game area 7, and there is an outlet 26 at the bottom for absorbing hit balls that have not been won. Also, on the upper left and right outside the game area 7,
Two speakers 27 are provided which emit sound effects.
A game effect LED 28a and game effect lamps 28b and 28c are provided on the outer periphery of the game area 7.

In this example, one speaker 27
A prize ball lamp 51 that lights up when the prize ball is paid out is provided in the vicinity of, and a ball-out lamp 52 that lights up when the supply ball runs out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 which is installed adjacent to the pachinko gaming machine 1 and allows a ball lending by inserting a prepaid card.

In the card unit 50, a usable indicator lamp 151 indicating whether or not the card unit 50 is usable, and a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. A fraction display switch 1 for displaying on a frequency display LED provided in the vicinity of the hit ball supply tray 3
52, the connection stand direction indicator 15 showing which side the pachinko gaming machine 1 the card unit 50 corresponds to
3, a card insertion display lamp 154 indicating that a card has been inserted into the card unit 50, a card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back surface of the card insertion slot 155. A card unit lock 156 is provided for releasing the card unit 50 when checking the mechanism of the writer.

The batted ball launched from the batted ball launching device enters the game area 7 through the batted ball rail, and then the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the displayed number on the variable display 10 is continuously changed. Further, when the ball hits the start winning opening 14 and is detected by the start opening switch 17, if the variation of the symbol can be started, the symbol in the variable display portion 9 starts to rotate. If it is not in a state where the variation of the symbol can be started, the start winning memory is incremented by 1.

The rotation of the image in the variable display section 9 is stopped when a certain time has elapsed. When the combination of the images at the time of stop is the combination of the big hit symbols, the big hit game state is entered. That is, the opening / closing plate 20 is opened until a certain period of time elapses or until a predetermined number (for example, 10) of hit balls are won. Then, when a hit ball enters the specific winning area and is detected by the V count switch 22 while the opening / closing plate 20 is open, a continuation right is generated and the opening / closing plate 20 is opened again. The continuation right can be generated a predetermined number of times (for example, 15 rounds).

When the combination of the images in the variable display portion 9 at the time of stop is the combination of the big hit symbols accompanied by the probability variation, the probability of the big hit next increases. That is, the high probability state is more advantageous for the player. Further, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening the variable winning ball device 15 are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the rear surface of the variable display device 8, as shown in FIG. 2, a ball storage tank 38 is provided on the upper part of the mechanism plate 36, and the game ball is from above the pachinko game machine 1 in a state where it is installed on the game machine installation island. Sphere storage tank 3
8 are supplied. The game balls in the ball storage tank 38 reach the ball payout device through the guide gutter 39.

On the mechanism plate 36, a variable display control unit 29 for controlling the variable display section 9 via the relay board 30, a game control board covered with a board case 32 and having a game control microcomputer mounted thereon (main board). ) 31, a relay substrate 33 for relaying signals between the variable display control unit 29 and the game control board 31, and a payout control board 37 on which a prize ball control microcomputer for controlling the payout of game balls is mounted. Is installed. Further, in the lower part of the mechanism plate 36, a hitting ball is utilized in the game area 7 by utilizing the rotational force of the motor.
A ball-striking device 34 for launching to a game effect lamp / LE
D28a, 28b, 28c, a prize ball lamp 51 and a lamp control board 35 for sending signals to the out-of-ball lamp 52 are installed.

FIG. 3 is a rear view of the mechanism board of the pachinko gaming machine 1 as viewed from the back. The balls stored in the ball storage tank 38 pass through the guide trough 39, and as shown in FIG. 3, pass the ball break detectors (ball break switches) 187a and 187b, and then the ball supply troughs 186a and 186b to dispense the balls. Device 9
To 7. The out-of-ball switches 187a and 187b are switches for detecting the presence / absence of game balls in the game ball passage, but a out-of-ball detection switch 167 for detecting the shortage of supply balls in the ball tank 38 is also provided. The game balls paid out from the ball payout device 97 are supplied to the hitting ball supply plate 3 provided on the front surface of the pachinko gaming machine 1 through the communication port 45.
A surplus ball passage 46 communicating with the surplus ball tray 4 provided on the front surface of the pachinko gaming machine 1 is formed on the side of the communication port 45. A large number of prize balls based on winnings are paid out, the hitting ball supply tray 3 becomes full, and finally when the game balls reach the communication port 45 and further game balls are paid out, the game balls are surplus through the surplus ball passage 46. Guided to the ball saucer 4. When the game ball is further paid out, the sensing lever 47 pushes the full tank switch 48 and the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball payout device 97 is stopped, the operation of the ball payout device 97 is stopped, and the driving of the hitting ball launching device 34 is stopped.

Next, the structure of the intermediate base unit installed on the mechanism plate 36 will be described. The intermediate base unit includes a ball supply gutter 186a, 186b and a ball dispensing device 9
7 is installed. As shown in FIG. 4, connecting concave protrusions 182 are formed above and below the intermediate base unit. The connecting concave protrusion 182 connects and fixes the intermediate base unit and the upper base unit and the lower base unit of the mechanism plate 36.

A passage member 18 is provided above the intermediate base unit.
4 is fixed. The ball payout device 97 is fixed to the lower portion of the passage body 184. The passage body 184 is a payout ball passage 186 for letting down the two rows of game balls whose flow-down direction has been converted to the left-right direction by the curve gutter 174 (see FIG. 3).
a, 186b. Delivery ball passage 186a, 186b
Ball cut switches 187a and 187b are installed on the upstream side of. The ball break switches 187a and 187b are
The presence or absence of a game ball in the payout ball passage 186a, 186b is detected, and the ball break switch 187a, 187b is detected.
When the game ball is no longer detected, the rotation of the payout motor (not shown in FIG. 4) in the ball payout device 97 is stopped and the ball payout is immobilized.

The out-of-ball switches 187a, 187b
Is locked by a locking piece 188 at a position where it is possible to detect the presence of about 27 to 28 gaming balls in the payout ball passages 186a, 186b. That is, the out-of-ball switches 187a and 187b are the maximum payout amount of one unit of prize balls (15 in this embodiment) and the maximum payout amount of one unit of ball lending (100 yen: 25 in this embodiment).
It is installed at a position where the above can be confirmed.

The central portion of the passage body 184 is formed in a curved shape to the left and right so as to weaken the ball pressure of the game ball flowing down inside. And the payout ball passages 186a, 186b
A stop hole 189 is formed between them. A mounting boss provided on the intermediate base unit is fitted into the back surface of the stop hole 189. In that state, the set screw is screwed,
The passage body 184 is fixed to the intermediate base unit. It should be noted that the passage body 184 can be aligned with the locking projection 185 provided on the intermediate base unit before being screwed.

Below the passage body 184, a ball payout device 97 is provided.
A game ball is supplied to the game machine and a ball payout device 9 is provided in the event of a malfunction.
A ball stopping device 190 for stopping the supply of the game balls to 7 is provided. The ball dispensing device 97 installed below the ball stopping device 190 is housed inside a rectangular parallelepiped case 198. Protrusions are provided at four positions on the left and right of the case 198. The lower end of the case 198 is fitted into the elastic engaging piece provided in the lower portion of the intermediate base unit in a state where each of the projecting portions is engaged with the positioning projecting piece provided in the intermediate base unit.

FIG. 5 is an exploded perspective view of the ball payout device 97. The configuration and operation of the ball payout device 97 will be described with reference to FIG. Ball dispensing device 97 in this embodiment
The stepping motor (delivery motor) 289 rotates the screw 288 to deliver the pachinko balls one by one. The ball payout device 97 pays out not only prize balls based on winning prizes but also game balls to be lent.

As shown in FIG. 5, the ball payout device 97 has two
It has two cases 198a and 198b. The ball payout device 9 is provided at two positions on the left and right of each case 198a and 198b.
An engaging projection 280 is provided that abuts a positioning projection provided on the upper portion of the installation position of No. 7. Further, in each case 198a, 198b, a ball supply path 281a, 2 is provided.
81b is formed. Sphere supply path 281a, 281b
Has curved surfaces 282a and 282b,
Below the end of 282b, the ball feed horizontal path 284a, 2
84b is formed. Further, the ball feeding horizontal path 284
Ball discharge paths 283a and 283b are formed at the ends of a and 284b.

Ball supply paths 281a, 281b, ball feed horizontal paths 284a, 284b, ball discharge paths 283a, 283b.
Are formed in front of partition walls 295a and 295b that partition the cases 198a and 198b into front and rear, respectively.
Further, the ball pressure cushioning member 285 is sandwiched between the cases 198a and 198b in front of the partition walls 295a and 295b. The ball pressure buffering member 285 distributes the balls supplied to the ball payout device 97 to the left and right sides to distribute the ball supply paths 281a, 281a, 2b.
Lead to 81b.

Further, below the ball pressure buffer member 285, there is provided a payout motor position sensor including a light emitting element (LED) 286 and a light receiving element (not shown). Light emitting element 2
86 and the light receiving element are provided with a predetermined gap. Then, the tip of the screw 288 is inserted into this space. The ball pressure cushioning member 28
When the cases 198a and 198b are attached to each other, 5 is completely housed and fixed in the inside.

A screw 28 rotated by a payout motor 289 is provided in each of the ball feeding horizontal paths 284a and 284b.
8 are arranged. The payout motor 289 is fixed to the motor fixing plate 290, and the motor fixing plate 290 defines the partition wall 29.
Fixing grooves 291a, 2 formed behind 5a, 295b
It is fitted in 91b. In this state, the motor shaft of the payout motor 289 projects in front of the partition walls 295a and 295b, so that the screw 288 is fixed in front of the projection. On the outer periphery of the screw 288, a spiral protrusion 288a for moving the game balls placed on the ball feeding horizontal paths 284a, 284b forward by the rotation of the payout motor 289.
Is provided.

A recess is formed at the tip of the screw 288 so as to house the light emitting element 286, and two notches 292 are formed 180 degrees apart from each other on the outer periphery of the recess. Therefore, while the screw 288 makes one rotation, the light from the light emitting element 286 is not emitted from the notch 292.
Is detected twice by the light receiving element via.

That is, the payout motor position sensor including the light emitting element 286 and the light receiving element serves to stop the screw 288 at a fixed position and detects that the payout operation has been performed. The wirings from the light emitting element 286, the light receiving element and the payout motor 289 are collected and led out to the outside from the lead holes formed in the lower rear portions of the cases 198a and 198b and connected to the connector.

A game ball is a ball feeding horizontal path 284a, 284b.
When the payout motor 289 rotates in the state of being mounted on the
The game ball moves forward on the ball feed horizontal paths 284a and 284b. And finally, the ball feeding horizontal path 28
4a, 284b to the ball discharge path 283a, 283b
To fall. At this time, the left and right ball feed horizontal paths 284a,
The drops from 284b are alternated. That is, every time the screw 288 makes a half rotation, one game ball falls from one side. Therefore, the light from the light emitting element 286 is detected by the light receiving element each time one game ball falls.

As shown in FIG. 4, a ball distributing member 311 is provided below the ball payout device 97. The ball distribution member 311 is driven by the distribution solenoid 310. For example, when the solenoid 310 is turned on, the ball distribution member 311 is tilted to the right, and when it is turned off, it is tilted to the left. Below the distribution solenoid 310, a prize ball count switch 301A and a ball lending count switch 301B, which are proximity switches, are provided. At the time of a prize ball based on winning, the ball sorting member 311 falls to the right side, and the ball discharge path 283.
Balls from a and 283b are both prize ball count switches 3
Pass 01A. Also, when lending a ball, the ball distribution member 3
11 falls to the left, and the balls from the ball discharge paths 283a and 283b both pass the ball lending count switch 301B. Therefore, the ball payout device 97 can switch the payout flow-down path between the time of winning the ball and the time of lending the ball to pay out a predetermined number of game media.

As described above, by providing the ball distributing member 311, the balls that have fallen in the two ball passages are the prize ball count switch 301A and the ball lending count switch 30.
Only one of 1B and 1B passes. Therefore,
The number of prize balls or the number of ball lends can be immediately grasped from the detection output of the prize ball count switch 301A and the ball lend count switch 301B without determining whether it is a prize ball or a ball lend.

In this embodiment, a ball payout device 97 for paying out game balls by rotating a stepping motor is used as a ball payout device for paying out game balls by driving an electric drive source. You may use the ball payout device of the structure which sends out a game ball by the drive source, or you may use the ball payout device of the structure which removes a stopper by the drive of an electric drive source and pays out by the own weight of the game ball.

FIG. 6 is a block diagram showing an example of the circuit configuration of the main board 31. Note that FIG. 6 also shows the payout control board 37, the lamp control board 35, the sound control board 70, the firing control board 91, and the display control board 80.
On the main board 31, the pachinko gaming machine 1 according to the program
And a basic circuit 53 for controlling the gate switch 12, the start switch 17, the V count switch 22, the count switch 23, the winning opening switches 19a, 24a and the prize ball counting switch 301A switch circuit 58 for giving the basic circuit 53 a signal. A solenoid circuit 59 for driving the solenoid 16 for opening and closing the variable winning ball device 15, the solenoid 21 for opening and closing the opening and closing plate 20, and the like according to a command from the basic circuit 53 are mounted.

Further, in accordance with the data given from the basic circuit 53, big hit information indicating occurrence of big hit, effective starting information indicating the number of starting winning balls used for starting image display on the variable display section 9, and probability variation. An information output circuit 64 that outputs the probability variation information indicating that to a host computer such as a hall management computer is included.

The basic circuit 53 includes a ROM 54 for storing a program for controlling a game and the like, a RAM 55 as an example of a storage unit used as a work memory, a CPU 56 for performing a control operation according to the program, and an I / O port section 5.
Including 7. In this embodiment, the ROM 54 and the RAM 5
5 is built in the CPU 56. That is, the CPU 5
6 is a one-chip microcomputer. 1
The chip microcomputer has at least a RAM 55
The ROM 54 and the I / O port portion 57 may be externally attached or may be incorporated. The I / O port unit 57 is a terminal capable of inputting / outputting information in the microcomputer.

Further, on the main board 31, any one of a system reset circuit 65 for resetting the basic circuit 53 when the power is turned on and an I / O port unit 57 for decoding an address signal given from the basic circuit 53. I /
An address decode circuit 67 for outputting a signal for selecting the O port is provided. In addition, the ball dispensing device 9
There is also switch information input from 7 to the main board 31,
They are omitted in FIG.

The hit ball launching device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 controls the ball to be fired at a speed according to the operation amount of the operation knob 5.

In this embodiment, the lamp control means mounted on the lamp control board 35 displays the start memory indicator 18, the gate passage memory indicator 41 and the decorative lamp 25 provided on the game board. While controlling, the game effect lamp and LED28 which are provided on the frame side
The display control of the a, 28b, 28c, the prize ball lamp 51, and the out-of-ball lamp 52 is performed. Here, the lamp control means is an example of the light emitter control means. Further, the display control of the variable display unit 9 that variably displays the special symbol and the variable display 10 that variably displays the normal symbol is performed by the display control means mounted on the display control board 80.

FIG. 7 shows a circuit configuration in the display control board 80, which is an example of realizing the variable display section 9 such as an LCD (liquid crystal display device) 82, a variable display 10, and an output port (port 0, 0) of the main board 31. 2) A block diagram shown together with 570 and 572 and output buffer circuits 620 and 62A. 8-bit data is output from the output port (output port 2) 572, and a 1-bit strobe signal (INT signal) is output from the output port 570.

The display control CPU 101 controls the control data R
It operates according to the program stored in the OM 102, and when the INT signal is input from the main board 31 via the noise filter 107 and the input buffer circuit 105B, the display control command is received via the input buffer circuit 105A. As the input buffer circuits 105A and 105B, for example, general-purpose ICs 74HC540 and 74HC14 can be used. If the display control CPU 101 does not include an I / O port, an I / O port is provided between the input buffer circuits 105A and 105B and the display control CPU 101.

Then, the display control CPU 101 controls the display of the screen displayed on the LCD 82 in accordance with the received display control command. Specifically, the VDP 103 is given a command according to the display control command. VDP103
Reads out the necessary data from the character ROM 86. The VDP 103 displays the LCD 8 according to the input data.
Image data to be displayed on the LCD 2 is generated, and R, G, B signals and synchronizing signals are output to the LCD 82.

FIG. 7 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for giving an operating clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image including characters, figures, symbols, or the like displayed on the LCD 82.

The input buffer circuits 105A and 105B are
The signal can be passed only in the direction from the main board 31 to the display control board 80. Therefore, the display control board 8
There is no room for signals to be transmitted from the 0 side to the main board 31 side. That is, the input buffer circuits 105A and 105B constitute an irreversible information input means together with the input ports. Even if the circuit in the display control board 80 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side.

The outputs of the output ports 570 and 572 may be directly output to the display control board 80, but output buffer circuits 620 and 62A capable of transmitting signals only in one direction.
By providing the display control board 8 from the main board 31.
One-way signal transmission to 0 can be made more reliable. That is, the output buffer circuits 620 and 62A form an irreversible information output unit together with the output ports.

Further, as the noise filter 107 for blocking high frequency signals, for example, a three-terminal capacitor or ferrite beads is used. Even if noise exists between the substrates in the display control command due to the presence of the noise filter 107, that noise will be generated. The effect is eliminated. A noise filter may be provided on the output side of the buffer circuits 620 and 62A of the main board 31.

FIG. 8 is a block diagram showing signal transmitting / receiving portions of the main board 31 and the lamp control board 35.
In this embodiment, a game effect LED 28a and game effect lamps 28b, 28 provided outside the game area 7 are provided.
c and lighting of the decorative lamp 25 provided on the game board, lighting of the prize ball lamp 51 and the ball out lamp 52 /
A lamp control command indicating turning off is output from the main board 31 to the lamp control board 35. In addition, the starting memory indicator 1
8 and the lamp control command indicating the number of gate passing memory indicators 41 to be lit is also transmitted from the main board 31 to the lamp control board 35.
Is output to.

As shown in FIG. 8, the lamp control commands relating to the lamp control are output ports (output ports 0, 3) 570, 5 of the I / O port section 57 in the basic circuit 53.
It is output from 73. Output port (output port 3) 57
3 outputs 8-bit data, and output port 570 outputs 1
The bit INT signal is output. In the lamp control board 35, the control command from the main board 31 is sent to the lamp control CPU via the input buffer circuits 355A and 355B.
351 is input. If the lamp control CPU 351 does not have an internal I / O port, an I / O port is provided between the input buffer circuits 355A and 355B and the lamp control CPU 351.

In the lamp control board 35, the CPU 351 for lamp control has the game effect LED 28a and the game effect lamps 28b, 2 defined according to each control command.
8c, according to the lighting pattern of the decorative lamp 25,
Game effect LED 28a, game effect lamps 28b, 28
c, output a lighting / extinguishing signal to the decoration lamp 25. The lighting / extinguishing signal is output to the game effect LED 28a, the game effect lamps 28b and 28c, and the decoration lamp 25. The lighting / extinguishing pattern is based on the lamp control CPU.
It is stored in the built-in ROM of 351 or the external ROM.

On the main board 31, the CPU 56 controls the RA
When there is an unpaid remaining number of prize balls in the stored contents of M55, a control command for instructing lighting of the prize ball lamp 51 is output, and is installed upstream of the payout ball passages 186a and 186b on the back surface of the game board. Ball break switch 187a, 187b
When the game ball is no longer detected (see FIG. 3), a control command for instructing lighting of the out-of-ball lamp 52 is output. In the lamp control board 35, each control command is sent to the lamp control CPU via the input buffer circuits 355A and 355B.
351 is input. The lamp control CPU 351 turns on / off the prize ball lamp 51 and the out-of-ball lamp 52 according to the control commands. The lighting / extinguishing pattern is stored in the built-in ROM or the external ROM of the lamp control CPU 351.

Further, the lamp control CPU 351 outputs a lighting / extinguishing signal to the start memory indicator 18 and the gate passage memory indicator 41 in response to the control command.

The input buffer circuits 355A and 355B are, for example, 74HC54 which is a general-purpose CMOS-IC.
0.74HC14 is used. Input buffer circuit 35
5A and 355B are the main board 31 and the lamp control board 35.
The signal can only be passed in the direction towards. Therefore, there is no room for signals to be transmitted from the lamp control board 35 side to the main board 31 side. Even if the circuit in the lamp control board 35 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side. A noise filter may be provided on the input side of the input buffer circuits 355A and 355B.

On the main board 31, the output port 5
Buffer circuits 620 and 63A are provided outside the 70 and 573. The buffer circuits 620 and 63A are, for example, 74HC250 and 7 that are general-purpose CMOS-ICs.
4HC14 is used. According to such a configuration, a signal input from the outside to the inside of the main board 31 is blocked, so that a signal line that may give a signal from the lamp control board 70 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 63A.

FIG. 9 is a block diagram showing a configuration example of the signal transmission portion of the voice control command on the main board 31 and the voice control board 70. In this embodiment, a voice control command for instructing the voice output of the speaker 27 provided outside the game area 7 according to the progress of the game,
Output from the main board 31 to the voice control board 70.

As shown in FIG. 9, the voice control command is
It is output from the output ports (output ports 0, 4) 570 and 574 of the I / O port unit 57 in the basic circuit 53.
8-bit data is output from the output port (output port 4) 574, and 1-bit I is output from the output port 570.
The NT signal is output. In the voice control board 70, each signal from the main board 31 is input to the input buffer circuit 705A,
Input to the voice control CPU 701 via 705B.
If the voice control CPU 701 does not include an I / O port, the input buffer circuits 705A and 705
An I / O port is provided between B and the voice control CPU 701.

Then, for example, the voice synthesizing circuit 702 using a digital signal processor is provided with the voice control CPU 7
A sound or sound effect according to the instruction 01 is generated and output to the volume switching circuit 703. The volume switching circuit 703 sets the output level of the voice control CPU 701 to a level according to the set volume and outputs the output level to the volume amplification circuit 704. The volume amplifier circuit 704 outputs the amplified audio signal to the speaker 27.

The input buffer circuits 705A and 705B are, for example, 74HC54 which is a general-purpose CMOS-IC.
0.74HC14 is used. Input buffer circuit 70
5A and 705B can pass signals only in the direction from the main board 31 to the voice control board 70. Therefore, there is no room for signals to be transmitted from the voice control board 70 side to the main board 31 side. Therefore, even if the circuit in the voice control board 70 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side. A noise filter may be provided on the input side of the input buffer circuits 705A and 705B.

On the main board 31, the output port 5
Buffer circuits 620 and 67A are provided outside 70 and 574, respectively. The buffer circuits 620 and 67A are, for example, 74HC250 and 7 that are general-purpose CMOS-ICs.
4HC14 is used. According to such a configuration, a signal input from the outside to the inside of the main board 31 is blocked, so that a signal line that may give a signal from the voice control board 70 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 67A.

FIG. 10 is a block diagram showing components related to payout, such as the components of the payout control board 37 and the ball payout device 97. As shown in FIG. 10, the detection signal from the full tank switch 48 is input to the I / O port 57 of the main board 31 via the relay board 71. The full tank switch 48 is a switch for detecting a full tank of the surplus ball receiving tray 4. In addition, the ball break switch 187 (187a, 187)
The detection signal from b) is also applied to the relay board 72 and the relay board 7.
1 is input to the I / O port 57 of the main board 31.

The CPU 56 of the main board 31 determines whether the detection signal from the ball break switch 187 indicates the ball break condition.
Alternatively, when the detection signal from the full tank switch 48 indicates a full tank state, a payout control command for instructing prohibition of payout is transmitted. When the payout control command instructing the payout prohibition is received, the payout control CPU 37 of the payout control board 37
1 stops the ball payout process.

Further, the detection signal from the prize ball count switch 301A is also input to the I / O port 57 of the main board 31 via the relay boards 72 and 71. The prize ball count switch 301A is provided in the payout mechanism portion of the ball payout device 97, and detects the actually paid prize ball payout ball.

When there is a winning, the payout control board 37 has output ports (ports 0, 1) 570, 571 of the main board 31.
A payout control command indicating the number of prize balls is input from. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit strobe signal (INT signal). The payout control command indicating the number of prize balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371 is
A payout control command is input via the / O port 372a, and the ball payout device 97 is driven according to the payout control command to pay a prize ball. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and has at least a built-in RAM.

On the main board 31, the output port 5
Buffer circuits 620 and 68A are provided outside the 70 and 571. The buffer circuits 620 and 68A are, for example, 74HC250 and 7 which are general-purpose CMOS-ICs.
4HC14 is used. According to such a configuration, a signal input from the outside to the inside of the main board 31 is blocked, so that the signal line that may give a signal from the payout control board 37 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 68A.

The payout control CPU 371 uses the output port 3
A ball lending number signal indicating the number of lent balls is output to the terminal board 160 and a buzzer drive signal is output to the buzzer board 75 via 72g. A buzzer is mounted on the buzzer board 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

Further, the input port 3 of the payout control board 37
Detection signals from the prize ball count switch 301A and the ball lending count switch 301B are input to 72b via the relay board 72. Ball lending count switch 3
01B is provided in the payout mechanism portion of the ball payout device 97,
Detects the actually loaned ball. Discharge control board 3
The drive signal from 7 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72.

A card unit control microcomputer is mounted on the card unit 50. Also,
The card unit 50 is provided with a fraction display switch 152, a connecting board direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155 (see FIG. 1). To the balance display board 74, a frequency display LED, a ball lending switch and a return switch, which are provided in the vicinity of the hitting ball supply tray 3, are connected.

From the balance display board 74 to the card unit 50
A ball lending switch signal and a return switch signal are given to the player through the payout control board 37 according to the operation of the player. In addition, the balance display board 74 from the card unit 50
A card balance display signal indicating the balance of the prepaid card and a ball lending allowance display signal are given to the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal) and a unit operation signal (B
RDY signal), ball lending request signal (BRQ signal), ball lending completion signal (EXS signal) and pachinko machine operation signal (P
RDY signal) is exchanged via the I / O port 372f.

When the power of the pachinko gaming machine 1 is turned on,
The payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. Further, the card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connected state / unconnected state based on the input state of the VL signal. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the card unit controlling microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time has elapsed from this point in time, the card unit control microcomputer outputs a BRQ signal to the payout control board 37. Then, the payout control CPU 3 of the payout control board 37
71 raises the EXS signal to the card unit 50, and when it detects the fall of the BRQ signal from the card unit 50, it drives the payout motor 289 to pay out a predetermined number of lending balls to the player. At this time, the distribution solenoid 310 is in a driven state. That is, the ball distribution member 311 is directed to the ball lending side. Then, when the payout is completed, the payout control CPU 371 causes the EXS signal for the card unit 50 to fall. After that, if the BRDY signal from the card unit 50 is not in the ON state, prize ball payout control is executed.

As described above, all the signals from the card unit 50 are input to the payout control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input to the main board 31 from 0, and there is no room for the signal to be illegally input to the basic circuit 53 of the main board 31 from the card unit 50 side.

In this embodiment, the case where the card unit 50 is provided is taken as an example, but the present invention can also be applied to a case where a game ball corresponding to the amount of coin is lent out in response to coin insertion. Further, in the present embodiment, the case of lending a game ball is taken as an example, but the present invention can be applied even if a score is added.

In this embodiment, at least the main substrate 3
1 and the RAM in the payout control board 37 are backed up by a backup power supply. That is, even if the power supply to the gaming machine is stopped, the contents of the RAM are saved for a predetermined period. When each CPU detects a drop in the power supply voltage, it performs a predetermined process and then waits for the power supply to be restored. When the power is turned on, each CPU has a RAM
If the data is saved in, the state before power-off is restored based on the saved data.

Further, as described above, the payout control board 3
7, the main board 31 for sending commands to the display control board 80, the lamp control board 35 and the voice control board 70.
An INT signal is output from the output port (output port 0) 570 of the above to each electric component control board. In this case, for example,
The output port 570 has an 8-bit configuration. Bit 0 is an INT signal to the payout control board 37, bit 1 is an INT signal to the display control board 80, and bit 2 is a lamp control board 3.
5 to the voice control board 70.
Used for output of NT signal.

FIG. 11 is a block diagram showing an example of the configuration around the CPU 56. As shown in FIG. 11, the voltage drop signal from the first power supply monitoring circuit (first power supply monitoring means) causes the non-maskable interrupt terminal (XNMI terminal) of the CPU 56.
It is connected to the. The first power supply monitoring circuit is a circuit that detects a power supply voltage drop by monitoring the voltage of any one of various DC power supplies used by the gaming machine. In this embodiment, the power supply voltage of VSL is monitored, and when the voltage value is below a predetermined value, a low level voltage drop signal is generated. VSL
Is the maximum DC voltage used in the gaming machine, which is +30 V in this example. Therefore, the CPU 56
Can confirm the occurrence of power failure by interrupt processing. In this embodiment, the first power supply monitoring circuit is mounted on the power supply board described later.

Although the system reset circuit 65 is also shown in FIG. 11, in this embodiment, the system reset circuit 65 also serves as a second power supply monitoring circuit (second power supply monitoring means). That is, the reset IC 651 is
When the power is turned on, the output is set to the low level for a predetermined time determined by the capacity of the external capacitor, and when the predetermined time elapses, the output is set to the high level. That is, the reset signal is raised to the high level to bring the CPU 56 into the operable state. The reset IC 651 monitors the power supply voltage of VSL, which is a power supply voltage equal to the power supply voltage monitored by the first power supply monitoring circuit, and has a predetermined voltage value (the first power supply monitoring circuit outputs a voltage drop signal). When the voltage becomes lower than the power supply voltage value), a low level voltage drop signal is generated. Therefore, the CPU 56 is system reset after performing a predetermined power supply stoppage process in response to the voltage drop signal from the first power supply monitoring circuit. In this embodiment, the reset signal and the voltage drop signal from the second power supply monitoring circuit are the same signal.

As shown in FIG. 11, the reset IC 651 is used.
The reset signal from is input to the NAND circuit 947 and also to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. The counter IC 941 counts the clock signal from the oscillator 943 when the input to the clear terminal becomes low level.
Then, the Q5 output of the counter IC 941 is the NOT circuit 9
It is input to the NAND circuit 947 via 45 and 946. The Q6 output of the counter IC 941 is input to the clock terminal of the flip-flop (FF) 942.
The D input of the flip-flop 942 is fixed to the high level, and the Q output is input to the logical sum circuit (OR circuit) 949. The NAND circuit 9 is connected to the other input of the OR circuit 949.
The output of 47 is introduced via the NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. With such a configuration, when the power is turned on, the reset terminal of the CPU 56 is supplied with the reset signal (low level signal) twice.
Reliably starts operation.

Then, for example, the detection voltage of the first power supply monitoring circuit (the voltage at which the voltage drop signal is output) is +
22V, and the detection voltage of the second power supply monitoring circuit is + 9V. In such a configuration, since the first power supply monitoring circuit and the second power supply monitoring circuit monitor the voltage of the same power supply VSL, the timing at which the first voltage monitoring circuit outputs the voltage drop signal It is possible to reliably set the difference between the timings at which the second voltage monitoring circuit outputs the voltage drop signal to the desired predetermined period. The desired predetermined period is a period from the start of the power supply stop process to the reliable completion of the power supply stop process in response to the voltage drop signal from the first power supply monitoring circuit.

In this example, the first detection condition for the first power supply monitoring means to output the detection signal is that the + 30V power supply voltage has dropped to + 22V, and the second power supply monitoring means outputs the detection signal. The second detection condition for output is that the + 30V power supply voltage has dropped to + 9V.
However, the voltage value used here is an example,
Other values may be used.

However, although the monitoring range is narrowed, as the monitoring voltage of the first voltage monitoring circuit and the second voltage monitoring circuit, +
It is also possible to use a 5V power supply voltage. Also in that case, the detection voltage of the first voltage monitoring circuit is set higher than the detection voltage of the second voltage monitoring circuit.

At least part of the RAM is backed up by the backup power supply supplied from the power supply board while the power is not supplied from the + 5V power supply, which is the drive power supply for the CPU 56, etc. Is saved. When the + 5V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to the normal operating state. At that time, since necessary data is stored in the backup RAM, it is possible to return to the game state at the time of the power failure at the time of recovery from the power failure or the like.

In FIG. 11, when the power is turned on, the CPU 5
The configuration in which the reset signal (low level signal) is applied twice to the reset terminal of 6 has been shown, but when using a CPU that is surely released from reset even if the reset signal rises only once, , 941-9
The circuit element shown at 49 is unnecessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

CPU 56 used in this embodiment
Also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). PIO is PB0-PB
It has 4 bits of 3 and a 1-byte port of PA0 to PA7. The ports PB0 to PB3 and PA0 to PA7 can be set to either input / output. However, the built-in PIO is not used in this embodiment. In that case, for example, all the ports are set to the input mode and all the ports are connected to the ground level. When the power is turned on, P
The IO is automatically set to the input mode.

FIG. 12 is a block diagram showing an example of the configuration of the power supply board 910 of the gaming machine. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the display control board 80, the voice control board 70, the lamp control board 35, and the payout control board 37, and each electric part control board in the gaming machine and Generates the voltage used by the mechanical components. In this example, AC24V, VSL (DC + 30V), DC + 21
Generates V, DC + 12V and DC + 5V. Also,
The backup power supply capacitor 916 is DC + 5
It is charged from V, that is, the line of the power source that drives the IC or the like on each substrate.

The transformer 911 converts the AC voltage from the AC power supply into 24V. 24V AC voltage is applied to connector 9
It is output to 15. In addition, the rectifier circuit 912 is an AC 24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
The C converter 913 has + 22V, + 12V and +5
V is generated and output to the connector 915. Connector 91
5 is connected to a relay board, for example, and the relay board supplies electric power of a necessary voltage to each electric component control board and mechanical components. A power switch 918 for stopping and starting power supply to the game machine is installed on the input side of the transformer 911.

+ 5V from the DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is an electric power so that the memory state can be retained with respect to the backup RAM of the electric component control board (RAM that is backed up by the power source, that is, memory means that can be in the memory content retaining state) when the power supply to the gaming machine is cut off Will be the backup power supply. Also,
A diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line.

A battery which can be charged from a + 5V power source may be used as the backup power source. When a battery is used, a rechargeable battery is used which loses its capacity when the power is not supplied from the + 5V power source for a predetermined time.

The power supply board 910 has the above-mentioned first
The power supply monitoring IC 902 that constitutes the power supply monitoring circuit of is mounted. The power supply monitoring IC 902 detects the occurrence of power failure by introducing the VSL power supply voltage and monitoring the VSL power supply voltage. Specifically, when the VSL power supply voltage becomes equal to or lower than a predetermined value (+ 22V in this example), it is determined that the power supply is cut off, and a voltage drop signal is output. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is the voltage immediately after conversion from AC to DC, is used. The voltage drop signal from the power supply monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

The predetermined value for the power supply monitoring IC 902 to detect the power failure is lower than the normal voltage, but is a voltage at which the CPU on each electric component control board can operate for a while. Further, the power supply monitoring IC 902 is configured to monitor a voltage higher than a voltage (+ 5V in this example) for driving a circuit element such as a CPU and immediately after the AC is converted to the DC. Therefore, the monitoring range can be expanded with respect to the voltage required by the CPU. Therefore,
More precise monitoring can be performed. Furthermore, when VSL (+ 30V) is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V, so it can be expected to prevent erroneous switch-on detection at the momentary power failure. That is, if the voltage of the +30 V power supply is monitored,
It is possible to detect the drop of + 12V, which is created after 0V is created, before it starts to drop. Therefore, if the voltage of the + 12V power supply drops, the switch output will be in the ON state, but if the + 30V power supply voltage that drops earlier than + 12V is monitored and power failure is recognized, the power supply will be turned on before the switch output turns on. It is possible to enter a state of waiting for restoration and enter a state in which no switch output is detected.

Since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, the first power supply monitoring circuit supplies the voltage drop signal to the plurality of electric component control boards. You can No matter how many electric component control boards require the voltage drop signal, only one first power supply monitoring means is required. Therefore, each electric component control means in each electric component control board can perform recovery control described later. Even if you go, the cost of the gaming machine does not rise so much.

In the configuration shown in FIG. 12, the detection output (voltage drop signal) of the power source monitoring IC 902 is passed through the buffer circuits 918 and 919 to the respective electric component control boards (for example, the main board 31 and the payout control circuit). Substrate 37), for example, one detection output is transmitted to the relay substrate,
The same signal may be distributed from the relay board to each electric component control board. In addition, a buffer circuit may be provided according to the number of substrates that require the voltage drop signal.

Next, the operation of the gaming machine will be described. Figure 1
3 is a flowchart showing a main process executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, the CPU 56 in the main process
First, necessary initial setting is performed (step S1).

Then, it is confirmed whether or not the data protection processing of the backup RAM area (for example, power failure occurrence NMI processing such as addition of parity data) has been performed at the time of power off (step S2). In this embodiment, a process for protecting the data in the backup RAM area is performed when an unexpected power failure occurs. When such a protection process is performed, backup is made. Upon confirming that there is no backup, the CPU 56 executes initialization processing (steps S2 and S3). In this embodiment, whether or not there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area when the power is turned off.
For example, if "55H" is set in the backup flag area, it means that there is backup (on state),
If a value other than "55H" is set, it means that there is no backup (off state). "55H" set in the backup flag area is the data set when the data protection processing of the backup RAM area is completed in the power failure occurrence NMI processing.
It is a parity code based on the area data.

If backup data exists in the backup RAM area, the CPU 56 executes the backup RA.
A data check (eg, parity check) of the M area is performed (step S4). When the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, so the check result is normal. If the check result is not normal, it is not possible to return the internal state to the state when the power was cut off, so the initialization process that is executed when the power is turned on, not when the power is restored, is executed (steps S5 and S3).

If the check result is normal, the CPU 56
Performs a game state recovery process for returning the internal state to the state at the time of power off (step S6). As shown in FIG.
When the value of the backup flag is set to "55H" and the check result is normal, the gaming state recovery process of step S6 is executed. Then, the save value of the PC (program counter) saved in the backup RAM area is set in the PC and the address is restored (step S7).

Execution of normal initialization processing (step S3)
When is completed, the main processing shifts to a loop processing in which the monitoring of the timer interrupt flag (step S9) is confirmed. In the loop, the display random number updating process (step S8) is also executed.

In this embodiment, step S2
After the presence or absence of backup data is confirmed in step S4, if backup data exists, the backup area is checked in step S4, but conversely, it is confirmed that the backup area check result is normal. ,
The presence / absence of backup data may be confirmed. Further, whether or not to execute the power failure recovery process may be determined by confirming whether or not there is backup data or checking the backup area.

Further, for example, the RAM data saved at the time of the parity check (step S4) when determining whether to execute the power failure recovery process, that is, when determining whether to restore the game state. By the special process flag etc. in the and the start winning award memory number data, the gaming machine is in the game standby state (not changing the symbol, not playing the jackpot,
If it is confirmed that the probability is not changing and the starting winning award memory is not stored), the initialization process may be executed without performing the game state recovery process.

FIG. 15 is a flow chart showing the initial setting process of step S1. In the initialization process, C
The PU 56 first sets the interrupt prohibition (step S1).
a). When the interrupt is set to be prohibited, the CPU 56 sets the interrupt mode to the interrupt mode 2 (step S1b) and sets the stack pointer designated address in the stack pointer (step S1c). Then, the CPU 56 initializes the built-in device register (step S1d). In addition, CTC (counter / timer) and PIO (parallel input / output port) that are built-in devices (built-in peripheral circuits)
After initialization (step S1e), the RAM is set to the accessible state (step S1f).

CPU 5 used in this embodiment
6 has the following three types of maskable interrupt (INT) modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

Interrupt mode 0: The built-in device that issued the interrupt request has the RST instruction (1 byte) or the CALL instruction (3
Byte) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction of the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, CPU 56 automatically sets interrupt mode 0
become. Therefore, when it is desired to set the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

Interrupt mode 1: When an interrupt is accepted,
It is a mode to always fly to the address 0038 (h).

Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the built-in device is the interrupt address. Is a mode indicating. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, the interrupt processing can be installed at an arbitrary (although discrete) even address. Each built-in device has a function of transmitting an interrupt vector when making an interrupt request.

Therefore, when the interrupt mode 2 is set, the interrupt request from each built-in device can be easily processed, and the interrupt process can be installed at an arbitrary position in the program. It will be possible. Further, unlike the interrupt mode 1, it is easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S1b of the initial setting process.

FIG. 16 shows a normal initialization process (step S
It is a flow chart which shows processing of 3). As shown in FIG. 16, in the initialization process, a RAM clear process is performed (step S3a). Then, based on the address value of the work area initialization table, a predetermined work area (for example, a random number counter for normal symbol judgment, a normal symbol judgment buffer, a special symbol left middle right symbol buffer, a payout command storage pointer, etc.) An initial value setting process (step S3b) for setting a value is performed. Then, the register of the CTC provided in the CPU 56 is set so that the timer interrupt is periodically applied every 2 ms (step S3).
c). That is, a value corresponding to 2 ms as an initial value is set in a predetermined register (time constant register). Since the interrupt is prohibited (see FIG. 15) in the initial setting process (step S1), the interrupt is permitted before the initialization process is completed (step S3d).

Therefore, in this embodiment, the CPU 56
The built-in CTC of is set to repeatedly generate timer interrupts. In this embodiment, the repetition cycle is 2 ms.
Is set to. Then, as shown in FIG. 17, when the timer interrupt occurs, the CPU 56 sets the timer interrupt flag (step S12).

When the CPU 56 detects in step S9 that the timer interrupt flag has been set, it resets the timer interrupt flag (step S1).
0), game control processing is executed (step S11). By the above control, in this embodiment, the game control process is activated every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the game control process is executed in the main process,
The game control process may be executed by the timer interrupt process.

As described above, in this embodiment, the interrupt mode 2 is set in the CPU 56 having the built-in CTC and PIO in the initial setting process. Therefore, it is possible to easily realize the periodic timer interrupt processing using the built-in CTC. Also, the timer interrupt process can be installed at any position on the program. Further, the switch detection process using the built-in PIO can be easily realized by the interrupt process. As a result, the program configuration can be simplified, and the effects of reducing the number of program development steps can be obtained.

In addition, in this embodiment, it is determined whether or not the power-off state is restored, depending on the presence or absence of backup data. Therefore, when the power is turned on when the power is restored after a power failure, it is possible to determine whether to restore the power-off state according to the contents of the backup data storage area.

Further, since it is judged whether or not the power-off state will be restored depending on the state of the backup data, when the power is turned on at the time of power restoration after a power failure, the contents of the backup data storage area It is possible to determine whether or not to restore the power-off state according to the state.

FIG. 18 is a flow chart showing the game control processing of step S11. In the game control process,
The CPU 56 firstly, via the switch circuit 58, the gate sensor 12, the starting opening sensor 17, the count sensor 23.
And enter the state of the winning opening switch 19a, 24a,
It is determined whether or not there is a winning for each winning opening or winning device (switch processing: step S21).

Next, various abnormality diagnosis processing is performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error processing: step S22).

Next, a process for updating each counter indicating each judgment random number such as a big hit judgment random number used for game control is performed (step S23). The CPU 56 further
A process of updating a display random number such as a random number that determines the type of the stop symbol is performed (step S24).

Further, the CPU 56 performs special symbol process processing (step S25). In the special symbol process control, the corresponding process is selected and executed according to the special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. Then, the value of the special symbol process flag is updated during each process according to the game state. Also, a normal symbol process process is performed (step S26). In the normal symbol process process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the variable display 10 by the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the game state.

Further, the CPU 56 carries out a process of setting the control command to be sent to the payout control board 37 or the like in a predetermined area of the RAM 55 and sending the control command (command control process: step S27).

Next, the CPU 56 carries out a data output process for outputting data such as big hit information, starting information and probability variation information supplied to the hall management computer (step S29).

Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S30). The solenoid circuit 59 drives the solenoids 16 and 21 in response to the drive command to open the variable winning ball device 15 or the opening / closing plate 20 in an open state or a closed state.

Further, the CPU 56 sets the number of prize balls based on the detection output of the switches 17, 23, 19a and 24a for detecting the winning of each winning opening (step S31). Specifically, the payout control command is output to the payout control board 37 in response to the winning detection. Discharge control board 37
The payout control CPU 371 mounted in the drive the ball payout device 97 in response to the payout control command.

As described above, the main process includes the process of determining whether or not to shift to the game control process, and the CPU
Since the flag for setting whether or not to shift to the game control process in the timer interrupt process based on the timer interrupt that the internal timer of 56 regularly generates, all of the game control process is executed surely. To be done. In other words, until all of the game control processing is executed, it is not determined whether or not to move to the next game control processing, so it is guaranteed that all the processing in the game control processing is completed. ing.

Here, the CPU 56 of the main board 31 is used.
The game control process executed by is executed according to the flag set in the timer interrupt process based on the timer interrupt that the internal timer of the CPU 56 regularly generates, but the signal is periodically (for example, every 2 ms). A hardware circuit for generating is provided, a signal from the circuit is introduced to an external interrupt terminal of the CPU 56, and a flag for determining whether or not to shift to the game control processing by the interrupt signal may be set. Good.

Even in such a configuration, the flag is not determined until all the game control processing is executed, so that it is guaranteed that all the processing during the game control processing is completed. It

FIG. 19 shows the payout control board 3 from the main board 31.
It is explanatory drawing which shows an example of the command form of the payout control command transmitted to FIG. In this embodiment, the payout control command has a 2-byte structure, and the first byte is MODE.
(Command classification), and the second byte represents EXT (command type). The command form shown in FIG. 19 is an example, and other command forms may be used.
The first bit (bit 7) of MODE data is always "1"
The first bit (bit 7) of the EXT data is always "0".

FIG. 20 shows the relationship between an 8-bit control signal (in this case, a payout control signal) and an INT signal (in this case, a payout control signal INT) which form a control command for each electric component control means. It is a timing diagram. Figure 2
As shown in 0, after the MODE or EXT data is output to the output port (port 1 in this case), A
When the period indicated by is elapsed, the CPU 56 turns on the INT signal, which is a signal indicating data output. When the period indicated by B elapses, the INT signal is turned off. Furthermore, if there is data to be sent next, that is, after sending the MODE data, C
The second byte of data is sent to the output port after a period indicated by. Regarding the data of the second byte, A,
The period of B is the same as the case of the first byte.

The period A is a period during which the CPU 56 prepares to send a command, that is, a period required for setting a send command in the buffer, and also stabilizes data on the control signal line (in this case, the payout control signal line). It is the period for conversion. The period B is a period for stabilizing the INT signal. Then, the period C is a period in which the electric component control means (in this case, the payout control means) is set so that the data can be surely taken in. During the period C, the data on the signal line does not change. That is, the data output is maintained until the period C has elapsed.

As will be described later, in this embodiment, the payout control command to the payout control board 37 and the display control board 8 are given.
The display control command for 0, the lamp control command for the lamp control board 35, and the voice control command for the voice control board 70 are sent using the same routine (common module). Therefore, during the period of C, that is, the period from when the INT signal for the first byte is turned off until the transmission of the data for the second byte is started, the command receiving process takes the longest time, which is the reception processing time in the electric component control means. Is set to be longer than.

In each electric component control means, the INT signal is in the on state (high level) to the off state (low level).
When it is detected, the process of fetching 1-byte data is started by, for example, an interrupt process.

Since the period C is longer than the reception processing time in the electric component control means which takes the longest time for the command reception processing, the game control means controls the command transmission processing for each electric component control means by the common module. Also, any of the electric component control means can surely receive the control command from the game control means.

In this embodiment, the CPU 56 executes (1
It operates with a system clock of 1.776 / 2) MHz. Then, specifically, 138 states (1 state = [2 / 11.776] μs) are spent during the period A, 82 states are spent during the period B, and 251 states are spent during the period C. Therefore, the period of C is longer than the period of A. That is, the CPU 56 becomes ready to send the next data after a lapse of a predetermined period after executing the INT signal output process, but during the predetermined period (C period), the CPU 56 sends the data before the INT signal output process. Is longer than the period from the start of outputting the INT signal (period A). As described above, the period A is a stabilization period in the command signal line, and the period C is a period for ensuring the time required for the receiving side to fetch data. Therefore, by making the period A shorter than the period C, it is possible to obtain the effect that the electric component control means on the receiving side can surely receive the command, and it is necessary to complete the transmission of one command. It also has the effect of shortening the period.

FIG. 21 is an explanatory diagram showing an example of the contents of the payout control command. In the example shown in FIG. 21, M
Command F with ODE = FF (H) and EXT = 00 (H)
F00 (H) is a payout control command that specifies the payable state. MODE = FF (H), EXT = 01
The command FF01 (H) of (H) is a payout control command that specifies the payout stop state. Also, MODE = F0
The command F0XX (H) of (H) is a payout control command for designating the number of prize balls. “XX”, which is EXT, indicates the number of payouts.

When the payout control means receives the payout control command of FF01 (H) from the game control means of the main board 31, the payout ball payout and the ball lending are stopped, and FF00.
When the payout control command (H) is received, prize balls can be paid out and balls can be lent. Further, when the payout control command for designating the number of prize balls is received, the prize ball payout control according to the number designated by the received command is performed.

The payout control command is sent only once so that the payout control means can recognize it. In this example, “recognizable” means that the INT signal is turned on, and “recognitionally sent once” means that in this example, the payout control signal is sent to each of the first byte and the second byte. Accordingly, the INT signal is turned on only once.

Further, since one command (command information) has a 2-byte structure, the influence of noise can be reduced. That is, when one command is composed of 1-byte command data, even if data is corrupted due to noise, it may be received as it is and erroneously controlled. If so, the control based on the command is started only when both are correctly received, so that the possibility of malfunction can be reduced as compared with the case of the 1-byte configuration.

FIG. 22 is an explanatory diagram showing an example of the contents of the display control command. Display control commands are MODE and E
It is a 2-byte structure of XT. In the example shown in FIG. 22,
Commands 8000 (H) -8022 (H), 8100
(H) to 8122 (H) are display control commands that specify the variation pattern of the special symbol in the variable display section 9 that variably displays the special symbol. The command for designating the variation pattern also serves as a variation start instruction. Command 88
XX (X = an arbitrary value of 4 bits) is a display control command relating to a variation pattern of a normal symbol which is variably displayed on the variable display 10. The command 89XX is a display control command for designating a stop symbol of a normal symbol. Command 8
AXX (X = an arbitrary value of 4 bits) is a display control command for instructing to stop the variable display of the normal symbols.

Commands 91XX, 92XX and 93X
X is a display control command for designating the left middle right stop symbol of the special symbol. The command A0XX is a display control command for instructing to stop the variable display of the special symbol.
The command BXXX is a display control command sent from the start of the big hit game to the end of the big hit game. Then, the commands C000 and EXXX are display control commands concerning the display state of the variable display portion 9 which is not related to the variation of the special symbol and the big hit game. Display control board 80
When receiving the above-mentioned display control command from the game control means of the main board 31, the display control means changes the display states of the variable display section 9 and the variable display 10 according to the contents shown in FIG.

FIG. 23 is an explanatory diagram showing an example of the contents of the lamp control command. Lamp control command is also MODE
And EXT have a 2-byte structure. In the example shown in FIG. 23, the commands 8000 (H) -8022 (H), 810
0 (H) to 8122 (H) are lamp control commands that specify the lamp / LED display control pattern corresponding to the variation pattern of the special symbol in the variable display section 9. In addition, the command A0XX (X = arbitrary value of 4 bits) is
It is a lamp control command for instructing the lamp / LED display control pattern when the variable display of the special symbol is stopped. The command BXXX is a lamp control command for instructing the lamp / LED display control pattern from the start of the big hit game to the end of the big hit game. And the command C000 is
This is a lamp control command for instructing a lamp / LED display control pattern during a customer waiting demonstration.

The commands 8XXX, AXXX, BX
XX and CXXX are lamp control commands sent from the game control means according to the game progress status. When the lamp control means receives the above-mentioned lamp control command from the game control means of the main board 31, it changes the display state of the lamp / LED according to the contents shown in FIG.

The command E0XX is the start memory display 18
Is a lamp control command indicating the number of lights. For example,
The lamp control means uses the "X
The number of indicators designated by "X" is turned on. Further, the command E1XX is a lamp control command indicating the number of the gate passage storage indicators 41 lit. For example, the lamp control means turns on the number of displays designated by "XX" in the gate passage storage display 41.
That is, those commands are commands for instructing the control of the light-emitting body provided for notifying the information of the number of holdings. In addition, the command regarding the number of lighting of the starting memory display 18 and the gate passing memory display 41 may be configured to indicate an increase or decrease of the number of lighting.

The commands E200 and E201 are lamp control commands relating to the display state of the prize ball lamp 51, and the commands E300 and E301 are lamp control commands relating to the display state of the out-of-ball lamp 52. The lamp control means, from the game control means of the main board 31 "E2
When the lamp control command of "01" is received, the prize ball lamp 5
The display state of 1 is set as a predetermined display state when there is a prize ball remaining, and when the lamp control command of "E200" is received, the display state of the prize ball lamp 51 is a predetermined display when there is no prize ball remaining. State. Further, when the lamp control command of "E300" is received from the game control means of the main board 31, the display state of the ball out lamp 52 is changed to the display state with a ball, and when the lamp control command of "E301" is received, the ball out lamp 52 is received. The display state of is set to the display state in which the ball is out. That is, the command E20
0 and E201 are commands indicating that a light emitting body provided to notify a player or the like that there is a non-prize game ball, and commands E300 and E201.
Reference numeral 301 is a command indicating that the light emitting body provided to notify the player or the game shop staff that the supply ball has run out is controlled.

The command E400 is when the power of the gaming machine is turned on, or from a specific game state (high probability state or time saving state, high probability state in this example) to a normal state (low probability state or non-time saving state, low probability in this example). This is a lamp control command for instructing the lamp / LED display control pattern when the state is changed to (state). The command E401 is a lamp / LED display when the normal state (low probability state or non-time saving state, low probability state in this example) shifts to a specific game state (high probability state or time saving state, high probability state in this example) It is a lamp control command for designating a control pattern. The command E402 is
It is a lamp control command for instructing the lamp / LED display control pattern when the error occurred during the big hit game is released. The command E403 is a lamp control command for instructing the lamp / LED display control pattern when the error of the count switch 23 occurs.
That is, these commands are commands for instructing to notify the gaming state by the light emitter. In this embodiment, the lamp control means receives the command for informing the gaming state, the decoration lamp 25,
Game effect LED 28a and game effect lamps 28b, 2
A part or all of 8c is used to perform lighting / extinguishing control for notifying a gaming state. Decorative lamp 2
5, game effect LED 28a and game effect lamp 28
Each of b and 28c may be composed of a group of a plurality of luminous bodies, in which case, the gaming state is informed by using a part of the decoration lamp 25, the game effect LED 28a, and the game effect lamps 28b and 28c. To do that means
For example, it also means that a part of the plurality of light emitting elements that form the decorative lamp 25 may be used.

FIG. 24 is an explanatory diagram showing an example of the contents of the voice control command. Voice control commands are also MODE and E
It is a 2-byte structure of XT. In the example shown in FIG. 24,
The command 8XXX (X = any value of 4 bits) is a voice control command for designating a sound generation pattern in the variable period of the special symbol. The command BXXX (any value of X = 4 bits) is a voice control command that specifies a sound generation pattern from the start of the big hit game to the end of the big hit game. Other commands are voice control commands that are not related to special symbol variations and jackpot games. When the voice control means of the voice control board 70 receives the above-mentioned voice control command from the game control means of the main board 31, FIG.
The voice output state is changed according to the contents shown in 4.

FIG. 25 is a flow chart showing an example of a special symbol process processing program executed by the CPU 56. The special symbol process process shown in FIG. 25 is shown in FIG.
This is a specific process of step S25 in the flowchart of FIG. When performing the special symbol process process, the CPU 56 performs any one of steps S300 to S309 shown in FIG. 25 according to the internal state after performing the fluctuation reduction timer subtraction process (step S310).

In the fluctuation shortening timer subtraction processing of step S310, whether or not the condition for shortening the fluctuation time of the special symbol is satisfied (for example, a predetermined time from the time when the start winning is detected until the processing based on the start winning is executed). The process of subtracting the fluctuation reduction timer for confirming whether or not has elapsed) is performed. Then, steps S300 to S309
The following processes are executed in each process.

Special symbol fluctuation waiting processing (step S30
0): The start winning opening 14 (in this embodiment, the winning opening of the variable winning ball device 15) is hit and the starting opening sensor 17 is turned on. When the starting opening sensor 17 is turned on, the number of memory of winning a prize for starting is increased by +
At the same time, the random numbers for determining the big hit are extracted.

Special symbol determination processing (step S301):
When the variable display of the special symbols can be started, the number of memory for winning the winning start is confirmed. If the number of memory for winning a prize is not 0,
Depending on the value of the extracted big hit determination random number, it is decided whether to make a big hit or not.

Stop symbol setting process (step S302):
The stop symbol of the left and right middle symbols is determined.

Reach operation setting processing (step S30
3): Whether or not the reach operation is performed is determined according to the value of the reach determination random number, and the variation period at the time of reach is determined according to the value of the reach type determination random number.

All symbol variation start processing (step S30
4): Control is performed so that all the symbols on the variable display unit 9 start changing. At this time, with respect to the display control board 80,
A control command for instructing the final stop symbol and the variation mode in the left and right is transmitted. When the processing is completed, the internal state (process flag) is updated so as to shift to step S305.

All symbol stop waiting processing (step S30
5): When a predetermined time has elapsed, control is performed so that all the symbols displayed on the variable display unit 9 are stopped. And
When the stop symbol is a combination of big hit symbols, the internal state (process flag) is updated so as to shift to step S306. If not, the internal state is updated to shift to step S300.

Special winning opening opening processing (step S30
6): Start the control for opening the special winning opening. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening. In addition, the big hit flag (the flag which shows that it is during big hit) is set. When the processing is completed, the internal state (process flag) is updated so as to shift to step S307.

Processing during opening of the special winning opening (step S30
7): Control for sending the display control command data of the special winning opening round display to the display control board 80, processing for confirming the establishment of the closing condition of the special winning opening, and the like. When the final closing condition for the special winning opening is satisfied, the internal state is updated so as to shift to step S308.

Specific area effective time processing (step S30
8): The presence or absence of passage of the V count switch 22 is monitored, and a process of confirming that the jackpot gaming state continuation condition is satisfied is performed. If the conditions for continuation of the jackpot gaming state are met and there are still remaining rounds, the internal state is set to step S30.
Update to move to 6. Further, when the jackpot gaming state continuation condition is not satisfied within a predetermined effective time, or when all the rounds are finished, the internal state is updated so as to shift to step S309.

Big hit end processing (step S309): Display for notifying the player that the big hit game state has ended. When the display ends, the internal state is updated so as to shift to step S300.

As described above, when the ball hits the starting winning opening 14, the CPU 56 determines whether to make a big hit or a big hit, a stop symbol, a reach mode, or a positive change in the special symbol process processing. However, the control command such as the display control command according to the determination is sent to the electric component control means such as the display control means. For example, the display control means controls the display of the variable display section 9 in response to a display control command from the main board 31. In addition, control commands are sent to the display control board 80, the lamp control board 35, and the voice control board 70 according to the progress of the game. The command transmission method is as described above.

FIG. 26 is a flow chart showing a part related to prize ball control of the switch process (step S21) in the game control process shown in FIG. In the switch process, the CPU 56 sets the out-of-ball state flag when the out-of-ball switch 187 detects the out-of-ball state (steps S121 and S122). Further, when the out-of-ball switch 187 detects that the ball is not out, the out-of-ball state flag is reset (steps S121 and S12).
3).

Next, when the lower tank full tank is detected by the full tank switch 48, the full tank flag is set (steps S124 and S125). When the full tank switch 48 detects that the lower plate is not full, the full tank flag is reset (steps S124 and S126).

Further, when it is detected that the count switch 23 is turned on, the 15 counter is incremented by 1 (steps S131 and S132), and the winning opening switches 19a and 24a are obtained.
When any one of the above is detected to be turned on, the 10 counter is incremented by 1 (steps S133 and S134), and when the start opening switch 17 is detected to be turned on, the six counter is incremented by 1 (steps S135 and S136).

In this embodiment, 15 prize balls are paid out for the prizes that have passed through the big winning opening, 6 prize balls are paid out for the prizes that have passed through the start winning opening 14, and the other winning openings 19, It is assumed that 10 prize balls are paid out for winning through 24 and the prize ball device. The 15-piece counter is a counter for counting the number of winnings in the big winning opening, the 10-piece counter is a counter for counting the number of winnings in the normal winning opening, and the 6-piece counter is a winning for the starting winning opening. It is a counter for counting the number.

FIG. 27 is a flow chart showing an example of the winning ball signal processing (step S31) in the game control processing shown in FIG. In this example, in the winning ball signal processing, the CPU 56 first confirms whether or not the payout is stopped (step S201). Withdrawal stop status is
This is the state after the command for designating the dispensing stop state is sent to the dispensing control board 37. If the payout is not stopped,
It is confirmed whether or not the out-of-ball state flag or the full tank flag is turned on (step S202).

When any of them changes to the ON state,
The command transmission table relating to the payout stop state designation is set (step S203). The command transmission table will be described in detail later. Note that step S202
In the above, when one of the flags is already in the on state and the other flag is in the on state, the command transmission table is not set (step S203).

If it is in the payout stop state, it is confirmed whether or not both the out-of-ball state flag and the full tank flag are turned off (step S204). When both are in the off state, the command transmission table relating to the payout stop cancellation designation is set (step S205).

Next, the CPU 56 carries out control to set a payout control command relating to the number of prize balls according to winning in the command transmission table. First, the value of the 15 counter is checked (step S211). As mentioned above, 1
The five-piece counter is counted up when the game ball wins the special winning opening and the count switch 23 is turned on. 15
If the value of the individual counter is not 0, the command transmission table for the instruction of the number of 15 prize balls is set (step S212). Further, the value of the 15 counter is decremented by 1 (step S213).

If the value of the 15 counter is 0, the value of the 10 counter is checked (step S215). As described above, the 10-piece counter is counted up when the game ball wins the winning opening and the winning opening switches 19a and 24a are turned on. When the value of the 10-piece counter is not 0, the command transmission table regarding the instruction of the number of 10 prize balls is set (step S216). Further, the value of the 15 counter is decremented by 1 (step S217).

If the 10-counter value is 0, the 6-counter value is checked (step S221). As described above, the six counter is counted up when the game ball wins the starting winning opening and the starting opening switch 17 is turned on. If the value of the 6-counter is not 0, the command transmission table relating to the instruction of the number of 6 prize balls is set (step S222). In addition, the value of 6 counters
1 (step S223).

As described above, when the payout control command is to be output from the game control means to the payout control board 37, the command transmission table is set. FIG. 28
FIG. 9A is an explanatory diagram showing a configuration example of a command transmission table. One command transmission table is composed of 3 bytes, and INT data is set in the 1st byte. Further, the command data 1 of the second byte is set to the MODE data of the first byte of the payout control command. Then, in the command data 2 of the 3rd byte, the EXT data of the 2nd byte of the payout control command is set.

Although the EXT data itself may be set in the area of the command data 2, the command data 2
May be set with data for designating the address of the table in which the EXT data is stored. In this embodiment, bit 7 of command data 2
If the (work area reference bit) is 0, it indicates that the EXT data itself is set in the command data 2. Note that such EXT data is data in which bit 7 is 0. Further, if the work area reference bit is 1, it indicates that the other 7 bits are an offset for designating the address of the table in which the EXT data is stored.

In this embodiment, a plurality of command transmission tables are prepared, and the command transmission table to be used is designated by the pointer. Also, the plurality of command transmission tables are used as ring buffers. Therefore, CP
In the winning ball signal processing, U56 sets INT data, command data 1 and command data 2 in the command transmission table pointed to by the write pointer. Then, the value of the write pointer is updated. Since one command transmission table has a 3-byte structure, specifically, the write pointer value is incremented by +3.

In the process shown in FIG. 27, only the command transmission table setting process relating to one payout control command is performed for one process, but since a plurality of command transmission tables are provided, a plurality of command transmission tables are provided. The table setting process may be performed. For example, when a plurality of prizes are stored in the 15-piece counter, the 10-piece counter, and the 6-piece counter, a plurality of command transmission table setting processes may be performed by one-time winning ball signal processing.

Further, here, the payout control command will be described, but when the display control command, the lamp control command and the voice control command are sent, FIG.
INT data, command data 1 and command data 2 are set in the command transmission table as shown in FIG. Also at that time, the INT data, the command data 1 and the command data 2 are set in the command transmission table pointed to by the write pointer.

FIG. 28B is an explanatory diagram showing a structural example of INT data. Bit 0 in the INT data indicates whether or not the payout control command should be sent to the payout control board 37. If bit 0 is "1", it indicates that the payout control command should be sent. Therefore, the CPU 56
In the winning ball signal processing, "01" is added to the INT data.
(H) ”is set.

Bits 1, 2, 3 of INT data
Are bits indicating whether or not to send a display control command, a lamp control command, and a voice control command, respectively, and the CPU 56 performs special symbol process processing or the like at the timing to send these commands. INT data, command data 1 and command data 2 are set in the command transmission table pointed to by the pointer. When sending those commands, the corresponding bit of the INT data is set to "1", and the MODE data and EX are added to the command data 1 and the command data 2.
T data is set.

FIG. 29 is a flow chart showing a processing example of the command control processing (step S27) in the game control processing shown in FIG. The command control processing is processing including command output processing. In the command control process, the CPU 56 first saves the address (content of the read pointer) of the command transmission table to the stack or the like (step S231). Then, the INT data of the command transmission table pointed to by the read pointer is loaded into the argument 1 (step S232). The argument 1 is input information for the command transmission process described later. Further, the address indicating the command transmission table is incremented by 1 (step S233). Therefore, the address indicating the command transmission table matches the address of the command data 1.

Therefore, the CPU 56 sends the command data 1
Is read out and set to the argument 2 (step S234).
The argument 2 is also input information for the command transmission process described later. Then, the command transmission processing routine is called (step S235).

FIG. 30 is a flow chart showing the command transmission routine. In the command transmission routine,
The CPU 56 first sets the data set in the argument 1, that is, the INT data, in the work area determined as the comparison value (step S251). Then
The number of transmissions = 4 is set in the work area determined as the number of processes (step S252). Then, the port 1 (output port 571) for outputting the payout control signal
Is set to the IO address (step S2
53).

Next, the CPU 56 shifts the comparison value right by 1 bit (step S254). As a result of the shift processing, it is confirmed whether the carry bit has become 1 (step S255). The carry bit has become 1, which means that the rightmost bit in the INT data is "1".
It means that it was. In this embodiment, the shift process is performed four times. For example, when it is specified that the payout control command should be sent, the carry bit becomes 1 in the first shift process.

When the carry bit becomes 1, the data set in the argument 2, in this case, the command data 1 (that is, MODE data) is output to the address set as the IO address (step S2
56). Since the address of the port 1 (output port 571) is set as the IO address when the first shift processing is performed, the MODE data of the payout control command is eventually output to the port 1.

Next, the CPU 56 sets the IO address to 1
While adding (step S257), 1 is subtracted from the processing number (step S258). When the port 1 is shown before the addition, the address of the port 2 (output port 572) is set to the IO address by the addition process for the IO address. Port 2 (output port 572)
Is a port for outputting a display control command.
Then, the CPU 56 checks the value of the number of processes (step S259), and if the value is not 0, the step S2
Return to 54. The shift process is performed again in step S254.

In the second shift processing, the value of bit 1 in the INT data is pushed out, and the carry flag becomes "1" or "0" depending on the value of bit 1. Therefore,
A check is made to see if it is specified that a display control command should be sent. Similarly, by the third and fourth shift processing, it is checked whether or not the lamp control command and the voice control command should be sent. Thus, when each shift process is performed, the IO address is set to the IO address corresponding to the command (payout control command, display control command, lamp control command, voice control command) checked by the shift process. Has been done.
Therefore, when the carry flag becomes "1", the control command is sent to the corresponding output port (port 1 to port 4). That is, one common module
It is possible to perform control command transmission processing to each electric component control means.

Further, in this way, since it is determined which electric component control means the control command should be output only by the shift processing, it is determined which electric component control means the control command should be output to. Processing has been simplified.

Next, the CPU 56 reads the contents of the argument 1 in which the INT data before the start of the shift processing is stored (step S260), and reads the read data into the port 0.
Output to (output port 570) (step S26)
1). In the INT data, steps S251 to S259
Control command (payout control command,
The bit corresponding to the output bit of the INT signal corresponding to the display control command, the lamp control command, the voice control command is “1”. Therefore, port 1 to port 4
The INT signal corresponding to the control command (the payout control command, the display control command, the lamp control command, the voice control command) output to any of the above is turned on.

Next, the CPU 56 sets a predetermined value in the wait counter (step S262), and decrements by 1 until the value becomes 0 (steps S263, S26).
4). This process is a process for setting the period B shown in FIG. When the value of the wait counter becomes 0, clear data (00) is set (step S26).
5) output the data to port 0 (step S2)
66). Therefore, the INT signal is turned off. Then, a predetermined value is set in the wait counter (step S2
62), and decrement by 1 until the value becomes 0 (steps S268 and S269). This process is a process for setting the period C shown in FIG.

Therefore, the value set in the wait counter in step S267 is set so that the period C is a period sufficient for surely performing the command receiving process by all the electric component control means which are the control command receiving targets. Value. The value set in the wait counter is
The value is longer than the time required for the processes of steps S251 to S259.

As described above, the MODE data of the first byte of the control command is transmitted. Therefore, CPU5
In step S236 shown in FIG. 29, 6 adds 1 to the value indicating the command transmission table. Therefore, the area of the command data 2 in the third byte is designated. The CPU 56
The contents of the pointed command data 2 are loaded into the argument 2 (step S237). Also, it is confirmed whether or not the value of bit 7 (work area reference bit) of the command data 2 is "0" (step S239). If not 0, the head address of the command extension data address table is set to the pointer (step S239), and the value of bits 6 to 0 of the command data 2 is added to the pointer to calculate the address (step S240). Then, the data of the area indicated by the address is loaded into the argument 2 (step S241).

In the command extension data address table, EXT data which can be sent to the electric component control means is sequentially set. Therefore, by the above processing, if the value of the work area reference bit is “1”, the EXT data in the command extension data address table according to the content of the command data 2 is loaded into the argument 2 and the work area reference bit If the value is “0”, the content of the command data 2 is loaded as it is in the argument 2. Even when the EXT data is read from the command extension data address table, bit 7 of the data is "0".

Next, the CPU 56 calls the command transmission routine (step S242). Therefore, MOD
EXT data is transmitted at the same timing as in the case of transmitting E data. After that, the CPU 56 restores the address of the command transmission table (step S243) and updates the value of the read pointer pointing to the command transmission table (step S244). Since one command transmission table has a 3-byte structure, specifically, the value of the read pointer is incremented by +3.

As described above, the control command (payout control command, display control command, lamp control command, voice control command) having a 2-byte structure is transmitted to the corresponding electric component control means. In the electrical component control means INT
When the fall of the signal is detected, the control command fetch processing is started, but for any electric component control means, a new signal from the game control means is output to the signal line before the fetch processing is completed. There is no such thing. That is, a reliable command reception process is performed in each electric component control means. Each electric component control means is
The control command acquisition process may be started at the rising edge of the NT signal. Further, the polarity of the INT signal may be reversed from that shown in FIG.

Further, in this embodiment, a plurality of command transmission tables are used as the ring buffer, and the command transmission table shown in FIG.
In the command control process shown in FIG. 9, command output control is performed for the command transmission table pointed to by the read pointer, and a process of setting data in the command transmission table, for example, in the winning ball signal process shown in FIG. Command setting processing is performed for the command transmission table pointed to by the add pointer. Therefore, even if a plurality of command transmission requests are generated at the same time, the command output processing based on those requests can be executed without any problem.

Next, the command reception processing and the like in the electric component control means will be described. Here, the command receiving process and the like in the payout control means will be described.

FIG. 31 is a block diagram showing an example of the configuration around the payout control CPU 371. As shown in FIG. 31, the voltage drop signal from the first power supply monitoring circuit (first power supply monitoring means) causes the non-maskable interrupt terminal (XNMI terminal) of the payout control CPU 371 via the buffer circuit 960.
It is connected to the. The first power supply monitoring circuit is a circuit that detects a power supply voltage drop by monitoring the voltage of any one of various DC power supplies used by the gaming machine. In this embodiment, the power supply voltage of VSL is monitored, and when the voltage value is below a predetermined value, a low level voltage drop signal is generated. VSL
Is the maximum DC voltage used in the gaming machine, which is +30 V in this example. Therefore, the payout control CPU 371 can confirm the occurrence of power interruption by the interrupt process.

C for payout control used in this embodiment
The PU 371, like the CPU 56 of the main board 31, also has a PI
Built-in O and CTC. However, the built-in PIO is not used in this embodiment. In that case, for example, all the ports are set to the input mode and all the ports are connected to the ground level.

Further, similarly to the CPU 56 of the main board 31,
The payout control CPU 371 can also be set to any of the interrupt modes 0 to 2, and the CTC can operate in a timer mode or a counter mode as described below.
In this embodiment, channel 3 of the built-in CTC is used in timer mode and channel 2 is used in counter mode. Channel 3 is used as a timer interrupt generation source, and channel 2 is used for receiving the payout control command. Further, the payout control CPU 371 incorporates CTCs of a plurality of channels. The operation mode can be set for each channel.

Counter mode: CPU 371 for payout control
When the rising or falling of the clock signal is input to the CLK / TRG terminal of, the count value is decremented by one. If interrupt generation permission is set for that channel, an interrupt is generated when the count value reaches 0, and
Reload the initial value into the counter. Further, if the interrupt vector is set, the interrupt vector is sent out to the internal data bus when the count value becomes 0.

Timer mode: The count value is decremented by -1 based on the clock signal obtained by dividing the system clock (internal clock) by 1/16 or 1/256. If interrupt generation permission is set for that channel,
When the count value becomes 0, an interrupt is generated and the initial value is reloaded into the counter. Further, if the interrupt vector is set, the interrupt vector is sent out to the internal data bus when the count value becomes 0.

CLK / TRG of payout control CPU 371
The INT signal (payout control signal INT) from the main board 31 is connected to the two terminals. When a clock signal is input to the CLK / TRG2 terminal, the payout control CPU 371
Timer counter register CLK / TR built in
The value of G2 (CTC channel 2 counter) is down-counted. Then, when the register value becomes 0, an interrupt occurs. Therefore, the timer counter register CLK / T
If the initial value of RG2 is set to "1", an interrupt will occur in response to the input of the INT signal.

A system reset circuit 975 is also mounted on the payout control board 37, but in this embodiment,
The system reset circuit 975 also serves as a second power supply monitoring circuit (second power supply monitoring means). That is, the reset IC 976 sets the output to the low level for a predetermined time determined by the capacitance of the external capacitor when the power is turned on, and sets the output to the high level after the predetermined time elapses. In addition, the reset IC 976 monitors the power supply voltage of VSL, which is a power supply voltage equal to the power supply voltage monitored by the first power supply monitoring circuit mounted on the power supply board 910, so that the voltage value becomes a predetermined value (for example, + 9V) or less. Then, a low level voltage drop signal is generated. Therefore, when the power is off, the reset IC 976
The CPU 371 for payout control is system reset when the voltage drop signal from is low level. Note that, as shown in FIG. 31, the voltage drop signal is the same output signal as the reset signal.

Although the predetermined value for the reset IC 976 to detect the power failure is lower than the voltage at the normal time, the payout control C
The voltage is such that the PU 371 can operate for a while. Further, since the reset IC 976 is configured to monitor a voltage higher than the voltage required by the payout control CPU 371 (+ 5V in this example), the payout control CPU
The monitoring range can be expanded with respect to the voltage required by the 371. Therefore, more precise monitoring can be performed.

While the power is not supplied from the + 5V power supply, at least a part of the built-in RAM of the payout control CPU 371 is backed up by connecting the backup power supply supplied from the power supply board to the backup terminal, and the game machine is played back. Contents are saved even if the power is turned off. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 975, so that the payout control CPU 371 returns to a normal operation state. At that time, because the necessary data has been backed up,
At the time of recovery from a power failure or the like, it is possible to return to the game state at the time of power failure.

As described above, in this embodiment, the first power supply monitoring circuit mounted on the power supply board 910 monitors the voltage of the highest power supply VSL among the DC voltages used in the gaming machine. When the voltage of the power supply falls below a predetermined value, a voltage drop signal (power cut detection signal) is generated. At the timing when the power failure detection signal is output, the IC drive voltage is
The voltage value is still sufficient to drive various circuit elements. Therefore, the payout control board 37 that operates with the IC drive voltage
The operating time for the payout control CPU 371 to perform a predetermined power supply stop process is secured.

[0210] Here again, the first power supply monitoring circuit is
Highest power supply VSL among DC voltage used in amusement machines
However, the timing at which the power failure detection signal is generated is such that an operation time is ensured for the electric component control means operating at the IC drive voltage to perform a predetermined power supply stop time process. At the timing, the monitored voltage may not be the highest voltage of the power supply VSL. That is, if at least a voltage higher than the IC drive voltage is monitored, the power failure detection signal can be generated at a timing such that an operation time for the electric component control means to perform a predetermined power supply stoppage process is secured. it can.

In this case, as described above, the voltage to be monitored is + 12V supplied to the various switches of the game machine such as the prize ball count switch 301A, so that the switch-on erroneous detection is prevented when the power is turned off. It is preferable that the voltage can be expected. That is, it is preferable that the voltage drop can be detected before the + 12V power supply voltage, which is the voltage (switch voltage) supplied to the switch, starts to drop. Therefore, it is preferable to monitor at least a voltage higher than the switch voltage.

In the configuration shown in FIG. 31, system reset circuit 975 outputs a low level for a period determined by the capacitance of the capacitor when the power is turned on, and then outputs a high level. That is, the reset release timing is only once. However, the main substrate 31 shown in FIG.
Similarly to the case of 1, the circuit configuration in which the reset release timing occurs a plurality of times may be used.

FIG. 32 is a flow chart showing the main processing of the payout control CPU 371. In the main process,
The payout control CPU 371 first performs necessary initial setting (step S701).

FIG. 33 is a flow chart showing the initial setting process of step S701. In the initial setting process, the payout control CPU 371 first sets an interrupt prohibition (step S701a). Next, the payout control CPU
The 371 sets the interrupt mode to the interrupt mode 2 (step S701b), and sets the stack pointer designated address in the stack pointer (step S701c). Further, the payout control CPU 371 initializes the built-in device register (step S701d), and after initializing the CTC and PIO (step S701e),
The RAM is set to the accessible state (step S70).
1f).

In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore,
In the setting process of the built-in device register of step S701d and the process of step S701e, register setting for setting the channel to be used to the timer mode,
Register settings are made to enable interrupt generation and register settings to set interrupt vectors. And
The interrupt by that channel is used as the timer interrupt described above. If it is desired to generate a timer interrupt every 2 ms, a value corresponding to 2 ms is set as an initial value in a predetermined register (time constant register).

The interrupt vector set in the channel set to the timer mode corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. The timer interrupt flag is set in the timer interrupt process, and when it is detected that the timer interrupt flag is set in the main process, the payout control process is executed.
That is, in the timer interrupt process, settings are made to execute the payout control process, which is an example of the electric component control process.

Further, another one channel of the built-in CTC is used in the counter mode. Therefore, in the built-in device register setting process of step S701d and the process of step S701e, register setting for setting the channel to be used in the counter mode, register setting for permitting interrupt generation, and interrupt vector are set. Register setting is performed.

The interrupt vector set in the channel set in the counter mode corresponds to the head address of the command reception interrupt process described later. Specifically, the start address of the command reception interrupt process is specified by the value set in the I register and the interrupt vector.

In this embodiment, the payout control CPU 3
Also in 71, the interrupt mode 2 is set. Therefore, the built-in CT
An interrupt process based on C count up can be used. Further, it is possible to set an interrupt processing start address according to the interrupt vector sent by the CTC.

An interrupt based on the count-up of CTC channel 2 (CH2) is an interrupt that occurs when the value of the above-mentioned timer counter register CLK / TRG2 becomes "0". Therefore, for example, in step S701e, the initial value "1" is set in the timer counter register CLK / TRG2. Also, CTC channel 3
The interrupt based on the count-up of (CH3) is the CPU
This is an interrupt that occurs when the internal clock (system clock) is counted down and the register value becomes "0", and is used as a 2 ms timer interrupt described later. Specifically, the register value of CH3 is 1 / of the system clock.
It is subtracted in 256 cycles. In step S701e, a value corresponding to 2 ms is set as an initial value in the CH3 register. In this embodiment, CH
The interrupt address for 2 is 0074H and the interrupt address for CH3 is 0076H.

Then, the payout control CPU 371 confirms whether backup data exists in the payout control backup RAM area (step S70).
2). That is, for example, similar to the processing of the CPU 56 of the main board 31, whether or not backup data exists is checked depending on whether or not the backup flag set when the power is turned off is in the set state. If the backup flag is set, it is determined that there is backup data. If it is determined that there is no backup data, it means that there is no unpaid gaming ball at the previous power off, and it is not necessary to return the internal state to the state at the time of power off. Therefore, the payout control CPU 371
Initialization processing that is executed when the power is turned on is executed when the power is not restored (steps S702 and S703).

When the backup data exists in the backup RAM area, the payout control CPU 371
Performs a data check of the backup RAM area (parity check in this example) (step S704).
When the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, so the check result is normal. If the check result is not normal, the internal state cannot be returned to the state when the power was cut off, so the initialization process that is executed when the power is turned on, not when the power is restored, is executed (steps S705 and S70).
3).

If the check result is normal, the payout control CPU 371 performs a payout state recovery process for returning the internal state to the state at the time of power off (step S706). Then, it returns to the address pointed to by the PC (program counter) stored in the backup RAM area (step S707).

Execution of normal initialization processing (step S70)
When 3) is finished, the main processing executed by the payout control CPU 371 shifts to the loop processing in which the monitoring of the timer interrupt flag (step S708) is confirmed.

Note that in this embodiment, step S7
After the presence / absence of backup data is confirmed in 02, if backup data exists, the backup area is checked in step S704, but it is confirmed that the backup area check result is normal. The presence / absence of backup data may be confirmed later. Further, it may be configured to determine whether or not to execute the power failure recovery process by confirming either the presence or absence of backup data or the check of the backup area.

Further, for example, a parity check for determining whether or not to execute a power failure recovery process (step S70)
In the case of 4), that is, when determining whether to restore the game state, the gaming machine is in the payout standby state (state not being paid out) by the payout game ball number data in the stored RAM data. If it is confirmed that the payout state is restored, the initialization process may be executed.

In the normal initialization process, as shown in FIG. 34, a register and RAM clear process (step S9).
01) is performed, and a predetermined initial value is set (step S902). Then, the initial setting process (step S7
Since the interruption is prohibited in 01a), the interruption is permitted before the initialization processing is completed (step S90).
3).

In this embodiment, the payout control CPU 3
CH3 of CTC 71 is set to repeatedly generate timer interrupts. Further, the repetition cycle is set to 2 ms. Then, as shown in FIG. 35, when a timer interrupt occurs, the payout control CPU 371 sets a timer interrupt flag (step S711). Although it is clearly shown in FIG. 35 that the interrupt is permitted (step S
710) In the 2 ms timer interrupt process, the interrupt permission state is first set. That is, during the 2 ms timer interrupt process, the interrupt is enabled.

The payout control CPU 371 operates in step S7.
When it is detected in 08 that the timer interrupt flag is set, the timer interrupt flag is reset (step S709) and the payout control process is executed (step S710). According to the above control, in this embodiment, the payout control process is activated every 2 ms. In this embodiment, only the flag is set in the timer interrupt process and the payout control process is executed in the main process, but the payout control process may be executed in the timer interrupt process.

When the power is turned on, the payout control CPU 371 can determine whether the normal initializing process is to be performed or the payout state is to be restored by simply checking the data in the backup RAM area. That is, by simple judgment,
The payout process can be restarted for the unpaid gaming balls. Further, in this embodiment, like the game control on the main board 31, the storage of stored contents is ensured by the parity check code.

FIG. 36 is an explanatory diagram showing a usage example of the RAM incorporated in the payout control CPU 371. In this example,
In the backup RAM area, a total number memory (for example, 2 bytes) and a rental ball number memory are formed. The total quantity storage stores the total number of payout quantities instructed from the main board 31 side. The loaned ball number storage is for storing the number of unpaid lent balls.

FIG. 37 is an explanatory diagram showing an example of the structure of a reception buffer for storing the payout control command received from the main board 31. In this example, a ring buffer type reception buffer that can store six 2-byte payout control commands is used. Therefore, the reception buffer is composed of 12-byte areas of the fixed command buffers 1 to 12. Then, a command reception number counter indicating which area to store the received command is used. The command reception number counter takes a value of 0-11.

FIG. 38 is a flow chart showing the payout control command receiving process by the interrupt process. The payout control INT signal from the main board 31 is sent to the payout control CPU 371.
Is input to the CLK / TRG2 terminal. Therefore, when the INT signal from the main board 31 is turned on, the payout control CPU 371 is interrupted and the payout control command reception process shown in FIG. 38 is started.

Although the command receiving process of the payout control means will be described here, the same command receiving process is executed by the display control means, the lamp control means and the voice control means.

In the process of receiving the payout control command, the payout control CPU 371 first saves each register in the stack (step S850). Next, the input port 3 assigned to the input of the payout control command data
The data is read from 72a (step S851). Then, it is confirmed whether or not it is the first byte of the payout control command having a 2-byte structure (step S852). Whether or not it is the first byte is confirmed by whether or not the first bit of the received command is "1". The head bit is "1" in the MODE byte (first byte) of the payout control command having a 2-byte structure (see FIG. 19). Therefore, the payout control CPU 371
If the first bit is "1", it is determined that the valid first byte has been received, and the received command is stored in the confirmed command buffer indicated by the command reception number counter in the reception buffer area (step S853).

If it is not the first byte of the payout control command, it is confirmed whether or not the first byte has already been received (step S854). Whether or not the data has already been received is confirmed by whether or not valid data is set in the reception buffer (confirmation command buffer).

If the first byte has already been received,
It is confirmed whether the first bit of the received 1 byte is "0". If the first bit is "0",
Assuming that the valid second byte has been received, the received command is stored in the confirmed command buffer indicated by the command reception number counter + 1 in the reception buffer area (step S855). The first bit is "0" in the EXT byte (second byte) of the payout control command having a 2-byte structure (see FIG. 19). If the confirmation result in step S854 indicates that the first byte has already been received, the process ends if the first bit of the data received as the second byte is not "0".

When the command data of the second byte is stored in step S855, 2 is added to the command reception number counter (step S856). Then, it is confirmed whether the command reception counter is 12 or more (step S857), and if it is 12 or more, the command reception number counter is cleared (step S858). After that, the saved registers are restored (step S859),
The interrupt permission is set (step S859).

During the command reception interrupt process, the interrupt is disabled. As described above, the interrupt enable state is set during the 2ms timer interrupt process. Therefore, if a command reception interrupt occurs during the 2ms timer interrupt process, the command reception interrupt process is executed with priority. It Further, even if a 2 ms timer interrupt occurs during the command reception interrupt process, the interrupt process is kept waiting. As described above, in this embodiment, the processing priority of the command reception processing from the main board 31 is high. Further, since the other interrupt processing is not executed during the command receiving processing, the maximum time required for the command receiving processing is determined. If the other interrupt processing can be executed during the command receiving processing, it is difficult to estimate the maximum time required for the command receiving processing. Since the maximum time required for the command reception process is determined, the period C in the command transmission process of the game control means (see FIG. 20)
Can be accurately determined.

The payout control command has a 2-byte structure, and the first byte (MODE) and the second byte (EX
It is configured so that it can be immediately distinguished from T) on the receiving side.
That is, the receiving side can immediately detect whether the data as MODE or the data as EXT is received by the first bit. Therefore, as described above, it is possible to easily determine whether or not proper data has been received.

FIG. 39 is a flow chart showing the payout control process of step S710. In the payout control process, the payout control CPU 371 first determines whether or not the prize ball count switch 301A and the ball lending count switch 301B input to the input port 372b via the relay board 72 are turned on (switch process: Step S7
51).

Next, the payout control CPU 371 performs processing such as checking the signal input state from a sensor (for example, a motor position sensor for detecting the number of revolutions of the payout motor 289) to determine the state of the sensor ( Input determination processing: step S752). The payout control CPU 371 further analyzes the received payout control command and executes a process according to the analysis result (command analysis execution process: step S75).
3).

Next, the payout control CPU 371 sets the payout stop state when the payout stop instruction command is received from the main board 31, and releases the payout stop state when the payout start instruction command is received (step S754). ).
In addition, prepaid card unit control processing is performed (step S755).

Next, the payout control CPU 371 controls the payout of the lent balls in response to the ball lending request (step S756). Further, the payout control CPU 371 performs a prize ball control process for paying out the number of prize balls stored in the total number memory (step S757). And C for payout control
The PU 371 includes the output port 372c and the relay board 72.
A drive signal is output to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the step S75.
The payout motor control process of rotating the payout motor 289 for the number of revolutions set in the ball lending control process of 6 or the prize ball control process of step S757 is performed (step S758).

Incidentally, in this embodiment, the payout motor 2
A stepping motor is used as 89, and a 1-2 phase excitation method is used to control the payout motor 289. Therefore, specifically, in the payout motor control process, eight types of excitation pattern data are repeatedly output to the payout motor 289. Further, in this embodiment, each excitation pattern data is output by 4 ms.

Next, error detection processing is performed, and a predetermined display is performed on the error display LED 374 according to the result (error processing: step S759). There are the following eight types of detected errors, for example.

Prize ball path error: When no prize ball count switch 301A detects passage of a game ball when the prize ball payout operation ends or when the payout motor 289 makes one rotation. “0” is displayed on the error display LED 374.

Ball lending route error: When the payout operation of the ball lending is completed or when the payout motor 289 makes one rotation, no ball lending count switch 301B detects the passage of the game ball. “1” is displayed on the error display LED 374.

Prize ball count switch ball clogging error: When the prize ball count switch 301A detects ON for 0.5 seconds or more. “2” is displayed on the error display LED 374.

Ball lending count switch Ball clogging error:
When the ball lending count switch 301B is turned on for 0.5 seconds or longer. “3” is displayed on the error display LED 374.

Discharge motor ball biting error: Discharge motor 28
When 9 does not rotate normally. Specifically, when the payout motor position sensor is kept on for a predetermined period or longer, or is off for a predetermined period or longer. “4” is displayed on the error display LED 374. Note that when a payout motor ball biting error occurs, the payout control CPU 371 causes 50 ms.
After outputting the reference excitation phase of, the four types of excitation pattern data of the excitation pattern data of 1-2 phase excitation are set to 8
Reverse rotation and forward rotation of the payout motor 289 are repeated by outputting every ms.

Prepaid card unit not connected error:
When the OFF of the VL signal is detected. Error display LED3
“5” is displayed on 74.

Prepaid card unit communication error: When it is detected that a signal is output from the prepaid card unit 50 at a timing other than the specified timing. Error display LE
“6” is displayed in D374.

Dispensing stop state: When a dispensing control command indicating discontinuation of dispensing is received from the main board 31. Error display LE
“7” is displayed in D374. When a payout control command indicating the start of payout is received from the main board 31,
After 2002 ms from that point, the payout stopped state is returned to the payable state.

Further, processing for controlling the information signal output from the external connection terminal (not shown) is performed (output processing: step S760). The information signal is a signal that is turned on for a predetermined time for each payout unit (for example, 25 pieces) of the rented balls, and then turned off for a predetermined time.

FIG. 40 is a flow chart showing an example of the switch process of step S751. In the switch processing, the payout control CPU 371 confirms whether or not the prize ball count switch 301A is in the ON state (step S751a). If it is in the ON state, the payout control CPU 371 increments the prize ball count switch ON counter by 1 (step S751b). The prize ball count switch on counter is the prize ball count switch 30.
This is a counter for counting the number of times the ON state of 1A is detected.

Then, the value of the prize ball count switch ON counter is checked (step S751c), and if the value is 2, it is determined that one prize ball has been paid out. When it is determined that one prize ball has been paid out, the payout control CPU 371 decrements the prize ball unpaid counter (the number of prize balls stored in the total number memory) by -1 (step S751d).

When it is confirmed in step S751a that the prize ball count switch 301A is not in the ON state, the payout control CPU 371 clears the prize ball count switch ON counter (step S751e). And in this embodiment, the ball lending count switch 3
It is confirmed whether or not 01B indicates the ON state (step S751f). If it is in the ON state, the payout control CPU 371 increments the ball lending count switch ON counter by 1 (step S751g). Ball lending count switch ON counter is ball lending count switch 301
This is a counter for counting the number of times the ON state of B is detected.

Then, the value of the ball lending count switch ON counter is checked (step S751h), and if the value is 2, it is determined that one ball has been paid out. When it is determined that one loan ball has been paid out, the payout control CPU 371 causes the loan ball unpaid number counter (the number of loan balls stored in the loan ball number storage).
Is decremented by 1 (step S751i).

When it is confirmed in step S751f that the ball lending count switch 301B is not on, the payout control CPU 371 clears the ball lending count switch ON counter (step S751j).

FIG. 41 is a flow chart showing an example of the command analysis execution processing of step S753. In the command analysis execution processing, the payout control CPU 371
It is confirmed whether or not there is a received command in the confirmed command buffer area (step S753a). If there is a received command, it is confirmed whether or not the received payout control command is the payout amount instruction command (step S753).
b). If there are multiple received commands in the confirmed command buffer area, check whether or not the received payout control command is the payout amount instruction command by checking the received command that was received first. Be seen.

If the received payout control command is the payout quantity instruction command, the quantity instructed by the payout quantity instruction command is added to the total quantity storage (step S753).
c). That is, the payout control CPU 371 causes the main board 3
The number of prize balls included in the payout amount instruction command sent from the first CPU 56 is stored in the backup RAM area (total number storage).

If necessary, the payout control CPU 371 performs the subtraction of the command reception number counter and the reception command shift processing in the confirmed command buffer area.

FIG. 42 is a flow chart showing an example of the payout stop state setting process of step S754. In the payout stop state setting process, the payout control CPU 371
It is confirmed whether or not there is a received command in the confirmed command buffer area (step S754a). If there is a received command in the confirmed command buffer area, it is confirmed whether the received payout control command is a payout stop instruction command (step S754b). If it is the payout stop instruction command, the payout control CPU 371 sets the payout stop state (step S754c).

When it is confirmed in step S754b that the received command is not the payout stop instruction command, it is confirmed whether or not the received payout control command is the payout start instruction command (step S754d). If it is the payout start instruction command, the payout stop state is released (step S7).
54e).

FIG. 43 is a flow chart showing an example of the prepaid card unit control processing in step S755. In the prepaid card unit control process, the payout control CPU 371 confirms whether or not the VL signal input from the card unit control microcomputer is detected (step S755a). If the VL signal is not detected, the VL signal non-detection counter is incremented by 1 (step S755b). Further, the payout control CPU 37
1 confirms whether the value of the VL signal non-detection counter is 125 in this example (step S755c). If the value of the VL signal non-detection counter is 125, the payout control CP
The U371 stops the output of the firing control signal to the firing control board 91 and stops the drive motor 94 (step S7).
55d).

By the above processing, 125 times (2 ms ×
(125 = 250 ms) When the OFF of the VL signal is continuously detected, the ball firing prohibition state is set.

When the VL signal is detected in step S755a, the payout control CPU 371 clears the VL signal non-detection counter (step S755e). If the output control signal output is stopped (step S755f), the payout control CPU 371 starts the output control signal output to the discharge control board 91 to put the drive motor 94 into an operable state (step S755g). .

44 and 45, step S756 is executed.
It is a flow chart which shows an example of the ball lending control processing of.
In addition, in this embodiment, the maximum value of the continuous payout amount is one unit (for example, 25) of the lending sphere, but the maximum value of the continuous payout amount may be another number.

[0270] In the ball lending control process, the payout control CP
The U371 confirms whether or not the ball lending is being paid out (step S511), and if the ball lending is being paid out, the process shifts to the process during ball lending shown in FIG. In addition, whether or not the lent-out of the lent-out sphere is being performed is determined by the state of the lent-out-of-ball-lending flag described later. If the loan balls are not being paid out, it is confirmed whether or not the prize balls are being paid out (step S512). Whether or not the prize balls are being paid out is determined by the state of a prize ball processing flag described later.

If neither the lending balls nor the prize balls are being paid out, the payout control CPU 371 confirms whether or not there is a ball lending request from the card unit 50 (step S5).
13). When there is a request, the ball lending processing flag is turned on (step S514), and 25 (one unit of ball lending: 100 yen here) is set in the backup RAM area storage of the number of lending balls (step S515). Then, the payout control CPU 371 turns on the EXS signal (step S516). Further, the distribution solenoid 310 is driven to set the ball distribution member 311 below the ball dispensing device 97 to the ball lending side (step S517). Further, the payout motor 289 is turned on (step S51
8), and shifts to the processing during ball lending shown in FIG.

The payout motor 289 is turned on by
Strictly speaking, the BRQ signal is turned off to indicate that the card unit 50 has recognized the acceptance. The ball lending processing flag is set in the backup RAM area.

FIG. 45 is a flowchart showing the processing during ball lending in the payout control processing by the payout control CPU 371. In the ball lending process, the payout motor 289 is turned on if it is not turned on. In addition, in this embodiment,
In the switch processing of step S751, since it is confirmed whether or not the game balls have been paid out by the detection output of the ball lending count switch 301B, the subtraction of the number of lent balls is not performed in the ball lending control process. In the ball lending control process, the payout control CPU 371 confirms whether or not it is in the lending ball passage waiting time (step S519). If it is not during the lending ball passage waiting time, the lending balls are paid out (step S520), and it is confirmed whether or not the driving of the payout motor 289 should be ended (whether the payout operation for one unit is ended) (step S521). ). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts is completed. The rotation corresponding to the predetermined number of payouts is monitored by the output of the payout motor position sensor. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S522).
The lending ball passage waiting time is set (step S52).
3).

In the ball lending process of step S520, the ON / OFF of the payout motor position sensor is monitored by a timer. However, if the ON state or the OFF state continues for a predetermined time or more, the payout control CPU 371 causes the payout motor to operate. It is determined that a ball biting error has occurred.

If it is during the lending ball passage waiting time in step S519, the payout control CPU 371 confirms whether or not the lending ball passage waiting time has ended (step S52).
4). The lending ball passage waiting time is the time from when the last payout ball is paid out by the payout motor 289 to when it passes through the ball lending count switch 301B. When confirming the end of the lending ball passage waiting time, all of the one unit of lending balls have been paid out, so that it is possible to indicate to the card unit 50 that the next ball lending request can be accepted. The EXS signal is turned off (step S524). The distribution solenoid is turned off (step S5).
25), the ball lending processing flag is turned off (step S5).
27). If the last payout ball has not passed the ball lending count switch 301B before the lending ball passage waiting time elapses, a ball lending route error is determined. Also,
In this embodiment, prize balls and ball lending are performed by the same payout device.

If the BRQ signal, which is the ball lending request signal, is turned on again within a predetermined period after turning off the EXS signal indicating acceptance of the ball lending request, the ball lending is performed without turning off the distribution solenoid and the payout motor. The processing may be continued. That is, a predetermined unit (100 yen unit in this example)
Instead of performing the ball lending process every time, the ball lending process may be continuously executed.

The content of the number of rented balls is stored by the backup power supply of the power supply board 910 for a predetermined period even if the power of the game machine is turned off. Therefore, when the power is restored during the predetermined period, the payout control CPU 371 can continue the ball lending process based on the contents of the number of lent balls stored.

In FIG. 46 and FIG. 47, step S757 is executed.
It is a flow chart which shows an example of the prize ball control processing. In this example, the maximum value of the continuous payout amount is the same as one unit of the lending sphere (for example, 25), but the maximum value of the continuous payout amount may be another number.

In the prize ball control process, the payout control CPU
The 371 confirms whether or not the rental balls are being paid out (step S531). Whether or not the lent sphere is being paid out is determined by the state of the sphere lending processing flag. If the renting balls are not being paid out, it is confirmed whether or not the prize balls are being paid out (step S
532), if the prize balls are being paid out, the process moves to the prize ball process shown in FIG. Whether or not the prize balls are being paid out is determined by the state of a prize ball processing flag described later.

If neither the lending balls nor the prize balls are being paid out, the payout control CPU 371 confirms whether or not there is a ball lending preparation request from the card unit 50 (step S).
533). Whether or not there is a ball lending preparation request is made by confirming whether the BRDY signal input from the card unit 50 is on (requested) or off (no request).

If there is no ball lending preparation request from the card unit 50, the payout control CPU 371 confirms whether or not the number of prize balls (the number of unpaid prize balls) stored in the total number memory is not 0 ( Step S534). If the number of prize balls stored in the total number memory is not 0, CP for prize ball control
U371 turns on the prize ball processing flag (step S5).
35), and it is confirmed whether or not the value of the total number storage is 25 or more (step S536). The prize ball processing flag is set in the backup RAM area.

The number of prize balls stored in the total number memory is 2
If it is 5 or more, the CPU 371 for payout control sets the 25 payout operation in order to output a drive signal to the payout motor 289 so as to rotate the payout motor 289 until paying out 25 game balls. (Step S53
7). If the number of prize balls stored in the total number memory is not 25 or more, the payout control CPU 371 drives the payout motor 289 to rotate until all the game balls stored in the total number memory are paid out. In order to output, the total number payout operation is set (step S53).
8). Next, the payout motor 289 is turned on (step S538). Since the distribution solenoid is off, the ball distribution member below the ball payout device 97 is set to the prize ball side. Then, the process shifts to the process of paying out prize balls in the prize ball control process shown in FIG.

FIG. 47 is a flow chart showing an example of a winning ball process in the payout control process by the payout control CPU 371. In the prize ball control processing, the payout motor 289
If is not on, turn it on. It should be noted that, in this embodiment, in the switch processing of step S751, it is confirmed whether or not the game balls have been paid out by the detection output of the prize ball count switch 301A. Is not done. In the process during the prize ball, the payout control CPU 371 confirms whether or not the prize ball passage waiting time is in progress (step S540). If it is not during the prize ball waiting time, the prize balls are paid out (step S
541), should the drive of the payout motor 289 be ended (2
Whether or not a predetermined number of payout operations of 5 or less than 25 has been completed) is confirmed (step S542). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts is completed. The rotation corresponding to the predetermined number of payouts is monitored by the output of the payout motor position sensor. When the rotation corresponding to the predetermined number of payouts is completed, the payout control C is performed.
The PU 371 stops driving the payout motor 289 (step S543) and sets the prize ball passage waiting time (step S544). The prize ball passage waiting time is the time from when the last payout ball is paid out by the payout motor 289 until it passes through the prize ball count switch 301A.

If it is during the prize ball passage waiting time in step S540, the payout control CPU 371 confirms whether or not the prize ball passage waiting time is over (step S545).
When the prize ball waiting time is over, step S537
Alternatively, all the prize balls set in step S538 have been paid out. Therefore, the payout control CPU 371
If the award ball passage waiting time has ended, the award ball processing flag is turned off (step S546). If the last payout ball has not passed the prize ball count switch 301A before the prize ball passage waiting time has elapsed, a prize ball path error is determined.

In this embodiment, step S5
11, the ball lending is prioritized over the prize ball processing according to the determination in step S531, but the prize ball processing may be prioritized over the ball lending.

The contents of the total number storage and the number of lent balls stored are stored in the power supply board 910 for a predetermined period even if the power of the game machine is turned off.
Saved by backup power supply. Therefore, when the power is restored during the predetermined period, the payout control CPU 371
Can continue the payout process based on the contents of the total number storage.

The payout control CPU 371 manages the number of prize balls instructed from the main board 31 as the total number by storing the number of prize balls. However, for each number of prize balls (for example, 15, 10, 6, 6).
Individual). For example, a number counter corresponding to each number of prize balls is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When the prize ball payout corresponding to the number counter is performed, the number counter is decremented by 1 (in this case, the subtraction process is performed in the payout control process).
Also in that case, each number counter is formed in the backup RAM area. Therefore, even if the power of the gaming machine is turned off, if the power is restored within a predetermined period, the payout control CPU 371.
Can continue the prize ball payout process based on the content of each number counter.

FIG. 48 is a flow chart showing an example of a power failure occurrence NMI process executed according to an NMI based on a voltage change signal from the power supply monitoring circuit of the power supply board 910. In this embodiment, the NMI interrupt address is 00
66H. In the power failure occurrence NMI process, the payout control CPU 371 first stores the content of the interrupt prohibition flag in the parity flag (step S801). Then
The interrupt is set to be prohibited (step S802). Power outage N
In the MI processing, in this example, similar to the processing executed in the main board 31, a checksum generation processing for ensuring the storage of the RAM contents is performed. If another interrupt process is performed during that process, it is possible that the payout control CPU 371 will fall to a voltage at which it cannot operate before the checksum generation process is completed. , Settings are made so that other interrupts do not occur. In addition,
Steps S804 to S81 in power failure occurrence NMI processing
0 is an example of the process when the power supply is stopped.

If a CPU having a specification such that another interrupt will not be applied during the interrupt process, the process of step S802 is unnecessary.

Next, the payout control CPU 371 confirms whether or not the backup flag has already been set (step S803). If the backup flag has already been set, no further processing will be performed. If the backup flag is not set, the following power supply stop process is executed. That is, the processes of steps S804 to S810 are executed.

First, the contents of each register are backed up R
It is stored in the AM area (step S804). Then, the backup flag is set (step S805).
Then, an appropriate initial value is set in the backup check data area of the backup RAM area (step S80).
6) Sequentially exclusive-ORing the initial values and the data in the backup RAM area and inverting them (step S807), and setting the final calculated value in the backup parity data area (step S808). Also, RA
The M access is prohibited (step S809). When the power supply voltage decreases, the level of various signal lines may become unstable and the contents of RAM may be corrupted. If the RAM access is prohibited in this way, the data in the backup RAM may be corrupted. There is no.

Further, the payout control CPU 371 has all the output ports (in this embodiment, the output port 372).
c, 372g, 372e, and I / O port 372f
Output port part of), a clear signal is output. Therefore, all the output ports are turned off by the clear signal (step S810).

Next, the payout control CPU 371 starts loop processing. That is, no processing is performed. Therefore, before the operation is prohibited from the outside by the system reset signal from the reset IC 976 shown in FIG. 31, the operation is stopped internally. Therefore, when the power is turned off, the payout control CPU 371 reliably stops operating. As a result, due to the above-mentioned RAM access prohibition control and operation stop control, R caused by an abnormal operation that may occur as the power supply voltage decreases
It is possible to reliably prevent the contents of the AM from being destroyed.

In this embodiment, the power failure occurrence NM
In the I process, the program was put in a loop in the final part,
It may be configured to issue a HALT instruction.

As described above, the backup flag set after storing the register contents in the RAM area indicates whether or not there is backup data to be restored when the power is turned on (whether or not to recover from a power failure). Used in determining. Also, steps S801 to S810
Processing is completed before the payout control CPU 371 receives the system reset signal from the system reset circuit 975. In other words, to complete before receiving the system reset signal from the system reset circuit 975,
The detection voltage of the voltage monitoring circuit is set.

In this embodiment, the backup flag is confirmed at the start of the power supply stop process. If the backup flag has already been set, the power supply stop process is not executed. As mentioned above,
The backup flag is a flag indicating that the backup of necessary data is completed, and then the power supply stop process is completed. Therefore, for example, even if an NMI occurs again for some reason in the reset waiting loop state, the power supply stoppage process will not be repeatedly executed.

However, if a CPU having a specification such that another interrupt is not generated during the interrupt processing is used, the determination in step S803 is unnecessary.

Further, in this embodiment, the payout control C
PU371 is a non-maskable external interrupt terminal (NMI terminal)
Although the NMI interrupt signal from the power supply substrate (NMI interrupt signal from the power supply monitoring means) is detected via the, the NMI interrupt signal may be introduced to the maskable interrupt interrupt terminal (INT terminal). In that case, the INT process executes the power failure occurrence NMI process shown in FIG. Also, the NMI interrupt signal may be detected via the input port. In that case, the input port is monitored in the main process executed by the payout control CPU 371.

FIG. 49 is an explanatory diagram for explaining an example of the backup parity data creating method. However,
In the example shown in FIG. 49, the size of the data in the backup data RAM area is 3 bytes for simplicity. In the power outage generation process based on the power supply voltage drop, as shown in FIG. 49, initial data (00H in this example) is set in the backup check data area. Next, "00
The exclusive OR of "H" and "F0H" is obtained, and the result is exclusive OR of "16H". Further, the result is exclusive ORed with "DFH". Then, the value (“C6H” in this example) obtained by inverting the result (“39H” in this example) is set in the backup parity data area.

When the power is turned on again, the parity diagnosis is performed in the power failure recovery process. If all the data in the backup area is saved as it is, the data as shown in FIG. 49 is set in the backup area when the power is turned on again.

In the processing of step S704, the payout control CPU 371 performs the same processing as the processing executed in steps S806 and S807 of FIG. That is, initial data (00H in this example) is set in the backup check data area, and "00H" is set.
And "F0H" are exclusive ORed and the result and "1
6H "is exclusive ORed. Further, the result is exclusive ORed with "DFH". Then, the final calculation result obtained by inverting the result (“39H” in this example) is obtained. If all the data in the backup area is saved as it is, the final calculation result matches "C6H", that is, the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final calculation result will not be "C6H".

Therefore, the payout control CPU 371 compares the final calculation result with the data set in the backup check data area, and if they match, the parity diagnosis is normal. If they do not match, the parity diagnosis is abnormal.

As described above, in this embodiment, the payout control means is provided with a storage means (backup RAM in this example) that is backed up for a predetermined period even if the power of the gaming machine is turned off. CPU for payout control at the time of charging
371 (specifically, a program executed by the payout control CPU 371) is configured to perform a payout state recovery process (step S706) for recovering the payout state based on the backup data if the storage unit is in the backup state. .

The payout state recovery process will be described below. FIG. 50 is a flowchart showing an example of the payout state recovery processing shown in step S706 of FIG. In this example, the payout control CPU 371 uses the backup R
The value stored in the AM is restored in the register (step S861). Then, based on the data stored in the backup RAM, processing for recovering the payout state at the time of power failure is performed. For example, a flag in-progress processing flag is set.

When the payout state is restored, in this embodiment, the payout control CPU 371 restores the backup R in order to restore the interrupt permitted / prohibited state at the time of the previous power-off.
The value of the parity flag stored in the AM is confirmed (step S862). If the parity flag is clear, an interrupt permission setting is made (step S863). on the other hand,
If the parity flag is turned on, it is as it is (step S
The payout state recovery process is ended (while the interrupt prohibition state set in 701a remains).

Here, although the payout state recovery processing program is configured to return to the payout control main processing when the payout state recovery processing ends, the stack pointer stored in the power supply stop processing points to it. The address may be returned to the address stored in the stack area (in the backup RAM area) (the address that was being executed when the NMI interrupt occurred when the power was turned off).

As described above, after the initialization process is started and before the payout state recovery process is completed or before the initialization process is completed, the interrupt disabled state is set. Therefore, it is possible to prevent the processing from being interrupted by the interruption. As a result, it is possible to surely complete the initialization process, the determination as to whether or not the power-off state should be restored according to the contents of the backup data storage area, and the restoration process (or the initialization process). Even in the case where the configuration is such that the interrupt-disabled state is set before the recovery process is completed as described above, the interrupt-disabled / enabled condition at power-off is saved in the parity flag, It is possible to reliably restore the interrupt prohibited / permitted state when the power is turned off.

In each of the embodiments, the payout control means is taken as an example, but other electric part control means, for example,
The display control means, the voice control means, the lamp control means, etc. can surely receive the control command from the game control means by the processing as described above. Further, the display control means, the sound control means, the lamp control means, etc. are also configured to perform the above-described power supply monitoring control, and a power failure occurrence NM
In the I process, a clear signal may be output to stop the operation of the electric component controlled by each electric component control means. With such a configuration, the operation of each electric component can be stopped before the stop state is reached, and power restoration can be waited in an appropriate stop state.

Further, in the above-mentioned embodiment, the power supply monitoring circuit is provided on the power supply board 910, but the power supply monitoring circuit may be provided on the electric component control boards such as the main board 31 and the payout control board 37. . When the electric component control board on which the power supply circuit is mounted is configured,
No power monitoring circuit is installed.

Pachinko gaming machine 1 of each of the above embodiments
Is a first-class pachinko gaming machine in which a predetermined game value can be given to the player when the stop symbol of the special symbol that is variably displayed on the variable display portion 9 based on the start winning is a combination of the predetermined symbols. However, if there is a prize in the predetermined area of the electric accessory to be released based on the start prize, the second kind of pachinko gaming machine that allows the player to be provided with a predetermined game value, and it is variably displayed based on the start prize. The present invention can be applied even to a third-class pachinko gaming machine in which a predetermined right is generated or continues when there is a prize for a predetermined electric accessory that is released when a stop symbol of a pattern is a combination of predetermined symbols.

Furthermore, the present invention can be applied not only to a pachinko gaming machine but also to a slot machine or the like provided with an electric component that performs some operation.

[0312]

As described above, according to the present invention, in the gaming machine, the command output processing is commonly used to output the command data and the take-in signal to the plural kinds of electric component control means, and the command output means However, in the command output process,
After the command data is output and the capture signal is output, the next command data is output after a predetermined time has elapsed, and the predetermined period is the period required for each of the plurality of types of electrical component control means to receive the command data. Since it is configured to be longer than the maximum period of, in the gaming machine of the configuration in which the command is sent from the game control means to the other plurality of electric component control means, each electric component control means reliably receives the command. There is an effect that can be. Further, it is possible to reduce the program capacity related to command transmission of the game control means.

When one command information sent to the electric component control means is composed of two command data, for example, the command information is divided into a command classification and a command type to simplify the command receiving process. As a result, it becomes possible to check the received command based on the mutual relation between the two command data, and it is possible to perform the proper transmission / reception processing of the command information. Further, it is possible to reduce the possibility of malfunction due to data corruption due to noise or the like during transfer of the command information.

When the command output means is configured to be able to output one command data and the next command data in a distinguishable manner, each electric component control means facilitates the received command check. It can be carried out.

When the command output means is configured to maintain the output of the command data until the predetermined period of time elapses, the electric component control means can stably fetch the command data.

When the game control means is constructed to have an area capable of simultaneously storing a plurality of commands to be output, even if a plurality of command transmission requests are generated at the same time, they are based on those requests. The command sending process is executed reliably.

If the command output process is configured to include a process for determining which of the plurality of types of electric component control means the command data is to be output, the command output processing is executed. Even if the output process is shared by the electric component control means, the command is appropriately transmitted to the electric component control means to be transmitted.

When the predetermined period until the next command data is output is configured to be longer than the period from the output of the command data to the output of the fetch signal, the game control means generates an electric signal. The output state of the command sent to the component control means is stable, and the electric component control means can reliably receive the command.

If the value giving control means as the electric part controlling means can store a plurality of input command data at the same time, the received command data will not be lost even if the value giving control processing is delayed. Since the command data from the game control means can be received without fail, the value to be given to the player can be surely given, and the player can be prevented from being disadvantaged.

[Brief description of drawings]

FIG. 1 is a front view of a pachinko gaming machine as viewed from the front.

FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine.

FIG. 3 is a rear view of the mechanism board of the pachinko gaming machine as viewed from the rear side.

FIG. 4 is a front view showing a configuration around an intermediate base unit installed on a mechanism plate.

FIG. 5 is an exploded perspective view showing a ball dispensing device.

FIG. 6 is a block diagram showing a circuit configuration of a game control board (main board).

FIG. 7 is a block diagram showing a circuit configuration in a display control board.

FIG. 8 is a block diagram showing a circuit configuration in a lamp control board.

FIG. 9 is a block diagram showing a circuit configuration in the voice control board.

FIG. 10 is a block diagram showing components related to a prize ball, such as components of a payout control board and a ball dispensing device.

FIG. 11 is a block diagram showing an example of a configuration around a CPU for power supply monitoring and power supply backup.

FIG. 12 is a block diagram showing a configuration example of a power supply board.

FIG. 13 is a flowchart showing an example of main processing executed by a CPU on a main board.

FIG. 14 is an explanatory diagram showing an example of a method of determining whether or not to execute a game state recovery process.

FIG. 15 is a flowchart showing an example of initial setting processing.

FIG. 16 is a flowchart showing an example of initialization processing.

FIG. 17 is a flowchart showing an example of 2 ms timer interrupt processing.

FIG. 18 is a flowchart showing an example of game control processing.

FIG. 19 is an explanatory diagram showing a configuration example of a payout control command.

FIG. 20 is a timing diagram showing a relationship between a control signal and an INT signal.

FIG. 21 is an explanatory diagram showing an example of contents of a payout control command.

FIG. 22 is an explanatory diagram showing an example of the content of a display control command.

FIG. 23 is an explanatory diagram showing an example of contents of a lamp control command.

FIG. 24 is an explanatory diagram showing an example of the content of a voice control command.

FIG. 25 is a flowchart showing a special symbol process process.

FIG. 26 is a flowchart showing a switch process.

FIG. 27 is a flowchart showing a winning ball signal processing.

FIG. 28 is an explanatory diagram showing the structure of a command transmission table.

FIG. 29 is a flowchart showing command control processing.

FIG. 30 is a flowchart showing command transmission processing.

FIG. 31 is a block diagram showing a configuration example around a payout control CPU for power supply monitoring and power supply backup.

FIG. 32 is a flowchart showing an example of a main process executed by a payout control CPU.

FIG. 33 is a flowchart showing an example of an initial setting process of the payout control CPU.

FIG. 34 is a flowchart showing an example of initialization processing of a payout control CPU.

FIG. 35 is a flowchart showing an example of timer interruption processing of the payout control CPU.

FIG. 36 is an explanatory diagram showing a configuration example of a RAM in the payout control means.

FIG. 37 is an explanatory diagram showing a configuration example of a reception buffer.

38 is a flowchart showing an example of command reception processing of the payout control CPU. FIG.

FIG. 39 is a flowchart showing an example of a payout control process executed by a payout control CPU.

FIG. 40 is a flowchart showing an example of a switch process.

FIG. 41 is a flowchart showing an example of command analysis execution processing.

FIG. 42 is a flowchart showing an example of payout stop state setting processing.

FIG. 43 is a flowchart showing an example of prepaid card unit control processing.

FIG. 44 is a flowchart showing an example of ball lending control processing.

FIG. 45 is a flowchart showing an example of ball lending control processing.

FIG. 46 is a flowchart showing an example of prize ball control processing.

FIG. 47 is a flowchart showing an example of prize ball control processing.

FIG. 48 is a power failure occurrence NM executed by the payout control CPU
It is a flow chart which shows an example of I processing.

FIG. 49 is an explanatory diagram illustrating an example of a backup parity data creation method.

FIG. 50 is a flowchart showing an example of a payout state recovery process executed by a payout control CPU.

[Explanation of symbols]

1 Pachinko machine 31 Main board 37 Discharge control board 53 Basic circuit 56 CPU 371 CPU for payout control 570 output ports (output port 0) 571 output port (output port 1) 572 output port (output port 2) 573 output port (output port 3) 574 output port (output port 4) 902 Power supply monitoring IC 910 Power board

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) A63F 7/02 324 A63F 7/02 304 A63F 7/02 320 A63F 7/02 326

Claims (6)

(57) [Claims] 1. A player can play a predetermined game.
A gaming machine, Control the progress of the gameCommand as command information with
OutputGame controlFor microcomputerWhen,Receives commands from the game control microcomputer
Depending on the command received and received Electricity provided in gaming machines
Control partsDoMultiple to perform electrical component control processingThe micro
ComputerIncluding,The command consists of 2-byte command data, Game controlFor microcomputerIs the pluralThe Ma
Black computerCommand data and commands for
For outputting the acquisition signal that specifies the acquisition of data
Execute command output processThenCommand output processTo
ThereThe pluralityMicrocomputerCommand for
Data and acquisition signalsAnd call the same subroutine
Output The aboveMicrocomputer for game controlIsTo the command
The first byteOutput the command data and output the capture signal.
After output, predeterminedperiodAfter the passageSecond byteCommand
Output the dataThe game control microcomputer, The predetermined period
The aboveMicrocomputerEach of the
Maximum of the time required to receive the
As a constant value over the periodAnd output the command dataThis
A gaming machine characterized by and. 2. A game control microcomputer is co
Command data of the first byte and 2 bytes in the command
The gaming machine according to claim 1, which outputs the command data for the eyes in a distinguishable manner on the receiving side . 3. The gaming machine according to claim 1, wherein the game control microcomputer has an area capable of simultaneously storing a plurality of commands to be output. 4. A game control microcomputer, any microcode of a plurality of microcomputers
4. A process according to claim 1, wherein a process for determining whether to output a command to a computer is executed .
The gaming machine according to. 5. The second byte of the predetermined period until the output command data 1 wherein the long claims 1 than the period until the output accepting signal from the output of the byte of command data section 4 A gaming machine according to any one of the above. 6. When a game ball wins in the winning area, a predetermined number
Is a gaming machine in which the prize balls are paid out to the player, Microcomputer As the predetermined condition is met
To the playerPayout of prize ballscontrolfor
MicrocomputerIncluded,The payout control microcomputer Is the typed
Claim that multiple mand data can be stored at the same timeFrom 1
In any one of Claim 5The game machine described.