JP3463695B2 - Imaging equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photographing device such as a video camera which is equipped with an image stabilizing device and an image enlarging device and which performs image processing using a field memory.

[0002]

2. Description of the Related Art In recent years, an image stabilization apparatus and an image enlarging apparatus using image processing, which have been attracting attention as a function of a video camera, require a field memory in order to perform image processing within one field. As an example thereof, a camera shake correction device disclosed in Japanese Patent Laid-Open No. 63-166370 will be shown below.

FIG. 5 is a block circuit diagram showing the overall structure of a camera shake correction device including a conventional field memory device. In the figure, 501 is a video signal input terminal and 502 is an A / D converter, which converts a video signal input to the video signal input terminal 501 into a digital signal. A field memory 503 stores the video signal converted into a digital signal by the A / D converter 502 for one field. 5
Reference numeral 04 is a motion vector detection circuit, which is an A / D converter 50.
2 outputs. A memory controller 505 controls the reading of the field memory 503 according to the output of the motion vector detection circuit 504. An interpolation enlargement circuit 506 interpolates and enlarges the video signal read from the memory 503. A D / A converter 507 converts the output signal of the interpolation circuit 506 into an analog signal and outputs it.

Next, the operation will be described. The video signal input to the video signal input terminal 501 is the A / D converter 50.
At 2, it is converted into a digital signal. The output of the A / D converter 502 is sent to the field memory 503 and the motion vector detection circuit 504, respectively. The motion vector detection circuit 504 detects the motion vector of the image for each field by a known representative point matching method, and outputs it to the memory controller 505.

The field memory 503 has an A / D
One field of the video signal output from the converter 502 is written. The memory controller 505 controls writing / reading of the field memory 503 according to the output of the motion vector detection circuit. Here, the field memory 50
When writing the output of the A / D converter 502 to 3, the whole screen for one field is written, but when reading this, a screen area smaller than the write screen is read and the read position is the motion vector detection circuit. It is changed according to the address output by 504. As a result, image blur can be reduced.

The principle will be described with reference to the drawings. FIG. 6 is a diagram showing the principle of image blur correction. In the figure, 601 is a screen written in the field memory 503 , 602a and 602b are screens read from the field memory 503 , and 603a and 603b are subjects in the screen. In a certain field, the subject 603a in the writing screen 601 moves to the position of 603b in the next field due to image shake, and the motion vector at that time is Δ.
If it is v, the subject in the read screen can be fixed at a fixed position by moving the read screen from the position of 602a to the position of 602b by Δv. By repeating the above operation for each field, continuous image blur included in the captured image can be removed. Therefore, the read address of the field memory 503 output from the memory controller 505 may be the initial value obtained by adding the integrated value ΣΔv of the motion vector from the start of the image blur correction operation. The video signal whose image blur has been corrected as described above is interpolated and enlarged by the interpolation enlargement circuit 506.
, The size of the input screen is interpolated / enlarged, and D / A
It is converted into an analog signal by the converter 507 and output.

By the way, if the video signal is always written into the field memory from the same address, the write address may catch up with the read address when the image is cut out. As a method of preventing this, there is a method of controlling the image memory device disclosed in Japanese Patent Laid-Open No. 2-109474.

That is, when the video signal read area of the first field written in the field memory is determined, the write start row address of the video signal of the subsequent second field is next to the read end row address of the first field. Set after the address of. In the row address control, the maximum row address and the minimum row address are handled as a continuous ring. For example, when using a field memory with row addresses 0 to 303,
A row address counter that is cleared to 0 when the count value reaches 303 may be used.

FIG. 7 is a timing chart of the row address control of the field memory in the conventional image stabilization apparatus. In the figure, the vertical axis represents the row address, the horizontal axis represents the time, the solid line represents the write row address, and the dotted line represents the read row address, and the vertical and horizontal half areas of the written image are read out. From the figure, it can be seen that this method can prevent the write row address and the read row address from conflicting with each other.

If the image stabilization apparatus as described above is incorporated in a video camera, stable shooting can be realized even in handheld shooting, which is convenient. Currently, the mainstream type of home video camera is a single-plate color video camera using a CCD image pickup device. A block circuit diagram showing an example of the overall configuration is shown in FIG. In the figure, 1 is a lens, which forms an optical image. A color separation filter 2 separates the optical image formed by the lens 1 into four types of color components. Reference numeral 3 is a CCD image pickup device, and the lens 1 forms an image,
The optical image separated for each color component by the color filter 2 is converted into an electric signal. An A / D converter 4 converts a video signal from the CCD solid-state image sensor into a digital signal.
Reference numeral 8 is an odd pixel latch circuit, which latches the data of the pixels in the odd columns output from the A / D converter 4. Reference numeral 9 is an even pixel latch circuit, which latches the data of the pixels in the even columns output from the A / D converter 4.

Reference numeral 10 denotes an adder which adds the data of the pixels in the odd-numbered columns output from the first odd-numbered pixel latch circuit 8 and the data of the pixels in the even-numbered columns output from the even-numbered pixel latch circuit 9 to obtain the luminance. Get the signal component. A subtraction circuit 11 subtracts the output signal of the even pixel latch circuit 9 from the output signal of the odd pixel latch circuit 8 to obtain a line-sequential color difference signal. A luminance signal latch circuit 12 latches the output signal of the adder 10. A color difference line sequential signal latch circuit 13 latches the output signal of the subtraction circuit 11 for two pixel periods. Reference numeral 14 denotes a 1H delay circuit, which delays the line-sequential color difference signal output from the subtractor 11 by one horizontal period. A color difference line sequential-simultaneous conversion circuit 15 includes a 2R-G selection switch 16 for selecting the first color difference signal 2R-G from the output signal of the color difference line sequential signal latch circuit 13 and the output signal of the 1H delay circuit 14. It is composed of a 2B-G selection switch 17 for selecting the second color difference signal 2B-G.

Reference numeral 21 is a first D / A converter, which converts the output signal of the luminance signal latch circuit 12 into an analog signal. A second D / A converter 22 converts the output signal of the 2R-G selection switch 16 of the color difference line sequential-simultaneous conversion circuit 15 into an analog signal. 23 is the third D / A
2B-G of the color difference line sequential-simultaneous conversion circuit 15 in the converter
The output signal of the selection switch 17 is converted into an analog signal. Reference numeral 824 is a reference signal generation circuit, which generates signals for controlling the CCD image sensor 3, the odd pixel latch circuit 8, the even pixel latch circuit 9, and the color difference line sequential-simultaneous conversion circuit 15. Reference numeral 31 denotes a CCD driver, which controls the operation of the CCD image pickup device 3 in accordance with the output signal of the reference signal generation circuit 24.

Next, the operation will be described. The optical image formed by the lens 1 is separated into four types of color components by the color separation filter 2. FIG. 9 is a diagram showing a filter configuration of a color separation filter of a conventional photographing device. The filter has a matrix structure corresponding to the arrangement of the photodiodes of the CCD image pickup device. The odd-row and odd-column filters are magenta transmission filters, and the odd-row and even-column filters are green transmission filters, and a multiple of 4-2 rows. , Odd-numbered filters are cyan transmission filters, multiples of 4-2 rows,
The filters in the even-numbered columns are yellow transmission filters and the filters in the multiples of four rows are odd-numbered filters, the yellow transmission filters are the filters in the odd-numbered columns, and the filters in the multiples-row even-numbered columns are the cyan transmission filters.

The optical image separated into four kinds of color components by the color separation filter 2 is converted into an electric signal by the CCD image pickup device. FIG. 10 is a diagram showing the structure of the CCD image pickup device. In the figure, reference numeral 1001 denotes a photodiode, which is two-dimensionally arranged in the vertical direction and the horizontal direction, and generates an electric charge according to the amount of light passing through the color separation filter 2. 1
002 is a vertical transfer CCD, which is a photodiode 100.
The charge generated by 1 is accumulated, and the charge is swept out in the vertical direction according to the vertical transfer clock from the CCD driver 31.
Reference numeral 1003 denotes a horizontal transfer CCD, which sweeps out the electric charges swept from the vertical transfer CCD by the vertical transfer clock in the horizontal direction according to the horizontal transfer clock from the CCD driver 31 and outputs it as a video signal.

In the CCD image pickup device 3, in the odd field, the charges of the 2n-1st row and the 2nth row (n = 1, 2, 3) are added to make one line of the video signal, and in the even field, the 2n row. The charges of the 2nd + 1th row and the charges of the 2nd + 1st row are added and read out as one line of the video signal. Here, since the filter arrangement of the color separation filter 2 is as shown in FIG. 9, the odd pixels in the odd lines in the odd field are magenta +.
Cyan, even pixels on odd lines are green + yellow,
Odd pixels in the even lines have magenta + yellow, and even pixels in the even lines have green + cyan. Similarly, odd line odd pixels in the even field are cyan +
Magenta, odd lines and even pixels are yellow + green,
Even line odd pixels have yellow + magenta color components, and even line even pixels have cyan + green color components.

The odd pixels of the video signal output from the solid-state image pickup device 3 are latched by the odd pixel latch circuit 8 and the even pixels are latched by the even pixel latch circuit 9, respectively. The adder 10 adds the odd pixel data output from the odd pixel latch circuit 8 and the even pixel data output from the even pixel latch circuit 9. At this time, the color components of the odd lines in the odd field are magenta + cyan + green + yellow,
This is 2R + 3G + 2B in RGB (red, green, blue) display, which corresponds to a luminance signal.

Further, the color components of the even-numbered lines also become magenta + yellow + green + cyan, and become a luminance signal. Similarly, even in the even field, both the odd line and the even line become luminance signals, and the output of the adder 10 becomes the luminance component of the video signal. The subtractor 11 subtracts the data of the even pixel output from the even pixel latch circuit 9 from the data of the odd pixel output from the odd pixel latch circuit 8. At this time, in the odd line of the odd field (magenta +
Cyan)-(green + yellow), which is 2B
-Corresponds to G. On the even-numbered line, (magenta + yellow)-(green + cyan) becomes 2R-G.

Similarly, (Cyan + Magenta)-(Yellow + Green) becomes 2B-G in the odd field of the even field and (Yellow + Magenta) -in the even line.
(Cyan + Green) gives 2R-G. Therefore,
In the output signal of the subtractor 11, two types of color difference signals appear alternately for each line.

Further, the output signal of the subtractor 11 passes through the color difference line sequential signal latch circuit 13 and the 1H delay circuit 14,
It is sent to the color line sequential-simultaneous conversion circuit 15. Also, 1H
Since the delay circuit 14 delays the output signal of the color difference line sequential signal latch circuit 13 by exactly one horizontal period, it outputs 2R-G for odd lines and 2B-G for even lines. In the color line sequential-simultaneous conversion circuit 15, the 2R-G selection switch 16 which alternately switches the output of the color difference line sequential signal latch circuit 13 and the output of the 1H delay circuit 14 for each line.
And 2B-G selection switch 17, 2R-G
The selection switch 16 outputs the output of the 1H delay circuit 14 on an odd line and the color difference line sequential signal latch circuit 13 on an even line.
Output is always selected and 2R-G is always output.

On the other hand, the 2B-G selection switch 17 selects the output of the color difference line sequential signal latch circuit 13 for odd lines and the output of the 1H delay circuit 14 for even lines,
Always output 2B-G. In this way, the color difference line-sequential-simultaneous conversion circuit 15 converts the color difference signals that appear line-sequentially into a simultaneous signal.

Further, the luminance signal output from the adder 10 is converted into an analog signal by the first D / A converter 21 via the luminance signal latch circuit 12, and similarly 2R.
The color difference signal 2R-G output by the -G selection switch 16 is output by the second D / A converter 22, and the color difference signal 2B-G output by the 2B-G selection switch is output by the third D / A converter 23. Converted to analog signal. The operation timing of the CCD image pickup device, the latch timing of the odd pixel latch circuit 8 and the even pixel latch circuit 9, and the switching timing of the color difference line sequential-simultaneous conversion circuit 15 are all controlled by the reference signal generation circuit 824. As above
The optical image formed by the lens 1 can be converted into a video signal.

[0022]

When the image stabilization device is combined with the single-panel color video camera as described above, the luminance signal and the color signal are combined rather than the field memory is provided at the luminance signal + color difference signal × 2. Has been converted to C
If a field memory is provided between the CD output and the luminance / color separation processing, the memory capacity can be reduced. However, in the image stabilization apparatus, due to the property of changing the read position in the field memory, the normal timing generated by the reference signal generation circuit in the odd pixel latch circuit 8, the even pixel latch circuit 9 and the color difference line sequential-simultaneous conversion circuit 15 is , Relationship with the color component of pixel data (hereinafter,
However, there is a problem that normal color processing cannot be performed.

The present invention has been made in order to solve the above problems, and when a camera shake device using image processing is combined with a color video camera using a single-plate type or two-plate type CCD image sensor, It is an object of the present invention to obtain an imaging device that can perform separation correctly.

[0024]

An image pickup apparatus according to the present invention has a storage capacity of one field or more of a luminance / color composite video signal from a CCD image pickup device, and its address configuration is an image in which a video signal constitutes a row address. On the vertical lines of the memory means, the column addresses corresponding to the horizontal pixels respectively, the write control means for controlling the writing of the video signal from the even addresses or the odd addresses of the memory means, and the memory means of the memory means. When read control means for controlling to read the video signal from an arbitrary address and luminance signal and chrominance signal are separated from the video signal of the memory means by arithmetic processing for each pixel, and the write address of the memory means is displayed in binary. And a luminance signal / color signal separating means for controlling the arithmetic processing according to the least significant bit.

Further, the luminance / color composite video signal from the CCD image pickup device is the luminance / color signal in the case of a color difference line sequential system in which two different color difference signals as color components alternately appear for each line. The output of the 1-line delay means for holding the color signal output by the separating means for one horizontal period and the output of the luminance signal / color signal separating means are selected based on the least significant bit of the read start row address of the memory means,
A sequential-simultaneous conversion means for simultaneously outputting the two kinds of color difference signals is provided.

Further, the write control means and the read control means operate so that the maximum value of the row address of the memory means becomes a continuous ring shape with the minimum value, and the read end of the first field read by the read control means is completed. The video signal of the continuous second field is written from the address subsequent to the column address.

[0027]

When the video signal is stored in the field memory, the photographing apparatus according to the present invention controls so that writing is always performed from either an odd address or an even address, and the least significant bit of the read start address is referred to when reading. , By making it possible to determine whether the read start address is an odd address or an even address, and controlling the operation of the brightness / color signal separating means based on this,
The color signal separating means can realize the operation according to the color phase.

When the luminance / color composite video signal from the CCD image pickup device is a color difference line-sequential system in which two different color difference signals alternately appear line by line as color components, the luminance signal / color signal separation means 1 line-sequential color difference signal to output
The line sequential color difference signal one line before, which is delayed by the line delay means, the output of the luminance signal / color signal separation means, and the above-mentioned 1
Start the reading of the field memory by controlling the operation of the color difference line sequential-simultaneous conversion means for selectively outputting the output signal of the line delay means for each color difference signal with reference to the least significant bit of the read start row address of the memory means. It is possible to realize the operation according to the change of the color phase due to the change of the row address.

Further, in order to prevent the conflict between the write address and the read address in the field memory, the write control means and the read control means are arranged in a ring shape in which the row address of the memory means is continuous with the maximum value being the minimum value. When the video signal of the second field consecutive from the address after the read end column address of the first field read by the read control means is written, the read end address is set to the read end row address. The write start row address also changes accordingly, but the write start address is always controlled to be an odd or even address, and the operation of the color difference line sequential-simultaneous conversion means is controlled with reference to the least significant bit of the read start row address. ,
It is possible to realize processing according to the vertical color phase of the video signal read from the field memory.

[0030]

EXAMPLES Example 1. FIG. 1 is a block diagram showing the overall configuration of a photographing apparatus according to an embodiment of the present invention. In the figure, 1 is a lens for forming an optical image. A color filter 2 divides the optical image formed by the lens 1 into four types of color components. Reference numeral 3 denotes a CCD solid-state image sensor, which converts an optical image formed by the lens m301 and separated into color components by the color filter 2 into an electric signal. An A / D converter 4 converts a video signal from the CCD solid-state image sensor into a digital signal. A field memory 5 writes and reads one field of the digitized video signal output from the A / D converter 4. A motion vector detection circuit 6 detects a motion vector for each field of an image formed by a video signal. A memory controller 7 controls writing in the field memory, and also controls reading of the field memory so as to correct image shake according to the detection output of the motion vector detection circuit 6. 8 is an odd pixel latch circuit,
Data of odd-numbered pixels in the output signal of the field memory 5 is latched. Reference numeral 9 is an even pixel latch circuit, which latches data of even pixels in the output signal of the field memory 5. An adder 10 adds the data of the odd pixels output from the odd pixel latch circuit 8 and the data of the even pixels output from the even pixel latch circuit 9.

Reference numeral 11 denotes a subtracter, which subtracts the data of the even pixel output from the even pixel latch circuit 9 from the data of the odd pixel output from the odd pixel latch circuit 8. A luminance signal latch circuit 12 latches the output signal of the adder 10 for two pixel periods. A color difference line sequential signal latch circuit 13 latches the output signal of the subtractor 11 for two pixel periods. 1
4 is a 1H delay circuit, which is a color difference line sequential signal latch circuit 1
The output of 3 is delayed by 1 horizontal period. Reference numeral 15 denotes a color difference line sequential-simultaneous conversion circuit, which includes a 2R-G selection switch 16 and a 2B-G selection switch 17 that selectively output the output signal of the color difference line sequential signal latch circuit 13 and the output signal of the 1H delay circuit 14. . Reference numeral 18 is a first electronic zoom circuit, which enlarges the signal output from the luminance signal latch circuit 12 by a predetermined magnification. A second electronic zoom circuit 19 enlarges the output signal of the 2R-G selection switch 16 of the color difference line sequential-simultaneous conversion circuit 15 by a predetermined magnification. Reference numeral 20 denotes a third electronic zoom circuit, which is a color difference line sequential-simultaneous conversion circuit 2B-
The output signal of the G selection switch 17 is enlarged by a predetermined magnification. Reference numeral 21 is a first D / A converter, which converts the output signal of the first electronic zoom circuit 18 into an analog signal. 22
Is a second D / A converter, and a second electronic zoom circuit 1
The output signal of 9 is converted into an analog signal.

A third D / A converter 23 converts the output signal of the third electronic zoom circuit 20 into an analog signal. Reference numeral 24 is a reference signal generating circuit, which is a CCD image pickup device 3, an odd pixel latch circuit 8, an even pixel latch circuit 9, a luminance signal latch circuit 12, and a color difference line sequential signal latch circuit 1.
3. Control operations of the color difference line sequential-simultaneous conversion circuit 15 and the like. Reference numeral 25 denotes a pixel selection control circuit, which selects the odd pixel latch enable signal and the even pixel latch enable signal generated by the reference signal generation circuit 24 according to the least significant bit of the read start column address output from the memory controller 7, It outputs to the enable terminals of the odd pixel latch circuit 8 and the even pixel latch circuit 9. Reference numeral 28 denotes a color difference signal selection control circuit, which switches the color difference signal selection signal generated by the reference signal generation circuit 24 between normal rotation and inversion according to the least significant bit of the read start row address output from the memory controller 7, and sequentially transfers the color difference lines simultaneously. Output to the conversion circuit 15.
Reference numeral 31 is a CCD driver, which generates a control signal for the CCD image pickup device 3 in accordance with an output signal from the reference signal generation circuit 24.

Next, the operation will be described. The optical image formed by the lens 1 is separated into four kinds of color components by the color separation filter 2. The filter array of the color separation filter 2 is the same as that shown in FIG. 9 in the conventional example. The optical image that has passed through the color separation filter 2 is converted into a video signal by the CCD image pickup device 3 and converted into a digital signal by the A / D converter 4. The processing up to this point is the same as in the conventional example.

The video signal converted into a digital signal by the A / D converter 4 is written in the field memory 5. The minimum row address of this field memory is 1, and the minimum column address is also 1. It is assumed that the field memory is written only during the vertical valid period of the video signal, and the row address to start writing is after the address next to the read end row address of the image of the previous field as shown in the conventional example. The memory controller 7 controls the write start address so that it is always an odd address.

That is, the write start row address is set as the read end row address + 2 when the read end row address is an odd number, and the read end row address + 1 when the read end row address is an even number, and writing is performed from the top line of the vertical effective line. go. In the horizontal address control, C
Writing is performed so that the first (first column) pixel of the video signal in each line from the CD image sensor becomes one column of the field memory. On the other hand, the read address of the field memory changes according to the motion vector of the entire image for each field detected by the motion vector detection circuit 6 as in the conventional example shown in FIG.

FIG. 2 shows an algorithm of motion vector calculation in the motion vector detection circuit 6 and the memory controller 7 and control of the field memory 5. Processes 201 and 202 represent processes performed when the power is turned on or immediately after the system is reset, and the initial value of the write start address of the field memory 5 is set to a predetermined address. Next, in process 203, the read and write control signals of the field memory are output (write control only in the initial state). Next, in process 204, the motion vector of the entire image in one field is calculated. Next, in process 205, the read start row address, column address and read end line address are calculated from the result of process 204 and the image recording address on the field memory. Next, the process 206 branches into two systems. That is, if the read end row address calculated by the process 205 is odd , the process branches to process 207, and if it is even , the process branches to process 208.

If the read end row address of the field memory is odd , the write start row address in the next field is determined to be a value obtained by adding 2 to the read end row address by the process 207, while the read end row address is even . In this case, the write start row address is determined to be a value obtained by adding +1 to the read end address by the process 208. Then, the process returns to the process 203, and the processes 203 to 207 or 208 are repeated for each field thereafter. Note that the processing 203 is performed immediately before each field effective area, and the processing 205 to 207 or 208 is performed.
Is performed during the vertical blanking period.

When there is no processing in the field memory 5 as in the conventional example shown in FIG. 8, the reference signal generation circuit 24 determines the color phase of the video signal reaching the odd pixel latch circuit 8 and the even pixel latch circuit 9. It was always constant with respect to various reference signals generated. However, in this embodiment, since the read address of the field memory changes according to the detection output of the motion vector detection circuit 6, the color phase of the video signal output from the field memory is different from that output from the CCD image sensor 3. Is different.

Therefore, normal processing cannot be performed in the odd pixel latch circuit 8, the even pixel latch circuit 9 and the color difference line sequential-simultaneous conversion circuit 15 which are controlled by the signal synchronized with the color phase of the video signal of the CCD image pickup device 3. . Since the color phase in the same field is determined only by whether the lines and pixels are odd or even, it is necessary to distinguish whether the target lines and pixels are odd or even for normal video signal processing. Good.

In this embodiment, since the write start row address and the write start column address are always odd addresses, it is possible to know whether the address is odd or even from the least significant bit of the address. Further, since the odd line of the video signal output from the CCD image pickup device 3 is written in the odd row address, the even line is written in the even address, the odd pixel is written in the odd column address, and the even pixel is written in the even column address, respectively. , The least significant bit of the address represents an odd / even number of lines and pixels of the video signal. Therefore, by referring to the least significant bit of the read start address, it is possible to know whether the first read line or pixel is an odd number or an even number when output from the CCD image sensor.

The video signal output from the field memory is separated into an odd pixel and an even pixel by the odd pixel latch circuit 8 and the even pixel latch circuit 9. The odd pixel latch circuit 8 and the even pixel latch circuit 9 are configured to latch the value of the input data D at the rising edge of the system clock when the rising edge of the system clock is "H". The output signals of the odd-numbered pixel latch circuit 8 and the even-numbered pixel latch circuit 9 are added to the luminance signal latch circuit 12 after being added by the adder 10, and then subtracted to the color difference line sequential signal latch circuit 13 after being subtracted by the subtractor 11. The reference signal generating circuit 24 is latched at a predetermined timing.

Therefore, even if the color phase of the output video signal of the field memory changes, the video signals for which the correct combination of addition and subtraction processing has been performed is input to the luminance signal latch circuit 12 and the color difference line sequential signal latch circuit 13. Must appear at a predetermined timing. In the present invention, this problem is solved by changing the phase of the latch enable signal of the odd pixel latch circuit 8 and the even pixel latch circuit 9 according to the read address of the field memory 5 by the pixel selection control circuit 25.

The pixel selection control circuit 25 selects a 2R-G selection switch 26 and a 2B-G selection switch 2 for selecting the two systems of latch enable signals output from the reference signal generation circuit 24.
It is composed of 7. Of the pixel latch enable signals from the reference signal generation circuit 24, the odd pixel latch enable signal in the conventional example is used as the first pixel latch enable signal, and the even pixel latch enable signal is used as the second pixel latch enable signal.

In the video signal recorded in the field memory 5, odd pixels are assigned to odd addresses. Therefore, since the color phase of the output video signal of the field memory having an odd read start column address is the same as that of the conventional example, the first pixel latch enable signal is set to enable the odd pixel latch circuit and the second pixel latch enable is set. The signal may be connected to the enable of the even pixel latch circuit, respectively.

On the other hand, when the read start column address is an even address, the color phase of the output video signal of the field memory is the inversion of the conventional example, so the first pixel latch enable signal is set to enable the even pixel latch circuit. The second pixel latch enable signal may be connected to the enable of the odd pixel latch circuit, respectively.

FIG. 3 is a timing chart when the video signal is read from the odd column address of the field memory in FIG. FIG. 3A is a timing chart when the read start column address is an odd number, and FIG.
(B) is a timing chart when the read start column address is an even number. Inverting the phases of the odd pixel latch enable signal and the even pixel latch enable signal in accordance with the change of the color phase so that a correct combination of signals appears at the outputs of the luminance signal latch circuit 12 and the color difference line sequential signal latch circuit 13. I understand.

Further, the output signal of the color difference line sequential signal latch circuit 13 is converted from the line sequential signal to the simultaneous signal by the 1H delay circuit 14 and the color difference line sequential-simultaneous conversion circuit 15. At this time, the color difference line 2R-G of the color difference line sequential-simultaneous conversion circuit 15 is so arranged that the color difference signal 2R-G and the color difference signal 2B-G always appear at the output of the 2R-G selection switch 16 and the 2B-G selection switch 17, respectively. The switching timing of the selection switch 16 and the 2B-G selection switch 17 is also changed according to the read start row address.

That is, if the read start row address is an odd number, the color phase in the vertical direction is the same as that of the conventional example shown in FIG. 4, and therefore the color difference line sequential-simultaneous conversion is performed by the line selection signal from the reference signal generation circuit 24. Controls the circuit 15, and if the read start row address is an even number, the reference signal generation circuit 2
The color-difference line-sequential-simultaneous conversion circuit 15 is controlled by a signal obtained by inverting the line selection signal from 4.

The color difference signal selection control circuit 28 includes an inverter for inverting the logic of the line selection signal from the reference signal generation circuit 24, and the reference when the least significant bit of the read start row address output from the memory controller 7 is "H". The line selection signal from the signal generation circuit 24 is selected and output, and when the least significant bit of the read start row address is "L", it is composed of a logic selection switch that selects the output of the inverter, and realizes the above operation. is doing.

The output signal of the luminance signal latch circuit 12 is enlarged to the original screen size by the first electronic zoom circuit 18, and converted into an analog signal by the first D / A converter. Further, the output signals of the 2R-G selection switch 16 and the 2B-G selection switch 17 of the color difference line sequential-simultaneous conversion circuit 15 are output to the original screen size by the second electronic zoom circuit 19 and the third electronic zoom circuit 20, respectively. And is converted into an analog signal by the second D / A converter 22 and the third D / A converter.

The filter arrangement of the color separation filters is not limited to that shown in FIG. 3, and another combination may be used.

Further, in the first embodiment, both the write start row address and the write start column address are odd addresses, but they may be even addresses.

In the first embodiment, the single-plate color video camera has been described, but the present invention can be applied to a two-plate color video camera or the like which requires similar pixel calculation.

[0054]

Since the photographing apparatus of the present invention is configured as described above, it has the following effects.

When the video signal is written in the field memory, the odd-numbered or even-numbered address is controlled to always be written, so that if the least significant bit of the read-start address is referred to at the time of reading, whether the read-start address is an even address or not By making it possible to determine whether the address is an odd number and controlling the operation of the luminance signal / color signal separation means based on this, correct arithmetic processing can be performed even if the color phase changes due to the image cutting operation in the field memory. Can be done.

Further, when the color signal component of the output signal of the CCD image pickup device is a color difference line sequential system in which two different color difference signals appear alternately, the color difference signal output from the luminance signal / color signal separating means is set to one horizontal line. Color-difference line-sequential for simultaneously synchronizing color-difference signals by selecting a 1-line delay means for delaying a period, an output of a luminance signal / color signal separation means and an output of a 1-line delay means-
By controlling the selection operation of the simultaneous conversion means with the least significant bit of the read start row address of the field memory as a reference, even if the vertical color phase changes according to the read start row address in the field memory, color difference line sequential-simultaneous A conversion process can be performed.

Further, the write control means and the read control means operate so that the row address of the memory means becomes a ring shape in which the maximum value is continuous with the minimum value, and the read control means reads the first field. In the system that prevents the read address and the write address from conflicting by writing the video signal of the continuous second field from the address subsequent to the end row address, the vertical change is caused by the change of the write row address. Even if the color phase changes, the color difference line sequential-simultaneous conversion processing can be correctly performed.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an overall configuration of an image pickup apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an algorithm of processing in the motion vector detection circuit and memory controller of FIG.

FIG. 3 is a timing chart when a video signal is read from an odd column address of the field memory in FIG.

4 is a timing chart when a video signal is read from an even column address of the field memory in FIG.

FIG. 5 is a block circuit diagram showing an overall configuration of a camera shake correction device including a conventional field memory device.

FIG. 6 is a diagram showing the principle of image shake correction.

FIG. 7 is a timing chart of row address control of the field memory in the conventional camera shake correction device.

FIG. 8 is a block circuit diagram showing an overall configuration of an image pickup apparatus using a conventional CCD image pickup element.

FIG. 9 is a diagram showing a filter configuration of a color separation filter of a conventional photographing device.

FIG. 10 is a diagram showing a configuration of a CCD image pickup device.

[Explanation of symbols]

1 lens Two-color separation filter 3 CCD image sensor 4 A / D converter 5 field memory 6 Motion vector detection circuit 7 Memory controller 8 Odd pixel latch circuit 9 Even pixel latch circuit 10 adder 11 Subtractor 12 Luminance signal latch circuit 13 Color difference signal latch circuit 14 1H delay circuit 15 color difference line sequential-simultaneous conversion circuit 16 2R-G selection switch 17 2B-G selection switch 18 First electronic zoom circuit 19 Second electronic zoom circuit 20 Third electronic zoom circuit 21 First D / A converter 22 Second D / A converter 23 Third D / A converter 24 Reference signal generation circuit 25 pixel selection control circuit 26 First switch 27 Second switch 28 Color difference signal selection control circuit 29 inverter 30 Logic selection switch 31 CCD driver

Continuation of front page (56) Reference JP-A-4-92589 (JP, A) JP-A-6-14340 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 9 / 07

Claims (3)

(57) [Claims] 1. A luminance / color composite video signal from a CCD image pickup device has a storage capacity of one field or more, and its address configuration is such that a row address is a vertical line of an image formed by the video signal and a column address is a horizontal direction. Memory means respectively associated with the pixels, write control means for controlling the video signal to be written from an even address or odd address of the memory means, and read control for controlling a video signal to be read from an arbitrary address of the memory means. The luminance signal and the chrominance signal are separated from the control means and the video signal of the memory means by the arithmetic processing for each pixel, and the arithmetic processing is performed by the least significant bit when the read row address or the column address of the memory means is displayed in binary. An image pickup apparatus, comprising: a luminance signal / color signal separation means for controlling the. 2. The luminance / color composite video signal from the CCD image pickup device is a color-difference line-sequential system in which two different color-difference signals as color components appear alternately on a line-by-line basis. The 1-line delay means for holding the color signal output by the above-mentioned 1-horizontal period, the output of the luminance signal / color signal separation means and the output signal of the 1-line delay means are stored in the least significant bit of the read start row address of the memory means. The photographing apparatus according to claim 1, further comprising: a sequential-simultaneous conversion unit that is selected as a reference and outputs the two types of color difference signals simultaneously. 3. The write control means and the read control means operate so that the row address of the memory means has a ring shape in which the maximum value and the minimum value are continuous, and the read control means reads the first field. 2. The image pickup apparatus according to claim 1, wherein the image pickup apparatus operates so as to write a video signal of a continuous second field from an address subsequent to the end column address.