JP3464670B2 - Notification method during reception isolation - Google Patents

Description

Detailed Description of the Invention

[Summary] [0002] Regarding a reception isolation notification method in which a reception isolation notification for a command is sent by an error answer, a conventional inter-bus interface is utilized, unnecessary processing time is eliminated, and flexibility in system design is provided. An unconditional determination of whether or not a processor connected to the first time-split bus or the second time-split bus is in reception isolation for the purpose of achieving the assignment, or the processor. The judgment circuit determines whether the command received in step 5 is a command that allows continued reception isolation or a request to cancel reception isolation, and the error answer return circuit is activated according to the output of the judgment circuit. Occasionally, the error answer output from the error answer return circuit may be added to the reception isolator. When an error answer code with the error indication information is set and the error answer is sent back to the processor that has accessed the processor in reception isolation, or when the judgment circuit outputs the command recognition output of the request to cancel the reception isolation It was configured to cause the initial settings of the processor during receive isolation.

[0002]

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a reception isolation notification method for performing reception isolation notification of a command with an error answer. Some digital switching systems are composed of multiprocessor systems. In the multiprocessor system, there is a system operation state in which a certain processor operates in an operation state (reception isolation) in which a command from another processor is not received.
Therefore, the receive isolation state needs to be known to other processors in the system in order to continue normal operation of the system. This is because if the recognition that the reception isolation is being performed is given only to the fault monitoring processor that manages the reception isolation, the following inconvenience occurs. The inconvenience is that even in the state where the reception isolation as described above occurs, a processor other than the fault monitoring processor in the system can access the processor in the reception isolation. Because it has become. Therefore, when such an access occurs, the fault monitoring processor will detect a non-responsive state that has occurred between the accessing processor in the system and the processor in the reception isolation. For that reason, the failure monitoring processor must analyze the non-response state.

[0003]

[Prior art]

FIG. 9 shows a system bus 100 having a plurality of processors 102 _0.
1 to 102 _N are connected to each other to show a multiprocessor system. Each processor 102 _i (i = 0,1,2, ..., N)
Transfer data to each other via the system bus 100. In order to prevent mutual interference in the data transfer, the processor operating with reception isolation as described above sets a reception isolation flag in its own processor and prohibits data reception from other processors. I am collecting. As a control method of the system bus 100 used for data transmission and reception as described above, there are an interlock type and a clock synchronous time split type. 104 is a bus sequence monitoring timer.

Even if data transmission / reception as described above is started with respect to a processor in reception isolation (10th
In the figure, A represents a write address transmitted from a data transmission source, WT represents a write instruction signal, and D represents data. ), If the sequence bus control method is of the interlock type as described above, no data is received by the processor in the reception isolation,
Therefore, the response on the data transmission / reception bus sequence is not returned from the processor in the reception isolation to the data transmission source processor (see ACK in FIG. 10). As a result, a no answer is detected by the bus sequence monitoring timer 104 (see timer overflow in FIG. 10), and one of the fault monitoring processors in the sequence (processors 102 _i other than the processor performing the data transmission / reception). One or several processors). In the fault monitoring processor that received this notification,
After isolating the no answer / bus sequence abnormality,
Take corrective action for the no answer / bus sequence abnormality. This method not only takes time until detection, but also puts a wasteful processing load on the fault monitoring processor.

Further, when the bus control system of the bus 100 used for transmitting and receiving the command as described above is of the clock synchronous time split type, when the command is received by the receiving processor, the reception Processor (CP in Figure 11
U _j ) is in reception isolation, and the response signal in the bus sequence (see SC in FIG. 11) is sent to the command source via the status line (in the system bus in FIG. 9). It is returned to the processor (CPU _{i in} Figure 11).
The command source processor receiving this response signal knows that the destination is in reception isolation.

[0006]

[Problems to be Solved by the Invention]

In the conventional receiving isolation notification method as described above when a processor that becomes reception isolation occurs in the system, no matter which format the bus control method takes, notification is made using a part of the bus sequence. However, even if the conventional reception isolation notification method is simply adopted in a multi-layer system bus (see FIG. 12), it is provided between the multi-layer busses. The above-mentioned reception isolation cannot be recognized only by the normal bus interface portion that is provided, and a processor for receiving the reception isolation display information from the processor that is in the reception isolation to the processor connected to another hierarchical bus. A special hardware circuit as shown in FIG. 13 is provided in the system bus interface circuit 110. This special hardware circuit is composed of transmission / reception buffers 114 and 116, reception buffer 118, reception isolation decoder 120, and error packet generation circuit 122. The error packet generation circuit 122 is a circuit that interprets a response signal received from the status line in the system bus 100 and generates an error packet. The error packet is sent to the upper system bus 124 via the transmission / reception buffer 116 or the individual line 112. Therefore, not only is it disadvantageous in terms of hardware, but it also affects the control of data transfer between the upper system bus 124 and the system bus 100.

The present invention was created in view of such problems,
It is an object of the present invention to provide a notification system during reception isolation which can eliminate wasteful processing time and give flexibility to system design while utilizing the conventional bus-to-bus interface.

[0008]

[Means for Solving the Problems]

FIG. 1 shows a block diagram of the principle of the present invention. As shown in this figure, the first aspect of the present invention is arranged between the first time-split type bus and the second time-split type bus 4. Two
Command passing circuit 6 having an error answer sending circuit for sending a command etc. to the second time split type bus 4 and sending an error answer to the second time split type bus, and the second time split type bus Bus 4 to the first time-split bus 2
A second command etc. passing circuit 8 for passing a command etc. to the second command etc. passing circuit 8 when the processor connected to the first time split type bus 2 is in reception isolation. In the case where it is determined that the received command is a command to stop the execution of the processor, a determination signal is output, and the first command etc. passing circuit 6 is activated in response to the determination signal. The error answer output circuit 10 has a reception isolation display setting circuit 15 for setting an answer code having reception isolation display information in the error answer output from the error answer return circuit 10. The error answer output from the display set circuit 15 is transmitted to the first target during the reception isolation. So as to return to the second time split type processor connected to a bus 4 that without access to the processor of the connection to arm split type bus 2, constructed.

A second aspect of the present invention is provided between the first time-split bus 2 and the second time-split bus 4 so that the first time-split bus 2 can be connected to the second time. A first command etc. passing circuit 6 having an error answer sending circuit for sending a command etc. to the split type bus 4 and sending an error answer to the second time split type bus, and the second time split type bus 4 From the first time-split type bus 2 to the first time-split type bus 2. The second command-like passing circuit 8 is connected to the first time-split type bus 2. If the processor determines that it has received a command that must be executed even during reception isolation, the first time It is configured by passing commands and the like to the plit type bus 2.

[0010]

[Action]

The processor connected to the second time split type bus 4 is connected to the first time split type bus 2.
When an access is made to a processor in reception isolation, it indicates that the command related to the access allows the processor in the reception isolation to continue its operation only on the condition. When it is, the answer code having the reception isolation display information is set in the error answer output from the error answer return circuit 10 activated in response to the determination output, and the error answer is in the reception isolation. Return to the processor that made the access to the processor.

When the error answer return circuit 10 is activated in response to the first decision output of the decision circuit 13, the error code output from the error answer return circuit 10 includes an answer code having reception isolation display information. A second circuit which is set by the reception isolation display setting circuit 15 and which has accessed its error answer to the processor connected to the first time-split type bus 2 in the reception isolation.
When the judgment circuit 13 outputs the second judgment output, the time-split bus 4 connected to the time-split bus 2 is connected to the first time-split bus 2 in the reception isolation. Brings up the initial settings of the processor.

[0012] Therefore, without providing the hardware dedicated to the notification during reception isolation and without causing the fault monitoring processor to perform useless processing, the processor during reception isolation can be utilized by utilizing the existing system resources. Receive isolation notification may be achieved for the accessing processor. In addition, a control system that sends a reception isolation notification to a processor that has accessed the reception isolation processor, and the reception isolation processor, even if the reception isolation processor is in the reception isolation, On the other hand, since the control system that causes the release of the reception isolation is integrally formed in the system, flexibility can be added to the system design.

[0013]

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described with reference to FIGS. 2 and 3. FIG. 2 shows the system components occupied in the digital switching system by the embodiment of the present invention shown in FIG. FIG. 2 is a system interface device (AD) for connecting the upper system bus 124 and the system bus 100.
P) board 50, in which the system bus interface circuits 52, 54, local bus 101, and microprocessor (μP) 56 are shown as its constituent elements, and the detailed structure of the system interface device (ADP) of the present invention is shown. Only the system bus side of the element is shown in FIG.

In FIG. 3, the following components are the local bus 10
It constitutes a circuit system that transfers data from 1 to the system bus 100. 20R and 22R are reception buffers, and 20S and 22S are transmission buffers. The reception buffer 20R, the transmission buffer 20S, and the answer generation circuit 21 are connected to the local bus 101.
The reception buffer 22R and the transmission buffer 22S are connected to the system bus 100. The reception control circuit 23R is
Control the reception buffer 20R, the transmission control circuit 23S,
It controls the transmission buffer 20S.

The data in the reception buffer 20R is written in the transmission queue storage memory 25S via the selector 24-1 and the selector 24-2. The selector 24-1 outputs the data (data other than the error answer code) of the reception buffer 20R or the answer creating circuit 21 according to the selection control signal on the selection control line 24S. The selector 24-2 outputs the error answer code from the selector 24-1 or the error answer code output circuit 26 according to the output signal of the AND circuit 27. The transmission queue write control circuit 28SW, the flip-flop circuit 29S, and the transmission queue read control circuit 28SR configure a write / read control circuit of the transmission queue storage memory 25S. The transmission queue write control circuit 28SW and the transmission queue read control circuit 28SR are controlled by the microprocessor 56 described above. The data read from the transmission queue storage memory 25S is sent to the system bus 100 via the transmission buffer 22S.

The following components make up a circuit system that transfers data from the system bus 100 to the local bus 101. Reception buffer 22R, reception queue storage memory 25R, transmission buffer 20S, and reception queue read control circuit 28RW,
The flip-flop circuit 29R and the reception queue read control circuit 28RR correspond to the reception buffer 20R, the transmission queue storage memory 25S, the transmission buffer 22S, and the transmission queue write control circuit 28SW, the flip-flop circuit 29S, and the transmission queue read control circuit 28SR, respectively. . Transmission control circuit 23
S controls data transmission from the transmission buffer 20S to the local bus 101.

First reception buffer 32, reception isolation determination circuit
The 34, the flip-flop circuit 35, the AND circuit 36, and the transmission buffer 22S are the above-mentioned constituent elements, that is, the AND circuit 2.
7, the OR circuit 37, the error answer code output circuit 26, and the selector 24-2 constitute a characteristic part of the present invention. The first reception buffer 32 and the reception isolation determination circuit 34 receive the output data of the reception buffer 22R, and the reception isolation determination circuit 34 also receives the output data of the first reception buffer 32. Reception isolation determination circuit 34
Also receives a receive isolation designation signal from the microprocessor 56. The determination output of the reception isolation determination circuit 34 is supplied to the set input of the flip-flop circuit 35. The set output of the flip-flop circuit 35 is supplied to the AND circuits 27 and 36 together with the output of the flip-flop circuit 29R. The output of the AND circuit 27 is
The AND circuit 36 is supplied to the selector 24-2.
Is supplied to the transmission control circuit 23S and the OR circuit 37, and the local bus request signal to the microprocessor 56.
Supplied as REQ.

FIG. 4 shows a lower system configuration for implementing the present invention. In FIG. 4, 53 ₁ , ..., 53 _N (corresponding to CPU in FIG. 2 to CPU _N ) are CPU boards, 55 is a bus interface circuit (BiF), 58 is a decoder, 59 is a microprocessor, and 60 is a flip-flop circuit. In this figure, reference numerals 55, 58, 59 and 60 are not given the subscripts 0 to N.

Further, FIG. 5 shows a reception isolation canceling system in each CPU in FIG.
Reference numeral 76 represents a latch circuit. These latch circuits use the address strobe signal AS and the data strobe signal shown in the figure.
The address signal AD and the data signal DT are latched S by DS (see FIG. 6). The decoder 74 decodes the outputs of the latch circuits 70 and 72. The decoded output is set in the latch circuit 76 by the response signal ACK (see FIG. 6). The output of the latch circuit 76 is supplied to the microprocessor 56 and the flip-flop circuit 60.

2 to 5, the host system bus 124 or the system bus 100 corresponds to the first time split type bus 2 in FIG. 1, and the system bus 100 or the host system bus 124 is It corresponds to the second time-split type bus 4 in FIG. System bus interface circuit 52,
Alternatively, the system bus interface circuit 54 corresponds to the first command etc. passing circuit 6 in FIG. 1, and corresponds to the system bus interface circuit 54, the microprocessor 56, or the system bus interface circuit 52, the microprocessor 5.
Reference numeral 6 corresponds to the second command transfer circuit 8 in FIG. Answer creating circuit 21, selector 24-1, transmission queue storing memory 25S, transmission queue writing control circuit 28SW,
The flip-flop circuit 29S, the transmission queue read control circuit 28SR, and the transmission buffer 22S correspond to the error answer return circuit 10 in FIG. The first reception buffer 32 and the reception isolation determination circuit 34 correspond to the determination circuit 13, and include a flip-flop circuit 35, AND circuits 27 and 36, and an inverter 27.
1, the OR circuit 37, the selector 24-2, and the error answer code output circuit 26 correspond to the reception isolation display set circuit 15 of FIG.

The operation of the embodiment of the present invention having the above configuration will be described below. System bus 100 to local bus 101 in FIG.
Data transfer control itself to or from the local bus 101 to the system bus 100 is performed under a conventional method.

The CPU shown in FIG. Will be described as a master, and an operation example of the embodiment of the present invention under a system operating state in which the CPU _N is set to the reception isolation state will be described. The setting of the CPU _{N to} the reception isolation state is, for example, CPU. By CPU
_This is done by sending a diagnostic command to _N. CP
U. The diagnostic command sent from the system bus 100,
It is received by the microprocessor 59 via the bus interface circuit 55 and the local bus 103 and is interpreted there. A set signal is output from the microprocessor 59,
The flip-flop circuit 60 is set by this set signal. The output of this flip-flop circuit 60 is the third
The reception isolation designation signal in the figure is supplied to the system bus interface circuit (ADP) 54 (see FIG. 2) via the bus interface circuit 55 and the system bus 100.

In such an operating state of the system, the CPU ₀ (not shown) connected to the upper system bus 124 (reference instead of the system bus 100; the same applies hereinafter) is the CPU under diagnosis. _{When a} command is sent to _N , the reception buffer 22R determines whether or not the command is addressed to its own CPU in the same manner as in the conventional method. This is because the command and password received from the host system bus 124 and the information (see FIG. 8) following this command are addressed to the CPU _N under diagnosis. If the judgment indicates that the command is addressed to the own CPU, the command is sent to the first receive buffer 32.
And notifies that the CPU _N is in reception isolation to the CPU _{0 as} follows. The command transferred from the CPU ₀ is followed by, for example, 4-byte sequence information as shown in FIG.

The reception isolation determination circuit 34 includes a reception buffer 22.
In response to the information from the R and the first reception buffer 32 and the reception isolation designating signal from the microprocessor 56, it is judged whether or not the error return of the reception isolation is necessary, and it is necessary as follows. Then, the flip-flop circuit 35 is set. In the set of the flip-flop circuit 35, the command fetched in the reception buffer 22R is
This is done when it is not desired to perform the process during reception isolation. This allows the AND circuit
The local bus request signal REQ is not generated from 36. The signal REQ is supplied to the OR circuit 37 via the inverter 271. This signal is also passed through the OR circuit 37 as a signal similar to the bus error which may occur normally, and the answer generation circuit 21
Is supplied to. Answering circuit that receives this signal
21 sends an error answer on line 21A and also sends line 2
Send a selection control signal on 4S.

In parallel with this processing, the command and the information transferred subsequently thereto are received and read by the read control circuit 28RW.
Receive queue storage memory 25R under the conventional method of controlling
When the reading is completed, the flip-flop circuit 29R is set and the reception is completed. Upon completion of this reception, the error answer code selection signal IRQ is sent from the AND circuit 27. This signal IRQ is also supplied to the receive buffer 20R and the microprocessor 56. As a result, the reception buffer 20R enters a state of waiting for access to the above-mentioned local bus request signal REQ, and the transmission queue write control circuit 28SW enters a state of writing the error answer described below.

Therefore, in the selector 24-2, the error answer in which the error answer code output from the error answer code output circuit 26 is inserted is transmitted to the transmission queue storage memory 25.
Transmission buffer 22S therefrom sent as transmission Kiyu into S and the CPU via the host system bus 124, ₀
Sent to. From the error answer code of the error answer, the CPU ₀ can know that the CPU _{N that} is the partner of the transmission and reception is in the reception isolation. The structure of the error answer and the error answer code is as follows.
Shown in the figure. The shaded area in the error answer code is an area for displaying the presence or absence of reception isolation.

Further, as described above, the command and password received from the host system bus 124, and the information (see FIG. 8) following this command indicate that they are addressed to the CPU _N under diagnosis. If it is determined that the command is desired to be processed even if the CPU _N is under diagnosis, the reception isolation determination circuit 34 outputs the flip-flop circuit 35. The signal to set is not generated. Therefore, the AND circuit 36 generates the local bus request signal REQ.

By the local bus request signal REQ, even if the CPU _N is under diagnosis, the diagnosis is canceled and the CPU _N is initialized as follows to process the entire system. Incorporated into action. CPU under diagnosis
The reason why the reception isolation cancellation is required is that the normal operation of the reception isolation only hinders the operation of the system. As an example, there is a case where a processing abnormality is detected even during processing operation in a system that is degenerated by a plurality of CPUs other than the CPU under diagnosis, and in this case the system is reconstructed. From the master, and because the garbled signal to be transferred rather than the reception isolation setting as described above from the master, gave the operating CPU a similar operating state to the operating CPU. It also results from having to release the CPU.

The above-mentioned local bus request signal REQ is transmitted to the transmission control circuit 23S.
Supplied to a local bus enable signal from a bus arbiter (not shown), which acts to cause the transfer buffer 20S to perform normal transfer control, while being sent to the local bus 101. Read from the receive queue storage memory 25R by the receive queue read control circuit 28RR which is stored in the receive queue storage memory 25R as the receive queue and has started its operation under the control of the microprocessor 56 which received the local bus request signal REQ. The password issued is the latch circuit 7
The address set to 2 and read from the reception queue storage memory 25R is set to the latch circuit 70. The decoder 74 receiving both of them outputs a signal indicating it, that is, a reception isolation cancellation signal. The CPU _N is reset (initialized) by this reception isolation cancellation signal, and the flip-flop circuit 60 is also reset. As a result, reception of the information (command, etc.) read from the reception queue storage memory 25R following the command, password, and address, that is, the process of incorporating the information into the processing operation of the entire system of the CPU _N described above is performed. Will be done.

The configuration of the present invention includes a control system that sends a notification during reception isolation to the CPU that has accessed the CPU during reception isolation, and a CP during reception isolation.
Even if the U is in the reception isolation, it provides a means by which a control system for causing the CPU to cancel the reception isolation during the reception isolation can be integrated in the system. Therefore, flexibility can be added to the system design.

This reception isolation canceling system is also the above-mentioned CPU.
It is also used to cancel the reception isolation from. The 4-byte sequence for that is the same as the 4-byte sequence for performing normal reception isolation cancellation. In addition, although the above-mentioned embodiment is an embodiment of a system having a multi-layer bus structure, the present invention can be implemented in a system composed of a single time-split type bus. It will be apparent to those skilled in the art from the description.

[0032]

【The invention's effect】

As is clear from the above description, according to the present invention, existing system resources can be provided without providing dedicated hardware for reception isolation notification and without causing the master CPU (processor) to perform unnecessary processing. , The notification during reception isolation can be achieved for the CPU that has accessed the CPU during reception isolation. Also, the CPU that accessed the CPU during reception isolation
To the control system that sends a reception isolation notification to the CPU and the reception isolation CPU, even if the reception isolation is in progress, causes the reception isolation CPU to cancel the reception isolation. Since the control system and the means for constructing the system can be integrated into the system, flexibility can be given to the system design.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a diagram showing a main part of a system implementing the present invention, FIG. 3 is a diagram showing an embodiment of the present invention, and FIG. 4 is implementing the present invention. Lower system configuration diagram, FIG. 5 is a diagram showing a reception isolation canceling system in each CPU in FIG. 4, FIG. 6 is a diagram showing a signal sequence on a local bus in each CPU in FIG. 4, FIG. FIG. 8 is a diagram showing a command and error answer format, FIG. 8 is a diagram showing a command sequence sent to the CPU under diagnosis in the embodiment of the present invention, and FIG. 9 is a block diagram of a multiprocessor system, FIG. 10 is a diagram showing one conventional reception isolation notification system, FIG. 11 is a diagram showing another conventional reception isolation notification system, and FIG. 12 is a reception isolator in a conventional multi-layer bus configuration system. Ration Shows a notification method, FIG. 13 is a diagram showing a configuration of a system bus interface circuit used in the receiver isolation in the notification system shown in FIG. 12.

[Explanation of symbols]

In FIGS. 1 to 5, 2 is a first time split type bus (upper system bus).
124, or system bus 100), 4 is the second time split type bus 4 (system bus 10)
0, or higher system bus 124), 6 is a first command transfer circuit (system bus interface circuit 52, or system bus interface circuit 54), 8 is a second command transfer circuit (system bus interface circuit 54, micro) Processor 56, or system bus interface circuit 52, microprocessor 5
6) and 10 are error answer return circuits (answer creation circuit 21, selector 24-1, transmission queue storage memory 25S, transmission queue write control circuit 28SW, flip-flop circuit 29S, transmission queue read control circuit 28SR, transmission buffer 22S), 13 is a determination circuit (first reception buffer 32, reception isolation determination circuit 34), 15 is a reception isolation display set circuit (flip-flop circuit 35, AND circuits 27, 36, inverter 271, OR circuit 37, selector 24-2 The error answer code output circuit 26).

Front page continuation (72) Inventor Hisamitsu Tanihira 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (72) Inventor Shuji Miki 1-6, Uchiyuki-cho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Katsuyuki Okada 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Within Nippon Telegraph and Telephone Corporation (56) References JP-A-54-70742 (JP, A) JP-A-63-308660 (JP, A) ) Japanese Patent Laid-Open No. 2-101567 (JP, A) Yoshiaki Wakimura et al., Development of high-performance system bus configuration technology, NTT Technology Journal, Japan, June 1, 1990, Vol. 2 No. 6, p. 81-84 (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 15/16-15/177 G06F 13/00 G06F 13/20-13/378 H04L 12/00-12/66

Claims (2)

(57) [Claims] 1. A command or the like is provided from the first time-split type bus to the second time-split type bus by being interposed between a first time-split type bus and a second time-split type bus. A first command etc. passing circuit having an error answer sending circuit for sending an error answer to the second time split type bus, and a command from the second time split type bus to the first time split type bus And a second command etc. passing circuit, the second command etc. passing circuit receives the command while the processor connected to the first time split type bus is in the reception isolation. Is determined to be a command for stopping the execution of the processor, a determination signal is output and the first command is output. The command transfer circuit has a reception isolation display set circuit that sets an answer code having reception isolation display information to the error answer output from the error answer return circuit activated in response to the determination signal, The first command etc. passing circuit makes access to the processor connected to the first time-split type bus in the reception isolation by using the error answer output from the reception isolation display set circuit. A notification method during reception isolation, characterized in that the notification is sent back to the processor connected to the time split type bus No. 2. 2. A command or the like is provided from the first time-split type bus to the second time-split type bus by being interposed between the first time-split type bus and the second time-split type bus. A first command etc. passing circuit having an error answer sending circuit for sending an error answer to the second time split type bus while passing
And a second command etc. passing circuit for passing a command etc. from the second time split type bus to the first time split type bus, wherein the second command etc. passing circuit is the first time split. If the processor connected to the type bus receives a command that must be executed even during reception isolation, the command is passed to the first time split type bus. Receive isolation notification method.