JP3465014B2 - Package insertion board and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package-inserted substrate and a method for manufacturing the same, and more particularly, to an integrated circuit chip such as a BGA (ball grid array) package or a CSP, which is sealed in a state of being connected to the substrate. The present invention relates to a structure of a package insertion board suitable for forming a packaged semiconductor product.

[0002]

2. Description of the Related Art Conventional BGA (ball grid array)
In a semiconductor integrated circuit package of a type, an integrated circuit chip made of a silicon semiconductor or the like is connected to a wiring pattern formed on a synthetic resin or ceramic substrate or film (hereinafter simply referred to as "interposing substrate"). Then, if necessary, appropriate resin sealing (resin molding) is performed. A plurality of terminal bonding pads arranged in a grid pattern are formed on the wiring pattern of the insertion board, and solder balls are bonded to these terminal bonding pads to form protruding electrodes. Such a ball grid array type integrated circuit package can easily support a multi-input / output structure or a high-density electrode structure due to its grid-like electrode arrangement, and can be mounted in a mounting process by being provided with protruding electrodes. Since the yield can be remarkably improved, it is attracting attention as an effective method for reducing the total mounting cost in an integrated circuit package having a high degree of integration. This type of integrated circuit package includes a printed circuit board-like interposer that is relatively larger than the chip size of the integrated circuit chip, and thus has a small area or a film-like shape called CSP, which is approximately the same size as the chip size. Even those having an interposer substrate have been proposed.

[0003]

However, among the protruding electrodes provided in the above-mentioned BGA type integrated circuit package, a conductor such as a solder ball is formed on the terminal bonding pad and bonded. The protruding electrode may be, for example, when stress is applied from the side of the protruding shape due to insufficient bonding strength at the bonding interface between the terminal bonding pad and the protruding electrode before and after mounting on a printed circuit board. It may break. Therefore, a test is performed in which a predetermined stress is applied from the side to measure the ball shear strength in a state where a conductor is bonded onto the terminal bonding pad of the interposer substrate to form the protruding electrode.

In general, when conductive connection is made on the conductive pad by wire bonding or the like, the surface of the conductive pad is covered with gold plating or the like so as to improve the electrical connection characteristic with the gold wire or the like. . Therefore, even when the above-mentioned protruding electrode is formed, the surface of the terminal bonding pad may be covered with gold plating or the like in order to improve the electrical characteristics between the protruding electrode and the integrated circuit chip. However, gold plating may increase the ball shear strength in some cases, but because the adhesion between gold plating and the wiring pattern or underlayer is unstable, there is a large variation in ball shear strength. Therefore, it is difficult to supply a stable quality product.

The above problems are not limited to solder balls, but plastic balls whose surface is coated with a conductor by plating or the like may be used, or instead of balls, plating may be performed on the terminal bonding pads. The same occurs when forming bump electrodes.

Therefore, the present invention solves the above-mentioned problems, and its problem is to provide a package provided with a terminal bonding pad for bonding various conductors such as solder balls and bump electrodes to form protruding electrodes. It is an object of the present invention to provide a technique capable of increasing the stability of the bonding strength of an interposer substrate while ensuring the bonding strength with the conductor.

[0007]

In order to solve the above-mentioned problems, a package insertion board of the present invention is provided with a chip connection portion having a predetermined wiring pattern and a plurality of chip connection pads conductively connected to the wiring pattern. And a terminal joint portion having a plurality of terminal joint pads conductively connected to the wiring pattern, so that the chip connecting portion is conductively or indirectly conductively connected to the plurality of input / output portions of the integrated circuit chip. A package interposer configured to be joined to a conductor for forming a protruding electrode, wherein the terminal joint pad of the terminal joint portion is formed on the surface of the chip connection pad and the terminal. The surface of the bonding pad is composed of a silver coating layer made of silver or an alloy mainly composed of silver, and the chip connection pad is on the surface of the base in the wiring pattern. Underlayer made of an alloy mainly composed of nickel or nickel is formed on the formed chip pads formed portion on the surface, Ri name the silver coating layer on a surface of the underlayer is formed, the silver coating layer Is a replacement type of wireless
Formed to a thickness of approximately 0.05 to 0.15 μm by deplating
It has been made and said Rukoto.

According to the present invention, since the surfaces of both the chip connection pad and the terminal bonding pad are made of the silver coating layer, the manufacturing process can be reduced and the material cost can be reduced as compared with gold by using silver. Therefore, the manufacturing cost can be reduced. Also,
Since the chip connection pad has a structure in which the silver coating layer is formed on the underlayer made of nickel or an alloy mainly composed of nickel, the flatness and hardness of the pad surface can be secured, and thus wire bonding is also hindered. The reliability of the conductive connection to the chip can be maintained.

Further , by forming the silver coating layer to a thickness within the above range, the terminal side pad forming portion can be uniformly coated and peeling of the silver coating layer can be prevented. It is possible to increase the bonding strength of the conductors that form the protruding electrodes and the like that are bonded to the terminal bonding pads.
In particular, the silver coating layer is formed by substitution type electroless plating.
By doing so, it is possible to increase the adhesion with the substrate.
Therefore, the strength of the terminal bonding pad can be increased.
It

In the present invention, it is preferable that the chip connection pad is formed with palladium or a base corrosion-resistant layer mainly containing palladium between the chip side pad forming portion and the base layer. According to the present invention, it is possible to improve the film formation rate when the underlayer is formed by the plating process, and it is possible to suppress partial abnormal growth of the plated layer.

Next, a method of manufacturing a package-inserted substrate according to the present invention comprises a predetermined wiring pattern, a chip connecting portion having a plurality of chip connection pads conductively connected to the wiring pattern, and a conductive pattern for the wiring pattern. And a terminal joint portion having a plurality of connected terminal joint pads, wherein the chip connecting portion is configured to be conductively or indirectly conductively connected to the plurality of input / output portions of the integrated circuit chip, A method for manufacturing a package interposer substrate, wherein the terminal bonding pad of a portion is bonded to a conductor for forming a protruding electrode, the chip side pad forming portion provided on the wiring pattern. And a silver coating layer made of silver or an alloy mainly composed of silver as a surface layer of the chip connection pad through an underlayer made of nickel or an alloy mainly composed of nickel. Form, and forming a silver coating layer made of an alloy mainly composed of silver or silver as a surface layer of the terminal connection pads obtained terminal side pad forming portion on which is provided on the wiring pattern.

In the present invention, it is desirable that the silver coating layer be formed by electroless plating. By forming the silver coating layer by the electroless plating method, the wiring pattern for plating required for electrolytic plating becomes unnecessary, so that it is possible to easily perform processing even in the case of high-definition pattern shape and electrode arrangement. it can. In particular, by forming the silver coating layer with a substitution-type electroless plating solution, the adhesion with the base can be enhanced, so that the strength of the terminal bonding pad can be enhanced.

In each of the above inventions, when the silver coating layer is formed on the undercoat layer, it is preferable that the silver coating layer is formed after performing the etching treatment after forming the undercoat layer. In this case, the adhesion strength of the silver coating layer can be increased. It is particularly preferable to use sulfuric acid for the etching treatment. The sulfuric acid concentration is preferably about 5 to 15 vol%.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Next, with reference to the accompanying drawings, a comparative configuration of a packaged substrate and a method of manufacturing the same according to the present invention
Examples and embodiments will be described in detail. FIG. 1 is a schematic cross-sectional view showing a schematic structure of a BGA (ball grid array) package using the package-inserted substrate according to the present embodiment. The interposer board 10 of this embodiment has the same material as the printed circuit board made of synthetic resin such as epoxy resin mixed with glass fiber. Interposer board 10
As such, in addition to such a thing, a tape-like or film-like thing made of a polyimide resin or the like, or
A metal substrate or the like can also be used.

A wiring pattern 11 including a plurality of wirings 11a is formed inside and on the surface of the interposer substrate 10. The wiring pattern 11 may be formed only on the surface of the interposer substrate 10, and may have a structure in which the portions formed on the upper surface and the lower surface are conductively connected via the through holes, or, The interposer substrate 10 may have one or more wiring layers inside. In the latter case,
The interposer substrate 10 can be formed by a bonding method or a build-up method.

A chip connecting portion 12 is provided on the upper surface of the interposer substrate 10.
In the chip connection portion 12, a large number of arranged chip connection pads 12a connected to the wirings 11a in the wiring pattern 11 are formed. An integrated circuit chip 21 is fixed inside the chip connecting portion 12. A conductive wire 22 made of a gold wire or the like is welded to the input / output pad 21a formed on the integrated circuit chip 21 and the chip connection pad 12a by wire bonding, and the input / output pad 21 is connected via the conductive wire 22.
a and the chip connection pad 12a are conductively connected.
A resin mold 23 is provided on the upper surface of the insertion substrate 10,
The chip connection pad 12a, the semiconductor chip 21, and the conductive wire 22 described above are sealed.

A terminal joint portion 13 is provided on the lower surface of the interposer substrate 10, and the wiring pattern 11 is formed on the terminal joint portion 13.
Terminal bonding pads 1 respectively connected to the internal wiring 11a
3a are arranged in a grid pattern. Each terminal bonding pad 13
Solder balls 24 are welded and joined to a, respectively. This solder ball 24 is used for the terminal bonding pad 13a.
By being bonded to the upper side, a protruding electrode protruding from the lower surface of the insertion substrate 10 is formed.

The interposer board 10 of this embodiment is shown in FIG.
It is manufactured in a state of a so-called BGA wiring board 100, which is a mother board shown in (1), and is finally divided into individual interposer boards 10 by a cutting process or the like. Further, the mounting of the integrated circuit chip 21, the molding, the bonding of the semiconductor balls 24, etc. may also be performed in the state of the BGA wiring substrate 100. The BGA wiring board 100 is in a state in which the plurality of interposer boards 10 are integrally arranged vertically and horizontally. The BGA wiring board 100 includes a plurality of interposer boards 10.
Corresponding to the chip connection portion 12 and the terminal joint portion 13 are configured.

In this embodiment, the wiring pattern 11 made of a copper pattern is formed on the upper surface and the lower surface of the chip connecting portion 12. When a copper-clad substrate is used as the BGA substrate 100, the wiring pattern is formed by a patterning process using a photolithography method. Alternatively, the copper plating film may be formed on the base material and then subjected to a patterning process. Further, when the substrate has a wiring layer, the wiring pattern 11 is formed by a build-up method or bonding. Further, a pad forming portion, which will be described later, provided on the chip connection pad 12a and the terminal bonding pad 13a is also formed at the same time as the wiring pattern 11.

FIG. 2 is a schematic sectional view showing the sectional structure of the BGA wiring board 100. In the BGA wiring board 100, a part of the wiring pattern 11 is formed on the upper surface of a base material 101 made of fiber reinforced synthetic resin or the like, and a chip side pad forming portion 121 is formed at an end of each wiring 11a. Substrate 1
On the upper surface of 01, the insulating film 102 that covers the wiring 11a connected to the chip side pad forming part 121 is formed so as to avoid the chip side pad forming part 121. A part of the wiring pattern 11 is also formed on the lower surface of the base material 101, and the terminal side pad forming portion 1 is formed at the end of each wiring 11a.
31 is formed. Each wiring 11a having the terminal side pad forming portion 131 at its end is conductively connected to the chip side pad forming portion 121. On the lower surface of the base material 101, the insulating film 103 that covers the wiring portion connected to the terminal side pad forming portion 131 is provided.
It is formed so as to avoid 1.

A surface layer 122 is laminated on the surface of the chip side pad forming portion 121, and the chip side pad forming portion 1 is formed.
21 and the surface layer 122 form the chip connection pad 12. On the other hand, the surface layer 132 is also laminated on the surface of the terminal-side pad forming portion 131, and the terminal-side pad forming portion 131 and the surface layer 132 form the terminal bonding pad 13. The planar shape of the terminal side pad forming part 131 is as shown in FIG.
Reference numeral 31 is provided so as to be slightly widened at the tip of each wiring 11a of the wiring pattern 11. Terminal side pad forming portion 131
Are arranged in parallel in a grid pattern as shown in FIG.

FIG. 3 is an enlarged sectional view showing the structure of the chip connecting pad 12a in the chip connecting portion 12. As shown in FIG. ratio
In the chip connection pad 12a of the comparative configuration example, a base layer 122a containing phosphorus and containing nickel as a main component is formed by electroless plating on the surface of the chip side pad forming portion 121 made of the above copper pattern, and is formed on the base layer 122a. A corrosion-resistant layer 122b containing a small amount of phosphorus and mainly composed of palladium is formed by an electroless plating method, and a coating layer 12 made of gold is formed on the corrosion-resistant layer 122b.
2c is formed by the electroless plating method.
In this case, the base layer 122a, the corrosion resistant layer 122b, and the coating layer 122c form the surface layer 122.

An outline of the method of manufacturing the surface layer 122 is shown below. The wiring pattern 11 on the upper surface of the BGA wiring board 100 is covered with the insulating film 102 made of a resist or the like except for the portion where the chip side pad forming portion 121 is formed. First, in this state, the BGA wiring board 100
Degreasing against the upper surface of the (eg "ACID CLEANE
R 1022 "or" ACID CLEANER 81
1 "(both manufactured by Shipley Far East Co., Ltd.) is used. ) And acid soft etching (eg “PRE
POSIT ETCH 748 "(manufactured by Shipley Far East Co.) is used. ) Are sequentially performed, and then PDC-
10W (made by Ishihara Yakuhin, trademark or product number)
To activate the copper surface of the chip side pad forming portion 121. This PDC-10C is palladium chloride 0.
It is an aqueous solution containing 42% and sodium acetate 20% as main components.

Next, the underlayer 1 which is a nickel coating is formed on the surface of the chip side pad forming portion 121 by electroless plating.
22a is formed. The plating solution used in this plating is NIPOSIT for 75 ml of ion-exchanged water.
65M (trade name, product number, manufactured by Shipley Far East Co., Ltd.) is 18.75 ml and NIPO
6.25 ml of SIT R (trade name, product number, manufactured by Shipley Far East Co., Ltd.) was added and stirred, and the liquid temperature was adjusted to 85 to 93 ° C., preferably 88 ° C. Here, the pH of the plating solution is 4.6-4.
8, preferably 4.7. Further, with respect to 1 liter of ion-exchanged water, 150 ml of Nimden NPR-4-M (trademark, product number, manufactured by Uemura Industry Co., Ltd.),
Nimden NPR-4-D (trademark, manufactured by Uemura Industry Co., Ltd.
(Product number) and 5 ml respectively, and stir,
A liquid having a liquid temperature of 79 to 81 ° C., preferably 80 ° C. can also be used. The pH of the plating solution in this case is 4.5-
It is 4.7, preferably 4.6.

The base layer 122a was formed to a thickness of about 5 μm by immersing it in the above plating solution for about 30 minutes. The plating solution contains a phosphorus compound (such as hypophosphite) together with nickel, and the formed underlayer 122a has an average composition of 93 wt% nickel and about 7 wt% phosphorus.
It is prepared to be

Next, the BGA wiring board 100 is immersed in an electroless palladium plating bath to form a corrosion resistant layer 122b, which is a palladium coating, on the surface of the underlayer 122a. As this plating bath, 160 to 240 milliliters of APP-10 (manufactured by Ishihara Chemical Co., Ltd., trademark or product number) per 1 liter of ion-exchanged water, preferably 200 milliliters, APP-20W (manufactured by Ishihara Chemical Co., Ltd., Trademark or product number) is added to 40 to 60 ml, preferably 50 ml, respectively, and mixed, and the bath temperature is adjusted to 45 to 55 ° C, preferably 50 ° C. The pH of the plating bath is 7.5 to 8.5, preferably 8.2.

The above APP-10 contains 0.9% of palladium chloride and 6.0% of ethylenediaminetetraacetic acid tetrasodium as main components. In addition, APP-20
Contains 20% sodium phosphinate.
The plating solution contains a small amount of a phosphorus compound, and the corrosion-resistant layer 122b thus formed has an alloy composition of about 96 wt% palladium and about 4 wt% phosphorus. The corrosion resistant layer 122b has a thickness of 0.05 to 0.1 μm. Here, the thickness of the corrosion resistant layer 122b is preferably in the range of about 0.01 to 0.2 μm. The lower limit of the thickness of the corrosion-resistant layer 122b is not always clear, and it is considered that the effect described later can be obtained even if the thickness is 0.01 μm or less as long as it is uniformly formed. It is difficult to form a film in terms of manufacturing technology, and it is preferably 0.01 μm or more in order to obtain reproducibility. If the thickness of the corrosion-resistant layer 122b exceeds 0.2 μm, the surface condition of the coating layer 122c described below tends to deteriorate, and the amount of expensive palladium used increases to increase the manufacturing cost. Not good for

Finally, the surface of the anticorrosion layer 122b is plated with substitutional gold to form a coating layer 122c which is a gold coating in two steps. First, about 1 by the strike bath
A thin film of about 0.05 μm is formed on the surface of the corrosion-resistant layer 122b by displacement plating for 0 minutes, and then electroless displacement plating is performed for about 10 to 15 minutes using a neutral bath to finally form a thin film. Then, a coating layer 122c having a thickness of about 0.5 μm is formed. Here, in the above-mentioned strike bath, "EL-222
GOLD "(manufactured by Shipley Far East Co., Ltd.,
(Trademark, product number), 250 ml, and potassium gold cyanide are mixed at a ratio of 1.5 g, and the pH is adjusted to 8.5 to 9.5, preferably 9.0 with aqueous ammonia, and the liquid temperature is 60. -80 degreeC, Preferably it was 70 degreeC. Further, "Orical TSS-22" (trademark, product number, manufactured by Uemura Kogyo Co., Ltd.) can also be used.
This is 10 ml of "Orical TSS-22-M20" (trademark, product number, manufactured by Uemura Kogyo Co., Ltd.), 6.0 g of potassium potassium cyanide, and 100 g of potassium cyanide per liter of ion-exchanged water. The mixture is mixed at a ratio of milliliter, the pH is adjusted to 4.5 to 6.0, preferably 4.8 with ammonia water or citric acid, and the liquid temperature is set to 75 to 85 ° C, preferably 75 ° C. is there. In addition, in the above neutral bath, "Aurical TTT-
11 "(trademark, product number, manufactured by Uemura Kogyo Co., Ltd.) was used. This is 500 ml of "Orical TTT-11-M2" (trademark, product number manufactured by Uemura Kogyo Co., Ltd.), 5.9 g of potassium potassium cyanide and 0 of potassium cyanide per 1 liter of ion-exchanged water. The pH was adjusted by mixing at a rate of 0.05 ml, and the liquid temperature was 75 ° C. and the gold concentration was 3.6-while appropriately replenishing each component.
4.1 g / l, preferably 4 g / l, pH
Is 4.6 to 5.0, preferably 4.8.

The thickness of the surface coating layer 122c is usually 0.0.
It is preferably formed within a range of 5 to 0.5 μm. If the thickness is less than 0.05 μm, the surface of the circuit electrode portion cannot be sufficiently covered, it is difficult to control the thickness, and it is difficult to obtain the effect of using gold in terms of conductive connectivity. When the thickness is 0.5 μm or more, the surface condition deteriorates and the manufacturing cost increases.

As the structure of the chip connection pad 12a, as shown in FIG.
21 and the underlayer 122a between the underlayer corrosion-resistant layer 1 shown below.
It is preferable to form 22d. This base corrosion-resistant layer 12
2d is BGA under the same conditions as the above-mentioned corrosion resistant layer 122b.
The wiring board 100 is dipped in an electroless palladium plating bath to form a base corrosion resistant layer 122d. For this plating bath, "APP-1
0 "(trademark or product number manufactured by Ishihara Yakuhin Co., Ltd.) is 160 to 240 ml, preferably 200 ml, and" APP-20W "(trademark or product number manufactured by Ishihara Yakuhin Co., Ltd.) is 40 to 60 ml, preferably 50 ml, respectively, were added and mixed, and the bath temperature was adjusted to 45 to 55 ° C, preferably 50 ° C.
The pH of the plating bath is 7.5 to 8.5, preferably 8.2.

The above-mentioned "APP-10" contains 0.9% of palladium chloride and 6.0% of ethylenediaminetetraacetic acid tetrasodium as main components. In addition, APP-
20 contains 20% of sodium phosphinate. The plating solution contains a small amount of a phosphorus compound, and the formed corrosion-resistant layer 122d has an alloy composition of about 96 wt% palladium and about 4 wt% phosphorus. In the present embodiment, the plating treatment is performed for 5 minutes under the above conditions, and the base corrosion-resistant layer 122d is formed on the surface of the chip-side pad forming portion 121 to have a thickness of about 0.1 to 0.2 μm. If the thickness of the base corrosion-resistant layer 122d is 0.01 μm or more, the chip-side pad forming portion 1
21 can be coated, and the catalytic effect described later can be obtained. The thickness of the base corrosion-resistant layer 122d is 0.2.
When the thickness is less than or equal to μm, the adhesion to the portion other than the chip-side pad forming portion 121 can be prevented, the final surface aspect of the circuit electrode portion can be kept good, and an extra base corrosion-resistant layer 122d is preferable in that it does not increase the manufacturing cost.

In the laminated structure of the circuit electrode portion formed as described above, the base corrosion-resistant layer 122d and the base layer 1 are formed on the surface of the chip side pad forming portion 121 of the wiring pattern 11.
22a, a corrosion resistant layer 122b, and a coating layer 122c are sequentially stacked. As described in Japanese Patent Application No. 9-74411 filed by the present inventors, the base corrosion-resistant layer 122d is formed on the surface of the chip-side pad forming portion 121 when the base layer 122a is formed. Utilizing the effect that phosphorus is preferentially deposited on the layer 122d, a high phosphorus concentration is realized in the lower layer portion of the base layer 122a, and the coating layer 122 is formed.
In order to suppress the erosion of the lower layer of the underlayer 122a during the gold substitution reaction that occurs during the formation of c, the film quality of the underlayer 122a is made uniform and of high quality, and the erosion of the underlayer 122a itself is reduced. And underlayer 12
This is for improving the surface condition of the coating layer 122c formed on the surface of 2a. Also, the chip side pad forming portion 12
In the case where the structure shown in FIG. 3 is formed by selectively forming the palladium film only on the surface of No. 1, the boundary between the insulating film 102 and the chip side pad forming portion 121 by increasing the concentration of the palladium catalyst. This is to avoid abnormal growth at the boundary portion of the nickel coating that occurs in the portion. That is, when the underlying corrosion-resistant layer 122d is not formed, the chip side pad forming portion 121 and the underlying layer 122a are formed.
In order to improve the adhesiveness with the underlayer 122a and to improve the film quality of the underlayer 122a, it is necessary to bring a high-concentration palladium catalyst into contact with the surface of the chip-side pad forming portion 121 in the activation treatment performed before forming the underlayer 122a. But
This is because the nickel film is also deposited on the boundary between the chip-side pad forming portion 121 and the insulating film 102 by the effect of the palladium catalyst, so that the boundary rises abnormally.

In this comparative example , since the corrosion resistant layer 122b is formed on the underlayer 122a and the erosion itself of the underlayer 122a hardly occurs, the role of the lower corrosion resistant layer 122d is mainly that of the underlayer 122a. It is to improve the film quality and the surface condition thereof and to suppress the abnormal growth of the boundary portion. By improving the film quality of the underlayer 122a and improving the surface condition thereof, the surface condition of the coating layer 122c is also improved. Of course, the surface condition of the coating layer 122c seems to be improved by the presence of the corrosion resistant layer 122b.

In this comparative configuration example , the base layer 122a,
Since the corrosion-resistant layer 122b is formed between the surface and the coating layer 122c, the plating liquid for gold plating enters the boundary portion between the laminated structure of the chip connection pads 12a and the insulating film 102 in the process of forming the coating layer 122c. Since it becomes difficult to prevent erosion and deterioration in the boundary portion of the base layer 122a, the quality of the chip connection pad 12a can be further improved.

Next, referring to FIG. 5, according to the present embodiment.
To describe the structure of the terminal connection pads 13a and a manufacturing method thereof that. The terminal bonding pad 13a is formed by forming a surface layer 132 made of a thin silver plating layer on the surface of the terminal side pad forming portion 131 made of a copper pattern. Surface layer 1
The formation of 32 is performed as follows. First, "AGPOSIT 7100" is formed on the bottom surface of the BGA wiring board 100.
(Manufactured by Shipley Far East Co., Ltd.) is sprayed by a spray method and a degreasing process is performed to remove organic substances from the surface of the terminal side pad forming portion 131. After that, a water washing process is performed by a spray method. Next, water is removed from the surface of the substrate by air blow, and “AGPOSIT
7200 "(manufactured by Shipley Far East Co., Ltd.)
Then, the surface of the terminal side pad forming portion 131 is subjected to etching treatment. After that, a water washing process is performed again by a spray method. Moreover, you may perform the same process as follows. That is, "Alpha500" (manufactured by Nippon Alpha Metals Co., Ltd.) containing an organic solvent as a main component is sprayed on the lower surface of the BGA wiring board 100 by a spray method, and degreasing is performed to remove organic matter from the surface of the terminal side pad forming portion 131. Remove. After that, a water washing process is performed by a spray method. Next, an aqueous solution containing sulfuric acid and hydrogen peroxide solution was prepared so that “Alpha 1000” (manufactured by Nippon Alpha Metals Co., Ltd.) was 5 vol%, and was sprayed to spray the terminal side pad forming portion 13
The surface of 1 is soft-etched. After that, a water washing process is performed again by a spray method.

Next, it is immersed in "AGPOSIT 7300" (manufactured by Shipley Far East Co., Ltd.) to prevent impurities from being brought into the silver plating bath. Next, "AGPOS
The substrate is immersed in a plating bath formed by "IT7400" (manufactured by Shipley Far East Co., Ltd.) to perform electroless silver plating. After that, a water washing process is performed again by a spray method. This electroless plating is a substitution type reaction with respect to the surface of the terminal side pad forming portion 131, and deposits silver while melting the copper on the surface. Under the conditions of this embodiment, the elution amount of copper and the deposition amount of silver were almost 1: 1. Next, "AGPOSIT
7500 "to stabilize the deposited silver coating. Also,
You may perform the same process as follows. That is, BGA is contained in a bath formed by "Alpha 2000" (manufactured by Nippon Alpha Metals Co., Ltd.), which is an organic chelating agent
The wiring board 100 is dipped to remove impurities that may adversely affect the plating process from the surface of the board. afterwards,
Further, a water washing process is performed. Next, the above "Alpha20
00 "(manufactured by Japan Alpha Metals)" 90% by volume "Alpha3000" (manufactured by Japan Alpha Metals)
The substrate is dipped in a plating bath formed by adding and electroless plating of silver is performed. This electroless plating also causes a substitution type reaction with respect to the surface of the terminal side pad forming portion 131, and deposits silver while melting the copper on the surface. The amount of copper eluted and the amount of silver deposited are approximately 1: 1 under the conditions of this embodiment.

The thickness of the silver-plated surface layer 132 formed by electroless plating in this plating bath is about 0.1 μm.
m. The thickness of the surface layer 132 is 0.05 to
The range of 0.15 μm is particularly desirable in order to improve the bonding characteristics described later. If the thickness is less than 0.05 μm, the surface of the terminal side pad forming portion 131 may not be completely covered, and the bonding characteristics and adhesion strength of a conductor such as a solder ball may deteriorate. On the contrary, if the thickness exceeds 0.15 μm, the surface layer 132 may be easily peeled off, or the contact characteristics may be affected by oxidation or the like.

The surface layer 132 deposited on the surface of the terminal side pad forming portion 131 has a silver nitrate composition in this embodiment. The above-mentioned "Alpha3000" contains an organic resin component, and the formed surface layer 132
Thin organic coating (thickness 0.01-0.0
4 μm) is formed. The organic coating suppresses alteration of the surface layer 132.

Next, an example of the processing procedure of the BGA wiring board 100 will be described. First, the BGA wiring board 100
The entire upper surface of is completely covered with a plating resist (a resist that has resistance to a plating solution and can be removed without affecting the underlying insulating film or conductor pattern). Then, on the terminal side pad forming portion 131 formed on the lower surface of the BGA wiring substrate 100, silver is plated by the above method to form the surface layer 132, thereby forming the terminal bonding pad 13a. Next, after cleaning, the plating resist is removed and again cleaned, and this time, the entire lower surface of the BGA wiring substrate 100 is covered with the plating resist. Then, the surface layer 12 is formed on the chip side pad forming portion 121 formed on the upper surface of the BGA wiring substrate 100 by the above method.
2 is formed, and the chip connection pad 12a is formed. Finally, the plating resist on the lower surface of the BGA wiring board 100 is removed and washed.

The BGA package shown in FIG. 1 was constructed using the BGA wiring board 100 of the above embodiment. At this time, one having a wiring pattern plated with copper,
Two types of BGA wiring boards, one having a wiring pattern formed only by a copper foil attached on a base material, were prepared, and these were used to form BGA wiring boards, respectively. Then, solder balls were placed on the terminal bonding pads 13a and heated to bond them. The solder balls thus joined were prepared for the above-described embodiment and the following Comparative Examples 1, 2, and 3, respectively, and the solder ball joining strength (ball shear strength, shear strength) was measured. It was measured. The ball shear strength is measured by applying a stress to the solder ball in parallel with the plate surface of the wiring board by a dedicated measuring device. The results (stress values when the protruding electrodes are broken by the solder balls) are shown in Table 1 below.

In Comparative Examples 1 and 2, nickel electroless plating and gold electroless plating are sequentially performed on the terminal side pad forming portion 131 to form a gold coating layer to form a terminal bonding pad. Then, solder balls are arranged on the terminal bonding pads and heat-bonded. In Comparative Example 1 and Comparative Example 2, the same terminal bonding pad was produced by two different companies. Of these, Comparative Example 1 was carried out by the applicant of the present application, and like the above-mentioned chip connection pad, a corrosion-resistant underlayer made of a palladium film and an underlayer made of a nickel film were formed on the terminal side pad forming portion 131. , A coating layer composed of a gold coating is sequentially formed.

Comparative Example 3 is the above-mentioned terminal side pad forming portion 1
A publicly known flux process is performed on 31 and then solder balls are directly adhered to the terminal side pad forming portion 131 by flux and heat-bonded.

The exposed surface of the terminal bonding pad 13a of the BGA wiring board 100 is a circle having a diameter of 0.25 mm.
The solder ball used had a diameter of 0.45 mm. Also,
The conditions of the heat bonding treatment were a temperature of 250 ° C. and a heating time of 30 seconds. In this case, a stress value of 300 g or more is a normal value or an allowable range.

[0044]

[Table 1]

As described above, in the case of the present embodiment, in both the copper-plated product (the above-mentioned substrate) and the copper-clad substrate used as it is (the above-mentioned substrate), Comparative Examples 2 and 3
On the other hand, it is understood that the ball shear strength is high and the variation in the ball shear strength is small. Therefore, it is understood that stable joining is performed in the present embodiment. In addition, the ball shear strength of the present embodiment is higher than that of Comparative Example 1. In this case, in Comparative Example 1, the three-step plating process is required even if the pre-processing and post-processing are removed. However, in the present embodiment, only one plating process needs to be performed, so that the manufacturing cost can be significantly reduced and the production can be performed. The efficiency can be increased.

Next, when the chip connection pad 12a is composed of an underlayer made of nickel or an alloy containing nickel as a main component, and a silver coating layer formed on the surface of the underlayer (this embodiment). A specific example of will be described. By forming the coating layer 122c on the underlying layer 122a as in the above comparative configuration example, the bonding characteristics and the adhesion of the coating layer 122c can be improved, but the underlying layer 122a similar to the above is used. Bonding characteristics and adhesion of the silver coating layer can also be secured by forming a silver coating layer on the silver coating, and the material cost of the silver coating layer is lower than that of gold. Since the coating layer can be formed simultaneously with the silver coating layer of the terminal bonding pad described later, the manufacturing cost can be greatly reduced.

In this case, the underlayer may have the same composition as the underlayer 122a forming the chip connection pad 12a, and the manufacturing method thereof may be similar to that of the underlayer 122a. it can. The silver coating layer can be formed by the same manufacturing method as that of the surface layer 132 described above. At this time, it is possible to form the silver coating layer on the surface of the undercoat layer as it is (after washing only), but in particular, in order to further improve the adhesion of the silver coating layer, the undercoat layer is formed. After that, it is preferable to apply an acid treatment as an etching treatment to the surface of the underlayer. It is preferable to use sulfuric acid for this acid treatment, and it is particularly preferable to use an aqueous solution having a sulfuric acid concentration of 5 to 15 vol%. The acid treatment time is usually about 30 seconds to 5 minutes, though it depends on the sulfuric acid concentration and the constitution of the treatment device. By this, the surface layer portion of the underlayer can be removed, and it is considered that the adhesion is improved.

The package-inserted substrate of the present invention is not limited to the above illustrated examples, and it goes without saying that various modifications can be made without departing from the scope of the present invention.

[0049]

As described above, according to the present invention,
By covering the surface of the terminal bonding pad of the terminal bonding portion with the silver coating layer while ensuring the conductive connectivity of the chip bonding pad, it is possible to increase the bonding strength between the terminal bonding pad and the solder ball and the like. Since the variation can be reduced, the reliability of the conductive connection portion of the package insertion board can be improved, and the reliability of the integrated circuit package including the package insertion board can be improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a schematic structure of a BGA package using an embodiment of a package insertion board according to the present invention.

FIG. 2 is a partially enlarged sectional view showing a part of the package insertion board of the embodiment in an enlarged manner.

FIG. 3 is an enlarged cross-sectional view showing a structural example of a chip connection pad formed on the surface of the package insertion substrate of the same embodiment.

FIG. 4 is an enlarged cross-sectional view showing another structural example of the chip connection pad formed on the surface of the package-inserted substrate of the same embodiment.

FIG. 5 is an enlarged cross-sectional view showing a structural example of a terminal bonding pad formed on the surface of the package insertion board of the same embodiment.

FIG. 6 is a partial cross-sectional perspective view showing the planar shape of the terminal bonding pad of the same embodiment.

FIG. 7 is a schematic perspective view showing an upper surface of the BGA wiring board of the embodiment (a) and a schematic perspective view showing a lower surface of the BGA wiring board (b).

[Explanation of symbols]

10 Package insertion board 11 wiring pattern 11a wiring 12 Chip connection part 12a Chip connection pad 13 terminal joint 13a terminal bonding pad 100 BGA wiring board 101 base material 102, 103 insulating film 121 Chip side pad formation part 122 surface layer 122a Underlayer 122b Corrosion resistant layer 122c coating layer 122d Underlayer corrosion resistant layer 131 Terminal side pad formation part 132 Surface layer (coating layer)

Continuation of front page (56) Reference JP-A-7-193166 (JP, A) JP-A-9-64225 (JP, A) JP-A-10-56095 (JP, A) JP-A-11-40940 (JP , A) Japanese Patent Publication 7-83069 (JP, B2) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 23/12 H05K 1/11 H05K 3/18

Claims (3)

(57) [Claims] 1. A terminal connection including a predetermined wiring pattern, a chip connection portion including a plurality of chip connection pads conductively connected to the wiring pattern, and a plurality of terminal connection pads conductively connected to the wiring pattern. And a chip connection part is configured to be directly or indirectly conductively connected to a plurality of input / output parts of the integrated circuit chip,
A package insertion substrate configured such that the terminal bonding pad of the terminal bonding portion is bonded to a conductor for forming a protruding electrode, the surface of the chip connection pad and the surface of the terminal bonding pad. Is formed of a silver coating layer made of silver or an alloy containing silver as a main component, and the chip connection pad has nickel or nickel on the surface of the chip side pad forming portion formed on the surface of the base in the wiring pattern. is underlayer made of an alloy mainly is formed, Ri Na with the silver coating layer is formed on the surface of the underlying layer, wherein the silver coating layer by electroless plating substitutional, about 0.0
A package-inserted substrate, which is formed to have a thickness of 5 to 0.15 μm . 2. The chip connection pad according to claim 1 , wherein palladium or a base corrosion-resistant layer mainly containing palladium is formed between the chip-side pad formation portion and the base layer. Package insertion board. 3. A terminal connection having a predetermined wiring pattern, a chip connection portion having a plurality of chip connection pads conductively connected to the wiring pattern, and a plurality of terminal connection pads conductively connected to the wiring pattern. And a chip connection part is configured to be directly or indirectly conductively connected to a plurality of input / output parts of the integrated circuit chip,
A method of manufacturing a package insertion board, wherein the terminal bonding pad of the terminal bonding portion is bonded to a conductor for forming a protruding electrode, the chip side pad provided in the wiring pattern. A base layer made of nickel or an alloy mainly composed of nickel is formed on the forming portion, and the base layer is made into an aqueous solution having a sulfuric acid concentration of 5 to 15 vol%
After etching for about 30 seconds to 5 minutes,
Place the silver coating layer of silver or silver made of an alloy mainly via the underlying layer as a surface layer of the chip connection pads
Formed by replacement electroless plating, and a silver coating layer made of silver or an alloy mainly composed of silver is used as a surface layer of the terminal bonding pad on the terminal side pad forming portion provided on the wiring pattern. A method of manufacturing a package-inserted substrate, characterized by being formed by electrolytic plating .