JP3465481B2 - Programmable logic device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of fixed wirings for wiring between program logic elements constituting logic and between program logic elements, and a plurality of program logic elements and fixed wirings. The present invention relates to a programmable logic device having a number of programmable switches connecting fixed wirings, and more particularly to a technique for supplying a specific signal in such a programmable logic device. 2. Description of the Related Art Conventionally, a specific signal net on a programmable logic device has a plurality of fixed globally fixed global wires fixedly selected, selected by a programmable switch, and supplied to all program logic elements with one buffer. I was FIG. 2 is a schematic diagram for explaining a conventional wiring example of a specific signal net. In FIG. 2, reference numeral 101 denotes a programmable logic device chip. On this chip 101, a bonding pad 110, an input / output buffer 111, and an internal area 102 are provided.
A plurality of program logic elements 103, a large number of programmable switches 200 used for wiring specific signals between these program logic elements, and a large number of specific signal wirings 130, 132, 134 are provided on 02. . However, in order to simplify the drawing, only the programmable switches and the wiring for specific signals are shown as necessary for the description. Conventionally, a specific signal is transmitted to a bonding pad 1
Wirings of specific signal nets connected to the input buffer 10 and from the input buffer 111 to the plurality of program logic elements 103 are, for example, specific signal wirings 130, 132, and 134 as shown in the figure.
Is connected by a large number of programmable switches 200. Therefore, all the program logic elements 103 are driven by the input buffer 111. As can be understood from these examples, conventionally, all the program logic elements are driven by one input buffer. Therefore, the transmission time of the specific signal is a load on all the wiring resistances, all the programmable switches, and all the program logic elements, and the logical design has been performed in consideration of the transmission time. In order to realize a high-speed operation of a programmable logic device, it is necessary to reduce the transmission time of a specific signal which affects the operation speed and to reduce the skew of the transmission time. Therefore, conventionally, when programming logic on a programmable logic device, for a specific signal net requiring high speed and low skew, a dedicated fixed wiring and a programmable switch are provided in an internal area of the programmable logic device. Fixed placement and wiring. However, a programmable logic device is
Process miniaturization, mountable logic scale increase, chip size increase, process miniaturization increases wiring resistance, increase in logic scale increases the number of program logic elements, increases load, increases chip size. As a result of the increase in wiring length due to the increase in scale, there has been a problem that the programmable logic device cannot realize high-speed operation. SUMMARY OF THE INVENTION It is an object of the present invention to improve the problem relating to the wiring of a specific signal net in the future and realize a high-speed operation of a programmable logic device. [0010] To achieve the above object, the present invention introduces a method for distributing a specific signal net to a program logic element on a programmable logic device. That is, it has a global wiring in which a fixed wiring, a buffer, and a programmable switch are fixedly wired, has an input buffer for supplying a specific signal, and a frequency dividing circuit in parallel with the first global wiring. Connected to a programmable switch, connected to a plurality of global wirings to the second global wiring to form a transmission path of a specific signal, and a final stage connected to the program logic element is fixed wiring to the plurality of program logic elements. Connecting. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram for explaining an example of wiring of a specific signal net on a programmable logic device according to the present invention. In FIG. 1, reference numeral 101 denotes a programmable logic device chip, on which a bonding pad 110, an input / output buffer 11
1. An internal area 102 is provided. On the internal area 102, in addition to a plurality of program logic elements 103, a large number of fixed wirings for wiring and programmable switches are provided. FIG. 1 shows that a specific signal is input to an input buffer 111.
5 shows an example of wiring for transmitting data from the program logic element 103 to the program logic element 103. In this wiring example, the specific signal wiring 13
0 to 139 are fixed wiring, specific signal buffers 113 to 1
14 is fixedly arranged, the program switches 120 and 121 are fixedly arranged, and the frequency dividing circuit 112 is fixedly arranged. Dividing circuit 1
Whether the specific signal used by the logic is distributed to the program logic element 103 in the area where the logic uses the output of the input buffer 111 and the output of the input buffer 111 is determined by the program switches 120 and 1.
It is determined by the program data held in the MOS switch 21. FIG. 4 shows a configuration example of the program switch 120. The program switch 120 is a MOS switch 4
The specific signals input from the fixed wirings 131 and 132 are connected to the fixed wirings 133 and 134 according to data programmed in the MOS switches and distributed. FIG. 5 shows a configuration example of the program switch 121. The program switch 121 is a MOS switch 4
A specific signal input from the fixed wirings 137 and 138 is connected to the fixed wiring 139 and distributed according to data programmed in the MOS switch. For example, the programmable logic device 10
1, the input buffer 11
FIG. 1 illustrates a case in which two phases of power are supplied from the output from the output 1 and the output from the frequency divider 112. The specific signal of the input buffer 111 is distributed to the program logic element area 140, and the output of the frequency divider 112 is distributed to the program logic element area 141. The specific signal is supplied from the input buffer 111 to the program switch 120 via the specific signal buffer 113. The program switch 120 turns on the MOS switches 404 and 408 in FIG.
06 is turned off, and the fixed wiring 132 and the fixed wiring 135, 1
34, and is programmed to supply power to the program logic element area 140. The fixed wiring 132 and the fixed wiring 134 are connected by the program switch 120, and power is supplied to the specific signal buffer 114.
To be transmitted. The program switch 121 is a MOS switch shown in FIG.
The switches 412 and 414 are turned on, and the MOS switch 41
1, 413 are turned off, and the fixed wiring 139 connected to the program logic element 103 is programmed to supply power, and a specific signal is transmitted to the program logic element 103. As described above, since the distribution is performed in the program logic element 103 via the buffers 113 and 114, the wiring length is shortened, the wiring resistance is reduced, and the data can be transferred at high speed. Also, the specific signal wirings 130 to 139 are fixed wirings, so that the input buffer 111 sends the program logic elements 103.
Since the transmission path is constant and has the same configuration, the skew of the specific signal can be reduced, the number of program switches can be reduced to two, and the delay time can be reduced. As can be seen from the fact that the output of the input buffer 111 and the output of the frequency dividing circuit 112 are performed by the program data of the program switches 120 and 121, the transmission path of the multi-phase specific signal can be programmed.
Since the programming is performed to select No. 9, the wiring efficiency is improved by not having a dedicated wiring 139 for each program logic element region using each phase. Incidentally, it is naturally possible to easily connect the input from the input buffer instead of the output of the frequency dividing circuit. It can also be understood that it can cope. The input buffer 111 and the fixed wiring 130
It is a matter of course that a configuration in which a PLL is connected between the two is also possible. FIG. 3 shows an example of the configuration of the specific signal when the logic is larger than that of FIG. This figure shows a configuration in which a global configuration consisting of specific signal wiring, a buffer, and a programmable switch is increased by one stage. Thus, it is possible to cope with an increase in the scale. As described in detail above, according to the present invention, in a programmable logic device, the transmission time of a specific signal can be reduced and the skew of the transmission time can be reduced. The device can be operated at high speed. In a programmable logic device, a number of effects can be obtained, such as a reduction in the number of loads and a reduction in power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram for explaining a wiring example of a specific signal net in an internal region of a program logic device according to the present invention. FIG. 2 is a schematic diagram for explaining a wiring example of a specific signal net in a conventional program logic device. FIG. 3 is a schematic diagram for explaining a wiring example of a specific signal net in an internal area of a program logic device according to the present invention. FIG. 4 is a schematic diagram illustrating a configuration example of a specific signal programmable switch according to the present invention. FIG. 5 is a schematic diagram for explaining a configuration example of a specific signal programmable switch according to the present invention. [Description of Signs] 101: Program logic device chip, 102: Internal area of program logic device, 103: Program logic element, 110: Bonding pad, 11
1: input buffer 112: frequency divider circuit
113 to 116: buffer for specific signal, 120 to 122
... Programmable switches for specific signals, 130 to 139
... fixed wiring for specific signal, 200 ... programmable switch, 401-408 ... MOS switch, 411-4
14 ... MOS switch.

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Claims (1)

(57) Claims 1. A signal to be supplied with a first signal of a first phase.
A first region in which a number of first logic elements are arranged;
A plurality of second logic elements to which a second signal of the phase is to be supplied
A signal is input from the outside and a second area where
An input buffer for outputting a signal toward the first and second areas.
And the signal output from the input buffer.
The multiple transmissions to each of the first and second logic elements
Number of signal wiring and programmable logic data
Device connected to the input buffer and output from the input buffer.
A first signal line for transmitting the first signal to be applied;
Connected to the first signal line to divide the first signal
A second signal line for transmitting the second signal,
Each of the first and second signal lines is connected via a buffer.
Connected first switch and connected to the first switch
And the first and second signals output from the first switch.
A third signal wiring for transmitting any of the two signals and
And fourth signal wiring, and those of the third and fourth signal wirings
And second switches respectively connected via buffers.
Switch and a third switch, and the second switch and a front switch.
The second switch connected to the plurality of first logic elements;
The first signal or the second signal output from the
A fifth signal wiring for transmitting the signal in the first area,
A third switch connected to the plurality of second logic elements;
The first signal output from the third switch
Or a second signal transmitting the second signal within the second region.
6 signal wirings, wherein the first switch receives the input first and second signals.
Is connected to the third signal line and the fourth signal line.
Output to each signal wiring, and the second switch
Of the first and second signals inputted, the at least
Also selects a signal to be supplied to one first logic element and
The signal is output to a fifth signal line, and the third switch is
Of the first and second signals inputted, the at least
Also selects a signal to be supplied to one second logic element and
Outputting to the sixth signal line, the plurality of first logic elements.
Converts the signal output from the second switch to the fifth switch.
Receiving from a signal line, wherein the plurality of second logic elements are
The signal output from the third switch is connected to the sixth signal
Programmable theory Ride, characterized in that it receives from the line
Vice.