JP3465887B2 - Test method for semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor integrated circuit (I
In particular, the present invention relates to a semiconductor integrated circuit test method capable of removing a semiconductor integrated circuit failure due to the influence of crosstalk noise by adding a small number of test patterns in a test process for detecting a failure of an IC, in addition to the test method of C).

[0002]

2. Description of the Related Art In the development of semiconductor integrated circuits, process miniaturization has progressed in recent years, resulting in higher integration and higher performance. In such a situation, the influence of crosstalk noise is likely to occur, which is often a problem.

The influence of this crosstalk is (1) as the wiring length of the adjacent wiring becomes longer, (2) as the wiring interval becomes narrower, (3) as the driver capability becomes different, and (4) between wirings among wiring capacitances. The higher the capacity ratio, the easier it is to receive. In addition, when the adjacent wirings are operated such that one side rises at the same time and one side rises at the same time, the delay value becomes large, and if the same change occurs at the same time, the delay value becomes small. Also, if one of the adjacent wires has a fixed value and only one of them changes, the drive capacity of the wire with a fixed value is lower than that of the changing wire, and the ratio of the inter-wiring capacity to the wiring capacity is high. Causes the influence of crosstalk that noise occurs in a fixed value signal, leading to malfunction.

Regarding the influence of this crosstalk, the design is guaranteed by performing delay verification and function verification in consideration of delay variation and noise at the stage of circuit design of the semiconductor integrated circuit. On the other hand, in a manufacturing test, a test pattern created by a gate delay ATPG using a scan path is used for testing a semiconductor integrated circuit that causes a failure due to a delay.

A pattern created by the gate delay ATPG using the OR gate circuit in the circuit diagram of FIG. 8 will be described. The OR circuit 40 receives an input signal from the input terminals A and B and obtains an output signal from the output terminal X. In this case, in order to detect the rising gate delay fault of the output terminal X, the gate delay ATPG tool uses OR to bring the output terminal X into the rising state.
Connect the input terminal A and the input terminal B of the gate to 1) the input terminal A.
Rises and the input terminal B remains fixed at 0. 2) The input terminal A rises and the input terminal B also rises. 3) The input terminal A is fixed at 0 and the input terminal B rises.
An attempt is made to create a pattern for making a kind of state, and one pattern that can be easily set to that state is selected and made.

[0006]

In the pattern generated by such a mechanism, it is necessary to determine whether or not both adjacent wirings that have the effect of crosstalk have the same change and the opposite change at the same time. I don't know. For this reason,
In manufacturing tests, failures due to the effects of crosstalk could only be removed by accident.

Another technique is a gate delay ATP
When a pattern in G is generated, all possible input combinations are generated as a pattern, and a manufacturing test is performed using the pattern to remove a semiconductor integrated circuit that fails due to the influence of crosstalk. It was being done. In this method, at the input terminals A and B of the OR gate of FIG. 8, 32 4 gate delay test pattern combinations of 2 4 are required, which is required for all terminals of the circuit. There is a problem in that a huge number of test patterns are required in order to consider the influence of crosstalk at the time of manufacturing test, because the number of powers of a number is required.

An object of the present invention is to make it possible to perform a manufacturing test in consideration of a failure due to the influence of crosstalk, and to make a manufacturing test pattern in consideration of a failure due to the influence of crosstalk with a minimum number of patterns. A test method for a semiconductor integrated circuit is provided.

[0009]

A semiconductor integrated circuit test method according to the present invention has a structure in which a netlist satisfying a logical function is input, a scan path test structure is created, and the netlist is mask pattern laid out. A gate delay ATP is used to extract a dangerous point in the layout where a crosstalk effect is likely to appear, and a test pattern in which a crosstalk effect appears at the extracted dangerous point.
It is characterized in that a test circuit is added in order to create in G, and a manufacturing test is performed by using a test pattern generated by performing a gate delay ATPG in the circuit.

In the present invention, a netlist satisfying a logical function is input, a scan path test structure is created,
Step 1 for improving controllability and observability by adding a scan FF or an external terminal for a portion of the netlist where controllability to 0 and 1 of each signal line and observability are not sufficient
And a step 2 of performing a mask pattern layout by inputting a netlist satisfying the logic function in which the scan path is inserted, a step 3 of extracting an adjacent wiring portion affected by crosstalk noise, and an input of the extracted logic gate. Using the contents of the dangerous point information file extracted in step 3, the test circuit for converting the signal into the transition of the signal value where crosstalk noise is likely to occur using the gate delay ATPG tool. Step 4 of adding to the list, and Step 5 of generating a test pattern having a signal value that easily causes crosstalk noise at the input of the logic gate extracted in Step 3 by using the test circuit of Step 4 by the gate delay ATPG tool. And the expected value at the external terminal of the test circuit added in step 5 is deleted. Step 6 of the test pattern modifications that that may include a step 7 for testing a semiconductor integrated circuit by a test pattern that is modified in step 6.

In the present invention, the extraction of the adjacent wiring at the dangerous place is performed by extracting the wiring capacitance and the wiring length of each wiring, calculating the capacitance between the adjacent wirings, and the capacitance between the adjacent wirings exceeds the predetermined reference value. The wiring is taken out, the flip-flops that are the same drive source are divided into groups based on the back trace results of the clock terminals of all the flip-flops, and the wirings in which the adjacent wirings in the same group have a synchronous relationship are taken out. It is possible to take out a drive having a difference in drive capacity of more than a reference value and a ratio of inter-wiring capacitance of a wiring capacity of a wiring having a smaller drive capacity exceeds a predetermined reference value.

Therefore, by testing the semiconductor integrated circuit using the present invention, it is possible to remove the failure of the semiconductor integrated circuit due to the influence of the crosstalk noise by adding a small number of test patterns.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flow chart of a test method for explaining an embodiment of the present invention. Referring to FIG. 1, a scanlist is inserted with a netlist 1 satisfying a desired logical function as an input, and at the same time, a control circuit is added to a test circuit for a portion with poor observability (step S1), and mask pattern layout processing is performed. Mask pattern data is created (step S2). Using the placement and wiring results,
Adjacent wiring susceptible to the influence of crosstalk noise is extracted as a dangerous point (step S3) and recorded in the dangerous point net file 7. With respect to the extracted signal, a gate delay ATPG tool adds a test circuit for generating a test pattern susceptible to the influence of crosstalk noise to the netlist 2 created in step S1 (step S4). At this time, the test circuit is added only to the netlist 2 and is not reflected in the layout mask pattern.

Next, a test pattern is created by the gate delay ATPG tool for the netlist 2 to which the test circuit is added. In the next step, a test pattern correction process of deleting an expected value of a terminal added as a test circuit which does not actually exist in the semiconductor integrated circuit itself is performed (step S5), and the test is performed (step S).
6). The files 3 to 7 are files that store respective information during each step.

Next, the dangerous point extraction processing which is susceptible to crosstalk noise in step S3 will be described. Figure 2
Referring to the flowchart of FIG. 5, in order to check the degree of influence of crosstalk noise from the layout result, the wiring capacitance of each wiring (step S11), the adjacent wiring length is extracted (step S12), and the capacitance between adjacent wirings for each wiring is calculated. Calculate (step S13). Next, the reference value of the capacitance between the adjacent wirings which causes a delay time delay due to the crosstalk noise and the malfunction, which is set in advance, and the capacitance between the adjacent wirings obtained in step S13 are compared, and the adjacent wiring (Y) exceeding the reference value is extracted. However, the adjacent wiring (N) which is stored in the dangerous place net file 7 and does not exceed the reference value is recorded in the non-target file 8 (step S14).

Next, using the netlist 2 in FIG. 1, backtrace is performed from the clock, set, and reset terminals of all FFs in the netlist to the external input terminals and logic gates, and the effect of crosstalk is caused. Reset, set signal, which has low wiring activation rate and is less susceptible to delay variation
Further, the names of clock signals to be arranged and wired so as not to be affected by the crosstalk noise in advance are extracted (step S15).

At the same time, all flip-flops (FFs) are used in order to extract adjacent wirings in which delay variations due to the influence of crosstalk noise are likely to occur and simultaneous changes may occur.
Based on the back trace result of the clock terminal, the same drive source FFs are grouped into the same group (step S16).

Next, the adjacent wiring extracted in step S4 is backtraced until it reaches an external terminal or reaches FF on the netlist 2 created in step S1 to extract the drive source (step S17). . Finally, with the adjacent wiring extracted in step S14, step S15
Is not the signal name extracted by step S16, and
By using the grouping information of the FF created in step 2, whether or not the adjacent wirings are in a synchronous relationship is checked by checking whether or not the drive source of the adjacent wirings belongs to the same group (step S18). The adjacent wiring (Y) to be extracted is extracted and stored in the dangerous point net file 7,
The adjacent wiring (N) not in the synchronous relationship is recorded in the non-target file 8. .

Next, the driver of the adjacent wiring is searched in order to extract a portion where an adjacent wiring is constituted by a wiring having a weak driving ability and a wiring having a strong driving ability, which is apt to malfunction due to the influence of crosstalk. (Step S1
9). In step S20, the drive capacities of the respective drivers are compared with each other, and if there is a difference in drive capacity that exceeds a preset reference value, step S21.
Then, for the wiring having the smaller drive capacity, the ratio of the inter-wiring capacitance is calculated from the wiring capacitance obtained in step S11 and the inter-wiring capacitance obtained in step S13.

Next, in step S22, when the capacitance ratio between the wirings exceeds the preset reference ratio, the adjacent wiring is considered to be susceptible to the crosstalk noise, and the dangerous location net file is designated as the dangerous location. Store in 7.

Next, step S4 of FIG. 1 will be described with reference to the block diagram of FIG. 3 and the circuit diagram of FIG. In FIG. 3, the functional blocks 31 to 34 are provided in the mask pattern 30 of the semiconductor integrated circuit, and the target wirings 11 and 12 are provided between the functional block 31 and the functional block 34.
Is provided.

Further, in the circuit of FIG. 4, it is shown that the test circuit 10 tests the adjacent wirings 11 and 12, and the output signal 15 of the test circuit 10 is output from the external terminal 13. The adjacent wires 11 and 12 are adjacent wires that are easily affected by the crosstalk noise extracted in step S3 of FIG. The test circuit 10 is added for the purpose of generating a test pattern in which the value of this signal has an effect of an increase in delay due to crosstalk noise, the signal of the adjacent wiring 11 rises, and the signal of the adjacent wiring 12 falls.

The test circuit 10 simultaneously operates the adjacent wiring 1
The circuit specifications are such that the output signal 15 rises in an input combination in which the signal 1 rises and the signal on the adjacent wiring 12 falls. With respect to this circuit configuration, if a pattern is generated by the gate delay ATPG tool in step S5 of FIG. 1, a pattern for detecting the rising gate delay fault of the output signal 15 using the external terminal 13 is created. The output signal 15, which is affected by the increase in delay due to the talk noise, rises, and the wiring 1
The pattern that the signal of 2 falls is created. In this case, as expected values, the terminal 13 added as the test circuit 10 of FIG.
Is generated on all external terminals affected by.

The operation of this embodiment will be described. In the netlist having the logical function, a scan path is inserted in step S1 of FIG. 1, and a circuit as shown in the block diagram of FIG. 5 is inserted in a portion where the controllability of signals 0 and 1 is poor. As this test circuit, a flip-flop (hereinafter referred to as F / F) 22,
24 and F / Fs 26 and 27 synchronized with the clock signal 29.
And a synchronizing circuit 28 dependent on these F / Fs 26 and 27.
And a selector 23, 25 for switching the output of the synchronizing circuit 28 and the outputs of the F / Fs 22, 24 depending on the test mode of the test signal 21. With such a circuit, 100% controllability of 0 and 1 of the signals of the wirings 11 and 12 of FIG. 5 is guaranteed during the scan path test.

The net list 2 in which the scan path is inserted in step S1 of FIG. 1 is subjected to mask pattern layout in step S2 of FIG. 1 to form a mask pattern 30 of the semiconductor integrated circuit as shown in FIG. It
Subsequently, a dangerous point extraction process that is easily affected by the crosstalk noise in step S3 of FIG. 1 is performed. The adjacent wiring length is calculated in step S11 of FIG.
Based on the wiring length calculated in 12, the capacitance between adjacent wirings is calculated and compared with the reference value of the capacitance between wirings which varies according to the process set in advance by the designer, and step S13
In, the adjacent wiring exceeding the reference value is extracted.

In this embodiment, the mask pattern 40 shown in FIG.
The operation will be described by taking as an example the case where the adjacent wirings 11 and 12 in FIG. An enlarged view of the adjacent wirings 11 and 12 from the functional block 31 to the functional block 34 of FIG. 3 corresponds to FIG. 5, and for simplification of description,
Only relevant wiring is shown, and the others are not described. The wirings 11 and 12 in FIG. 3 correspond to the wirings 11 and 12 in FIG.

In step S1 of FIG. 1, the netlist 2 in which the scan path is inserted is input and reaches the logic gate from the clock terminals, set and reset terminals of all FFs in the netlist, or the external input terminal 13 is reached. Back trace is performed until it reaches or reaches FF, and the net in the trace is registered as a clock and reset wiring.
At the same time, those FFs are grouped for each logic gate at the root of the clock obtained by back tracing from the clock terminal or each external input terminal. Next, in step S16 of FIG. 2, the wiring whose inter-wiring capacitance extracted in step S12 exceeds the reference value is backtraced until it reaches the external input terminal or reaches FF, and the terminal of the drive source of the adjacent wiring is Alternatively, FF is extracted.

In step S17, step S14
It is judged whether it is not the signal name extracted in step 2 or whether the drive source FF belongs to the same group.
Adjacent wirings that operate in synchronization are extracted instead of the set and reset signals. The wiring 11 and the wiring 12 in FIG. 5 are the driving source FFs, and the FFs 26 and FFs operated by the clock signal 29.
27, which is extracted as a dangerous place.

Subsequently, in step S4 of FIG. 1, a test pattern is generated to generate a test pattern in which the signal on the wiring 11 in FIG. 5 rises and the signal on the wiring 12 falls such that the delay increases due to the influence of crosstalk. The circuit 10a is added. The test circuit 10a is a circuit in which the output signal Y rises when the input signal A rises and the input signal B falls.

FIG. 6 shows the test mode signals (TM1, TM2) from the input terminals 17, 18 of the test circuit 10a.
Is a truth table of the test circuit which outputs the output signals 15 and 16 (X, Y).

In the netlist to which the test circuit is added in step S4 of FIG. 1, a gate delay fault detection test pattern is generated by the gate delay ATPG tool in step S5 of FIG. 1, and at this time, the output Y of FIG. In the pattern for detecting the rising fault, a pattern in which the desired crosstalk is likely to appear in the signals of the wirings 11 and 12 is created.

Next, in step S6 of FIG.
Test mode, output signal 1 from input terminals 17 and 18
The pattern of 5.16 is deleted. Using the test pattern corrected in step S6 of FIG. 1, the manufacturing test of step S7 of FIG. 1 is performed.

FIG. 7 shows another embodiment of the present invention, the basic configuration of which is as described above, but the device for extracting the dangerous portion which may malfunction due to the influence of the crosstalk in step S3 of FIG. 1 is devised. The flow is shown. Steps 15 to 18 are deleted from FIG.

Also in this case, the wiring capacitance of each wiring is calculated in step S11, and in steps S12 to S14, the adjacent wirings in which the capacitance between adjacent wirings exceeds the designated reference value are extracted as in the above embodiment. Then step S
In 17a, the adjacent wiring extracted in step S14 is backtraced until it reaches the logic gate, and the driver of the corresponding adjacent wiring is extracted. In step S20, the drive capacities of the respective drivers are compared, and if there is a difference in drive capacity that exceeds a preset reference value, in step S21, the wiring capacity obtained in step S12 is determined for the wiring with the smaller drive capacity. Then, the ratio occupied by the inter-wiring capacitance is calculated from the inter-wiring capacitance obtained in step S13. Next, in step S22, when the ratio of the inter-wiring capacitance exceeds a preset reference value, the adjacent wiring is recognized as a dangerous place because it is susceptible to the crosstalk noise.

Therefore, the manufacturing test method using this dangerous point extraction processing is also effective in detecting a failure such that the influence of crosstalk does not act as a delay due to the simultaneous operation but malfunctions as noise.

[0036]

As described above, according to the present invention,
After inserting the scan path and laying out, extract the dangerous points that may malfunction due to the influence of crosstalk, and generate only the test pattern that shows the influence of crosstalk only at that point. Since this method uses a pattern to perform the manufacturing test, only the pattern combinations where the crosstalk effect can be tested in the manufacturing test are created only in the locations where the crosstalk effect is likely to appear. The pattern at the time of testing the failure at the time of manufacturing test is minimized, the test time therefor can be minimized, and the effect of improving the quality while suppressing the increase and decrease of the test cost to the minimum.

Further, in the conventional method, 16 patterns are required for the output gate delay fault detection of the 2-input logic gate and the fault detection due to the influence of crosstalk. It is possible to perform testing with a total of 4 patterns of 2 patterns for detecting rise and fall of the gate output and 2 patterns for testing the influence of crosstalk, which has the effect of reducing the test time and thereby the test cost.

[Brief description of drawings]

FIG. 1 is a schematic flow chart illustrating a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating detailed processing of FIG.

FIG. 3 is a layout plan view illustrating an arrangement of adjacent wirings in FIG.

FIG. 4 is a block diagram when testing the adjacent wiring of FIG. 1;

FIG. 5 is a block diagram when processing is performed by the additional circuit in FIG.

6 is a truth table illustrating the operation of the test circuit of FIG.

FIG. 7 is a schematic flowchart illustrating a second embodiment of the present invention.

FIG. 8 is a block diagram at the time of strike by the OR circuit of the conventional example.

[Explanation of symbols]

1,2 netlist 3 to 6 files 7 dangerous place net file 8 non-target files 10, 10a test circuit 11,12 wiring (adjacent wiring) 13, 14 External terminal 15, 16 output signal 17,18 Input terminal 21 Test signal 22, 24, 26, 27 flip-flops 23,25 selector 28 Synchronous circuit 29 clock signals 30 mask patterns 31-34 Function block 40 OR gate

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 21/822 G01R 31/28 V 27/04 H01L 21/82 C 27/04 T (56) Reference JP-A-3-208177 (JP, A) JP-A-2-238573 (JP, A) JP-A-10-308451 (JP, A) JP-A-11-44741 (JP, A) JP-A-5-35824 (JP, A) Kaihei 9-319779 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G01R 31/28-31/3193 G06F 17/50 H01L 21/82

Claims (9)

(57) [Claims] 1. A netlist satisfying a logical function is input, a scan path test structure is created, the netlist is subjected to a mask pattern layout, and a danger point in which the influence of crosstalk is likely to appear in the layout is extracted. A test circuit is added in order to create a test pattern with the gate delay ATPG so that the influence of crosstalk appears in the extracted dangerous points, and a manufacturing test is performed using the test pattern generated by performing the gate delay ATPG in the circuit. A method for testing a semiconductor integrated circuit, comprising: 2. A scan flip-flop or an external terminal is added to a portion of the netlist where controllability to 0 or 1 or observability is not sufficient after the scan path test structure is formed. The method for testing a semiconductor integrated circuit according to claim 1, wherein a process for improving control and observability is added. 3. The semiconductor integrated circuit according to claim 2, wherein a netlist satisfying a logical function with a scan path inserted is input, a mask pattern layout is performed, and adjacent wirings which are easily affected by crosstalk noise are extracted as dangerous points. Circuit testing method. 4. The extraction of the adjacent wiring at the dangerous place is performed by extracting the wiring capacitance and wiring length of each wiring, calculating the capacitance between the adjacent wirings, and selecting the adjacent wiring whose capacitance between the adjacent wirings exceeds a predetermined reference value. 4. The method for testing a semiconductor integrated circuit according to claim 3, wherein the testing is performed. 5. Extraction of adjacent wiring at a dangerous place is performed by dividing the flip-flops that are the same drive source into groups based on the back trace results of the clock terminals of all the flip-flops, and determining that the adjacent wirings in the same group have a synchronous relationship. 4. The method for testing a semiconductor integrated circuit according to claim 3, wherein the testing is performed. 6. The extraction of adjacent wirings at a dangerous place has a difference in drive capacity between adjacent wirings equal to or larger than a reference value, and the ratio of inter-wiring capacity to the wiring capacity of the wiring having a smaller drive capacity is a predetermined reference value. 5. The method of taking out more than 4 pieces and carrying out
Alternatively, the method for testing a semiconductor integrated circuit as described in 5 above. 7. A test circuit for converting the extracted input signal of the logic gate to the adjacent wiring into a signal value transition that is apt to cause crosstalk noise by using a gate delay ATPG tool, and displaying information of a dangerous point. The method for testing a semiconductor integrated circuit according to claim 1, wherein the method is used to add to a net list. 8. A gate delay ATPG tool
8. The method for testing a semiconductor integrated circuit according to claim 7, wherein the test circuit is used to generate a test pattern in which the input signal of the extracted logic gate has a signal value in which crosstalk noise easily occurs. 9. The method for testing a semiconductor integrated circuit according to claim 7, wherein the test pattern is corrected by deleting the expected value at the external terminal of the added test circuit, and the semiconductor integrated circuit is tested by the corrected test pattern.