JP3467787B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a MOS transistor having a floating gate is formed, and more specifically, the threshold of a parasitic transistor in a MOS transistor without increasing the number of masks. The present invention relates to a method of ion implantation for a channel stopper capable of increasing the value voltage.

[0002]

2. Description of the Related Art In the process of manufacturing a semiconductor device in which a MOS transistor having a floating gate is formed, a selective oxidation element isolation region (L
OCOS) is formed, and a channel stopper region is formed below the LOCOS. The channel stopper region is formed by implanting impurity ions into the surface of the semiconductor substrate and then performing heat treatment.

Conventionally, the ion implantation for the channel stopper has been carried out before the formation of LOCOS by using a silicon nitride film as a mask for preventing oxidation for forming LOCOS. According to this method, the impurity ion-implanted for the channel stopper is simultaneously diffused by the heat treatment for forming the LOCOS.

[0004]

However, in such a conventional method, LOCOS oxidation is performed after the ion implantation when the N-type channel stopper ion implantation using boron (B) is performed, for example. However, there is a problem that the concentration of boron is lowered and the effect of increasing the threshold voltage of the parasitic transistor generated in the MOS transistor is weakened. When the threshold voltage of the parasitic transistor decreases, there is a problem that the characteristics of the original MOS transistor deteriorate. Further, there is a possibility that boron will diffuse into the channel region of the MOS transistor, in which case there is a problem that the effective channel width becomes smaller (narrow channel effect). Further, there is a problem that the channel stopper region is segregated and eaten with respect to LOCOS.

The present invention has been made in view of such circumstances, and a semiconductor device capable of increasing the threshold voltage of a parasitic transistor with respect to a MOS transistor and improving the characteristics of the transistor without increasing the number of masks. It aims at providing the manufacturing method of.

[0006]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a first conductive layer which becomes a floating gate after forming a selective oxidation element isolation region on the surface of a semiconductor substrate. Forming a film and then the first
Using the resist film as a mask to pattern the conductive film,
Ion implantation for a channel stopper is performed below the selective oxidation element isolation region formed in the memory cell region and a specific peripheral circuit region .

In the present invention, the ion implantation for the channel stopper after the formation of the selective oxidation element isolation region can be performed only to the selective oxidation element isolation region formed in the memory cell region and the specific peripheral circuit. Ion implantation for a channel stopper may be performed in the selective oxidation element isolation region existing in a specific peripheral circuit area even before the selective oxidation element isolation region is formed. Further, the overlapping width of the resist film for ion implantation for the channel stopper performed after the formation of the selective oxidation element isolation region and the selective oxidation element isolation region can be made larger in the peripheral circuit region than in the memory cell region. .

[0008]

In the method of manufacturing a semiconductor device of the present invention, since the channel stopper ion implantation is performed after the selective oxidation element isolation region is formed, impurities in the channel stopper region are removed during the thermal oxidation for forming the selective oxidation element isolation region. The diffusion layer is never thinned. Further, the impurities in the channel stopper region will not diffuse to the channel region of the MOS transistor. Therefore, the narrow channel effect can be suppressed, and the MOS transistor can be miniaturized. Further, the impurities in the channel stopper region will not be segregated in the selective oxidation element isolation region.

Further, according to the present invention, the resist film for patterning the first conductive film is used as a mask to perform the ion implantation for the channel stopper below the selective oxidation element isolation region. Nor. When a memory device is manufactured by using the method of the present invention, it becomes possible to optimize the ion implantation conditions for the channel stopper separately in the memory cell region and the peripheral circuit region, and it is possible to optimize the ion implantation conditions for each region. It is possible to form various MOS transistors.

In particular, the overlapping width of the resist film for ion implantation for the channel stopper performed after the formation of the selective oxidation element isolation region and the selective oxidation element isolation region is made larger in the peripheral circuit region than in the memory cell region. According to the present invention, in the transistor in the peripheral circuit region, the distance between the channel region and the channel stopper region is increased, and the breakdown voltage of the transistor is improved. On the other hand, in the transistor in the memory cell region, the threshold voltage of the parasitic transistor is improved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail below with reference to the drawings.
1 and 2 are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the present invention, FIG. 3 is a plan view showing an example of a mask pattern of a resist film for processing a first conductive film, FIG. FIG. 7 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

A semiconductor device manufactured by a manufacturing method according to an embodiment of the present invention is a method for manufacturing a semiconductor device in which a MOS transistor having a floating gate such as an EPROM or an E ² PROM is formed. , Manufactured by the process described below.

First, as shown in FIG. 1A, a semiconductor substrate 2 is first prepared. The semiconductor substrate 2 is not particularly limited, but a P-type silicon single crystal substrate is used, for example. The semiconductor substrate 2 may be an N-type silicon single crystal substrate. In that case, the conductivity types of the impurities used at the time of ion implantation for the channel stopper described later have opposite polarities.

Next, the pad insulating film 4 is formed on the surface of the semiconductor substrate 2 by, for example, a thermal oxidation method. The pad insulating film 4 is formed of, for example, a silicon oxide film having a thickness of 50 nm. Oxidation prevention films 6a and 6b for forming selective oxidation element isolation regions (LOCOS) are formed in a predetermined pattern on the surface of the pad insulating film 4. The oxidation prevention films 6a and 6b are composed of, for example, a silicon nitride film formed by a CVD method.

Next, in this embodiment, the surface of the semiconductor substrate 2 is covered with a resist film 8 and the resist film 8 is patterned so that the peripheral circuit region S except the memory cell region M is opened. In this state, the first stage ion implantation for the channel stopper is performed. That is, in the peripheral circuit region other than the memory cell region M, the channel stopper ion implantation before the LOCOS formation is performed as in the conventional case. This is because the transistors in the peripheral circuit region S are larger than those in the memory cell region M, and the breakdown voltage must be improved rather than increasing the threshold voltage of the parasitic transistor.

Boron (B), for example, is used as the impurity used for the ion implantation for the channel stopper in the first step, and the implantation energy is, for example, about 25 KeV. By this ion implantation, impurities are introduced into the portion 10 where the LOCOS is formed in the peripheral circuit region S.

Next, as shown in FIG. 1B, the resist film 8 is removed, and the surface of the semiconductor substrate 2 is thermally oxidized by the LOCOS method to form a pattern in which the oxidation prevention films 6a and 6b are not formed. LOCOS (selective oxidation element isolation region) 12 corresponding to is formed. The film thickness of LOCOS 12 is
For example, it is about 400 to 500 nm. Under the LOCOS 12 in the peripheral circuit region S, the first channel stopper region 14 is formed by thermally diffusing the impurities ion-implanted in the step shown in FIG. After the LOCOS process, the oxidation prevention films 6a and 6b are removed.

In the present embodiment, next, as shown in FIG. 6C, the pad insulating film 4 is removed and the gate insulating film 16 is formed.
It is formed on the surface of the semiconductor substrate 2 located between the LOCOS 12. The gate insulating film 16 is formed by thermally oxidizing the surface of the semiconductor substrate 2, and is made of, for example, a silicon oxide film having a thickness of about 10 nm.

A first conductive film 18 to be a floating gate is formed on the surface of the gate insulating film 16 made of a silicon oxide film. The first conductive film 18 is formed of a functional thin film having conductivity, and is formed of, for example, a polysilicon film having a thickness of about 100 nm formed by CVD. First
Since the conductive film 18 becomes a floating gate in the memory cell region M, the resist film 20 is first patterned.

In this embodiment, the LOC is used by using the resist film 20 for patterning the first conductive film 18 as a mask.
In order to perform the second-stage channel stopper ion implantation below the OS 12, in the memory cell region M, the ion implantation opening 22a is formed on the LOCOS 12 by etching such as RIE in a pattern as shown in FIG. It In FIG. 3, reference numeral 24 indicates a pattern of the control gate stacked on the floating gate via the intermediate insulating film. The first conductive film 18 is continuously patterned when the second conductive film forming the control gate 24 is processed in the pattern shown in FIG. 3, and finally has a shape along the control gate 24. .

As shown in FIG. 1C, the resist film 20
Thus, when patterning the first conductive film 18, the opening 22a is formed in the memory cell region M, but also in the peripheral circuit region S, for example, on the LOCOS 12 of a specific transistor for which a breakdown voltage is particularly required. , The ion implantation openings 22b are simultaneously formed.

Next, using the resist film 20 used for this pattern processing as a mask, second-stage channel stopper ion implantation is performed below the LOCOS 12 through the openings 22a and 22b. The conductivity type of the impurities used in the ion implantation for the channel stopper in the second stage is the same as the conductivity type of the impurities used in the ion implantation for the channel stopper in the first stage, and, for example, boron (B) is used. The ion implantation energy is high, for example, 300 KeV or more because the ion implantation is performed on the lower portion of the LOCOS 12. The dose amount of impurities to be ion-implanted is, for example, about 1 × 10 ¹³ cm ^-2 .

Thereafter, as shown in FIG. 2, if heat treatment is performed, L is added at the time of ion implantation for the second step of channel stopper.
Impurities introduced under the OCOS 12 are thermally diffused and the second
The channel stopper region 24 is formed. The second channel stopper region 24 is formed to a deeper and deeper concentration than the first channel stopper region 14.

Thereafter, in the memory cell region M, an intermediate insulating film and a control gate are formed based on a normal manufacturing process of a semiconductor device having a floating gate. Further, in the peripheral circuit region S, the first conductive film 18 and the gate insulating film 16 are removed, and when the intermediate insulating film and the control gate are formed in the memory cell region M, the same functional thin films as those are used for the peripheral circuit. A gate insulating film and a gate electrode of the transistor are formed. Also in the peripheral circuit region S, the first conductive film may form the gate electrode of the transistor in the peripheral circuit region S. Generally, it is preferable that the film thickness of the gate of the transistor in the peripheral circuit region S is thicker than that of the first conductive film 18. Therefore, the gate of the transistor in the peripheral circuit region S is formed by the second conductive film forming the control gate. To be done.

In this embodiment, the LOCOS 12 for separating the memory cell transistor T _rm in the memory cell region M from each other is isolated.
A second channel stopper region 24 having a higher concentration and a deeper concentration than the first channel stopper region 14 is formed in the lower portion. Therefore, in the memory cell region M, the memory cell M
The threshold voltage V _th of the parasitic transistor formed with respect to the OS transistor T _rm can be set high, and the characteristics of the memory cell transistor T _rm are improved.
In addition, a specific transistor T in the peripheral circuit region S
The first channel stopper region 14 and the second channel stopper region 24 can be formed so as to overlap with _rs1 , and the breakdown voltage of the transistor can be improved. The transistor T _rm in the memory cell region M is
Since only the second channel stopper region 24 is formed, the breakdown voltage may decrease, but it does not pose a problem because the breakdown voltage of the transistor in the memory cell region is about 8 to 9 volts. In the memory cell transistor, it is important to improve the threshold voltage V _th of the parasitic transistor rather than the breakdown voltage.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention. For example, in the embodiment described above, FIG.
In the step shown in (A), the memory cell region M was masked with the resist film 8 and only the peripheral circuit region S was subjected to the first-stage channel stopper ion implantation. However, in the present invention, the first-step channel stopper ion implantation is not necessarily an essential step, and the first-step channel stopper ion implantation is abolished, and the lower part of all LOCOS 12 formed on the surface of the semiconductor substrate 2 is abolished. On the other hand, only the second-stage channel stopper ion implantation shown in FIG. 1C may be performed. In the case of that embodiment, the step of forming and patterning the resist film 5 and the first step of ion implantation for channel stopper shown in FIG. 1A are unnecessary.

Further, according to the present invention, an embodiment as shown in FIG. 4 is considered as a modified example of the embodiment in which the ion implantation for the channel stopper in the first stage is implanted in the peripheral circuit region S and the memory cell region M. To be

In the embodiment shown in FIG. 4, the overlapping width t _s of the resist film 20 for the ion implantation for the second stage channel stopper performed after the formation of the LOCOS 12 and the LOCOS 12 is the overlapping width t of the memory cell region M. _The peripheral circuit area S is designed to be larger than _m . Figure 4 (A)
As shown in FIG. 5, in the peripheral circuit region S, the overlapping width t _s is large, and as a result, the breakdown voltage of the peripheral transistor T _rs1 is significantly improved. This is because the first channel stopper region 14 is formed in the portion corresponding to the overlapping width t _s , and the impurity concentration thereof is lower than that of the second channel stopper region 24. Further, the first channel stopper region 14 existing in the peripheral circuit S has the peripheral circuit transistor _Trs1.
It also has an effect of suppressing the narrow channel effect.

As shown in FIG. 4B, the overlap width t _m is narrow in the memory cell region due to the demand for high integration.
By the action of the channel stopper region 24, the threshold voltage of the parasitic transistor of the memory cell transistor T _rm can be set high, and the narrow channel effect due to miniaturization can be suppressed.

In FIG. 4, reference numeral 30 indicates an intermediate insulating film of the memory cell transistor, reference numeral 32 indicates a second conductive film which serves as a control gate of the memory cell transistor, and is formed of, for example, a polysilicon film. . In the example shown in FIG. 4, the second conductive film 32 serves as the gate electrode of the transistor in the peripheral circuit region. Other symbols shown in FIG.
Since it is common with the embodiment shown in FIGS.

[0031]

As described above, according to the present invention, since the ion implantation for the channel stopper is performed after the selective oxidation element isolation region is formed, during the thermal oxidation for forming the selective oxidation element isolation region, The impurity diffusion layer in the channel stopper region is never thinned. As a result, MO
The threshold voltage of the parasitic transistor in the S transistor does not rise, and the characteristics of the MOS transistor do not deteriorate. Further, the impurities in the channel stopper region do not diffuse to the channel region of the MOS transistor, so that the narrow channel effect can be suppressed and the MOS transistor can be miniaturized. Further, the impurities in the channel stopper region will not be segregated in the selective oxidation element isolation region.

Further, in the present invention, since the ion implantation for the channel stopper is performed below the selective oxidation element isolation region using the resist film for patterning the first conductive film as a mask, it is necessary to increase the number of masks specially. Nor.

When a memory device is manufactured using the method of the present invention, the ion implantation conditions for the channel stopper can be optimized separately in the memory cell region and the peripheral circuit region, and each can be optimized. It becomes possible to form an optimum MOS transistor in the region. Further, when the method of the present invention is used, the effective channel width of the memory cell MOS transistor, which is particularly limited in terms of cell size, can be widened, so that the channel width in the layout can be reduced, and the cell size can be reduced. Is possible. Further, by devising a patterning process of the first conductive film, it becomes possible to perform ion implantation for the channel stopper after the selective oxidation element isolation region is formed, in the specific MOS transistor selective oxidation element isolation region in the peripheral circuit region. It is possible to improve the breakdown voltage of the transistor. Therefore, the degree of freedom in process design is expanded.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 2 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment.

FIG. 3 is a plan view showing an example of a mask pattern of a resist film for processing the first conductive film.

FIG. 4 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

2 ... Semiconductor substrate 12 ... Selective oxidation element isolation region (LOCOS) 14 ... First channel stopper region 16 ... Gate insulating film 18 ... First conductive film 20 ... Resist films 22a, 22b ... Ion implantation opening 24 ... Second channel Stopper area M ... Memory cell area S ... Peripheral circuit area _Trm ... Memory cell transistors _Trs1 , _Trs2 ... Peripheral circuit transistor

Continuation of front page (51) Int.Cl. ⁷ identification code FI H01L 29/788 29/792 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/76 H01L 21/316 H01L 21/8247 H01L 27/10 481 H01L 27/115 H01L 29/788 H01L 29/792

Claims (3)

(57) [Claims] 1. A memory cell area and a peripheral circuit area are included,
The MOS transistor having a rotating gate is
In a method of manufacturing a semiconductor device formed in a memory cell region , a selective oxidation element isolation region is formed on a surface of a semiconductor substrate, a first conductive film to be a floating gate is formed, and then the first conductive film is formed. A method of manufacturing a semiconductor device, wherein ion implantation for a channel stopper is performed below a selective oxidation element isolation region formed in a memory cell region and a specific peripheral circuit region, using a resist film to be patterned as a mask. 2. An ion implantation for a channel stopper is performed in a selective oxidation element isolation region existing in a specific peripheral circuit area even before the selective oxidation element isolation region is formed. 1. The method for manufacturing a semiconductor device according to 1. 3. The overlap width of a resist film for ion implantation for a channel stopper performed after the formation of the selective oxidation element isolation region and the selective oxidation element isolation region is larger in the peripheral circuit region than in the memory cell region. The method for manufacturing a semiconductor device according to claim 1, wherein